Commit 1682bd1a authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher

drm/amd/display: Expand kernel doc for DC

This commit adds extra documentation for elements related to FAMs.
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Reviewed-by: default avatarAurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1a98cf8
...@@ -494,9 +494,12 @@ enum dcn_zstate_support_state { ...@@ -494,9 +494,12 @@ enum dcn_zstate_support_state {
DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
DCN_ZSTATE_SUPPORT_DISALLOW, DCN_ZSTATE_SUPPORT_DISALLOW,
}; };
/*
* For any clocks that may differ per pipe /**
* only the max is stored in this structure * dc_clocks - DC pipe clocks
*
* For any clocks that may differ per pipe only the max is stored in this
* structure
*/ */
struct dc_clocks { struct dc_clocks {
int dispclk_khz; int dispclk_khz;
...@@ -523,6 +526,16 @@ struct dc_clocks { ...@@ -523,6 +526,16 @@ struct dc_clocks {
bool prev_p_state_change_support; bool prev_p_state_change_support;
bool fclk_prev_p_state_change_support; bool fclk_prev_p_state_change_support;
int num_ways; int num_ways;
/**
* @fw_based_mclk_switching
*
* DC has a mechanism that leverage the variable refresh rate to switch
* memory clock in cases that we have a large latency to achieve the
* memory clock change and a short vblank window. DC has some
* requirements to enable this feature, and this field describes if the
* system support or not such a feature.
*/
bool fw_based_mclk_switching; bool fw_based_mclk_switching;
bool fw_based_mclk_switching_shut_down; bool fw_based_mclk_switching_shut_down;
int prev_num_ways; int prev_num_ways;
......
...@@ -201,7 +201,18 @@ struct dc_stream_state { ...@@ -201,7 +201,18 @@ struct dc_stream_state {
bool use_vsc_sdp_for_colorimetry; bool use_vsc_sdp_for_colorimetry;
bool ignore_msa_timing_param; bool ignore_msa_timing_param;
/**
* @allow_freesync:
*
* It say if Freesync is enabled or not.
*/
bool allow_freesync; bool allow_freesync;
/**
* @vrr_active_variable:
*
* It describes if VRR is in use.
*/
bool vrr_active_variable; bool vrr_active_variable;
bool freesync_on_desktop; bool freesync_on_desktop;
......
...@@ -29,6 +29,13 @@ ...@@ -29,6 +29,13 @@
#define DC__PRESENT 1 #define DC__PRESENT 1
#define DC__PRESENT__1 1 #define DC__PRESENT__1 1
#define DC__NUM_DPP 4 #define DC__NUM_DPP 4
/**
* @DC__VOLTAGE_STATES:
*
* Define the maximum amount of states supported by the ASIC. Every ASIC has a
* specific number of states; this macro defines the maximum number of states.
*/
#define DC__VOLTAGE_STATES 20 #define DC__VOLTAGE_STATES 20
#define DC__NUM_DPP__4 1 #define DC__NUM_DPP__4 1
#define DC__NUM_DPP__0_PRESENT 1 #define DC__NUM_DPP__0_PRESENT 1
......
...@@ -105,14 +105,39 @@ enum source_macro_tile_size { ...@@ -105,14 +105,39 @@ enum source_macro_tile_size {
enum cursor_bpp { enum cursor_bpp {
dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2 dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
}; };
/**
* @enum clock_change_support - It represents possible reasons to change the DRAM clock.
*
* DC may change the DRAM clock during its execution, and this enum tracks all
* the available methods. Note that every ASIC has their specific way to deal
* with these clock switch.
*/
enum clock_change_support { enum clock_change_support {
/**
* @dm_dram_clock_change_uninitialized: If you see this, we might have
* a code initialization issue
*/
dm_dram_clock_change_uninitialized = 0, dm_dram_clock_change_uninitialized = 0,
/**
* @dm_dram_clock_change_vactive: Support DRAM switch in VActive
*/
dm_dram_clock_change_vactive, dm_dram_clock_change_vactive,
/**
* @dm_dram_clock_change_vblank: Support DRAM switch in VBlank
*/
dm_dram_clock_change_vblank, dm_dram_clock_change_vblank,
dm_dram_clock_change_vactive_w_mall_full_frame, dm_dram_clock_change_vactive_w_mall_full_frame,
dm_dram_clock_change_vactive_w_mall_sub_vp, dm_dram_clock_change_vactive_w_mall_sub_vp,
dm_dram_clock_change_vblank_w_mall_full_frame, dm_dram_clock_change_vblank_w_mall_full_frame,
dm_dram_clock_change_vblank_w_mall_sub_vp, dm_dram_clock_change_vblank_w_mall_sub_vp,
/**
* @dm_dram_clock_change_unsupported: Do not support DRAM switch
*/
dm_dram_clock_change_unsupported dm_dram_clock_change_unsupported
}; };
......
...@@ -419,6 +419,15 @@ struct vba_vars_st { ...@@ -419,6 +419,15 @@ struct vba_vars_st {
double MinPixelChunkSizeBytes; double MinPixelChunkSizeBytes;
unsigned int DCCMetaBufferSizeBytes; unsigned int DCCMetaBufferSizeBytes;
// Pipe/Plane Parameters // Pipe/Plane Parameters
/** @VoltageLevel:
* Every ASIC has a fixed number of DPM states, and some devices might
* have some particular voltage configuration that does not map
* directly to the DPM states. This field tells how many states the
* target device supports; even though this field combines the DPM and
* special SOC voltages, it mostly matches the total number of DPM
* states.
*/
int VoltageLevel; int VoltageLevel;
double FabricClock; double FabricClock;
double DRAMSpeed; double DRAMSpeed;
......
...@@ -115,6 +115,13 @@ struct resource_funcs { ...@@ -115,6 +115,13 @@ struct resource_funcs {
int vlevel); int vlevel);
void (*update_soc_for_wm_a)( void (*update_soc_for_wm_a)(
struct dc *dc, struct dc_state *context); struct dc *dc, struct dc_state *context);
/**
* @populate_dml_pipes - Populate pipe data struct
*
* Returns:
* Total of pipes available in the specific ASIC.
*/
int (*populate_dml_pipes)( int (*populate_dml_pipes)(
struct dc *dc, struct dc *dc,
struct dc_state *context, struct dc_state *context,
......
...@@ -35,6 +35,13 @@ ...@@ -35,6 +35,13 @@
******************************************************************************/ ******************************************************************************/
#define MAX_AUDIOS 7 #define MAX_AUDIOS 7
/**
* @MAX_PIPES:
*
* Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
* to be used inside loops and for determining array sizes.
*/
#define MAX_PIPES 6 #define MAX_PIPES 6
#define MAX_DIG_LINK_ENCODERS 7 #define MAX_DIG_LINK_ENCODERS 7
#define MAX_DWB_PIPES 1 #define MAX_DWB_PIPES 1
......
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