Commit 16dc224f authored by Chris Wilson's avatar Chris Wilson

drm/i915: Replace the hardcoded I915_FENCE_TIMEOUT

Expose the hardcoded timeout for unsignaled foreign fences as a Kconfig
option, primarily to allow brave systems to disable the timeout and
solely rely on correct signaling.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Acked-by: default avatarMichael J. Ruhl <michael.j.ruhl@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200509105021.12542-1-chris@chris-wilson.co.uk
parent fcae4961
config DRM_I915_FENCE_TIMEOUT
int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
default 10000 # milliseconds
help
When listening to a foreign fence, we install a supplementary timer
to ensure that we are always signaled and our userspace is able to
make forward progress. This value specifies the timeout used for an
unsignaled foreign fence.
May be 0 to disable the timeout, and rely on the foreign fence being
eventually signaled.
config DRM_I915_USERFAULT_AUTOSUSPEND config DRM_I915_USERFAULT_AUTOSUSPEND
int "Runtime autosuspend delay for userspace GGTT mmaps (ms)" int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
default 250 # milliseconds default 250 # milliseconds
......
...@@ -35,6 +35,7 @@ subdir-ccflags-y += -I$(srctree)/$(src) ...@@ -35,6 +35,7 @@ subdir-ccflags-y += -I$(srctree)/$(src)
# core driver code # core driver code
i915-y += i915_drv.o \ i915-y += i915_drv.o \
i915_config.o \
i915_irq.o \ i915_irq.o \
i915_getparam.o \ i915_getparam.o \
i915_params.o \ i915_params.o \
......
...@@ -15815,7 +15815,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, ...@@ -15815,7 +15815,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
if (new_plane_state->uapi.fence) { /* explicit fencing */ if (new_plane_state->uapi.fence) { /* explicit fencing */
ret = i915_sw_fence_await_dma_fence(&state->commit_ready, ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
new_plane_state->uapi.fence, new_plane_state->uapi.fence,
I915_FENCE_TIMEOUT, i915_fence_timeout(dev_priv),
GFP_KERNEL); GFP_KERNEL);
if (ret < 0) if (ret < 0)
return ret; return ret;
...@@ -15842,7 +15842,8 @@ intel_prepare_plane_fb(struct drm_plane *_plane, ...@@ -15842,7 +15842,8 @@ intel_prepare_plane_fb(struct drm_plane *_plane,
ret = i915_sw_fence_await_reservation(&state->commit_ready, ret = i915_sw_fence_await_reservation(&state->commit_ready,
obj->base.resv, NULL, obj->base.resv, NULL,
false, I915_FENCE_TIMEOUT, false,
i915_fence_timeout(dev_priv),
GFP_KERNEL); GFP_KERNEL);
if (ret < 0) if (ret < 0)
goto unpin_fb; goto unpin_fb;
......
...@@ -108,7 +108,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, ...@@ -108,7 +108,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
if (clflush) { if (clflush) {
i915_sw_fence_await_reservation(&clflush->base.chain, i915_sw_fence_await_reservation(&clflush->base.chain,
obj->base.resv, NULL, true, obj->base.resv, NULL, true,
I915_FENCE_TIMEOUT, i915_fence_timeout(to_i915(obj->base.dev)),
I915_FENCE_GFP); I915_FENCE_GFP);
dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma); dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
dma_fence_work_commit(&clflush->base); dma_fence_work_commit(&clflush->base);
......
...@@ -288,8 +288,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, ...@@ -288,8 +288,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
i915_gem_object_lock(obj); i915_gem_object_lock(obj);
err = i915_sw_fence_await_reservation(&work->wait, err = i915_sw_fence_await_reservation(&work->wait,
obj->base.resv, NULL, obj->base.resv, NULL, true, 0,
true, I915_FENCE_TIMEOUT,
I915_FENCE_GFP); I915_FENCE_GFP);
if (err < 0) { if (err < 0) {
dma_fence_set_error(&work->dma, err); dma_fence_set_error(&work->dma, err);
......
...@@ -72,8 +72,8 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object *obj) ...@@ -72,8 +72,8 @@ i915_gem_object_lock_fence(struct drm_i915_gem_object *obj)
0, 0); 0, 0);
if (i915_sw_fence_await_reservation(&stub->chain, if (i915_sw_fence_await_reservation(&stub->chain,
obj->base.resv, NULL, obj->base.resv, NULL, true,
true, I915_FENCE_TIMEOUT, i915_fence_timeout(to_i915(obj->base.dev)),
I915_FENCE_GFP) < 0) I915_FENCE_GFP) < 0)
goto err; goto err;
......
// SPDX-License-Identifier: MIT
/*
* Copyright © 2020 Intel Corporation
*/
#include "i915_drv.h"
unsigned long
i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context)
{
if (context && IS_ACTIVE(CONFIG_DRM_I915_FENCE_TIMEOUT))
return msecs_to_jiffies_timeout(CONFIG_DRM_I915_FENCE_TIMEOUT);
return 0;
}
...@@ -614,8 +614,16 @@ struct i915_gem_mm { ...@@ -614,8 +614,16 @@ struct i915_gem_mm {
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
u64 context);
static inline unsigned long
i915_fence_timeout(const struct drm_i915_private *i915)
{
return i915_fence_context_timeout(i915, U64_MAX);
}
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
......
...@@ -1098,7 +1098,8 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) ...@@ -1098,7 +1098,8 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
{ {
mark_external(rq); mark_external(rq);
return i915_sw_fence_await_dma_fence(&rq->submit, fence, return i915_sw_fence_await_dma_fence(&rq->submit, fence,
fence->context ? I915_FENCE_TIMEOUT : 0, i915_fence_context_timeout(rq->i915,
fence->context),
I915_FENCE_GFP); I915_FENCE_GFP);
} }
......
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