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Commit 178a6c16 authored by Juerg Haefliger's avatar Juerg Haefliger Committed by Stefan Bader
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UBUNTU: SAUCE: perf/x86/{cstate,rapl,uncore}: Use Intel Model name macros 

There are a few more places in Xenial 4.4 that still use open-coded
magic numbers instead of the new model name macros. Fix that.

CVE-2018-12126
CVE-2018-12127
CVE-2018-12130
Signed-off-by: default avatarJuerg Haefliger <juergh@canonical.com>
Acked-by: default avatarTyler Hicks <tyhicks@canonical.com>
Acked-by: default avatarStefan Bader <stefan.bader@canonical.com>
Signed-off-by: default avatarStefan Bader <stefan.bader@canonical.com>
parent edf2c1c1
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Inline Side-by-side
Showing with 91 additions and 88 deletions
arch/x86/events/intel/cstate.c
View file @ 178a6c16
......@@ -90,6 +90,7 @@
#include <linux/perf_event.h>
#include <linux/nospec.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include "../perf_event.h"
#define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \
......@@ -138,43 +139,43 @@ bool test_core(int idx)
return false;
switch (boot_cpu_data.x86_model) {
case 30: /* 45nm Nehalem */
case 26: /* 45nm Nehalem-EP */
case 46: /* 45nm Nehalem-EX */
case INTEL_FAM6_NEHALEM:
case INTEL_FAM6_NEHALEM_EP:
case INTEL_FAM6_NEHALEM_EX:
case 37: /* 32nm Westmere */
case 44: /* 32nm Westmere-EP */
case 47: /* 32nm Westmere-EX */
case INTEL_FAM6_WESTMERE:
case INTEL_FAM6_WESTMERE_EP:
case INTEL_FAM6_WESTMERE_EX:
if (idx == PERF_CSTATE_CORE_C3_RES ||
idx == PERF_CSTATE_CORE_C6_RES)
return true;
break;
case 42: /* 32nm SandyBridge */
case 45: /* 32nm SandyBridge-E/EN/EP */
case INTEL_FAM6_SANDYBRIDGE:
case INTEL_FAM6_SANDYBRIDGE_X:
case 58: /* 22nm IvyBridge */
case 62: /* 22nm IvyBridge-EP/EX */
case INTEL_FAM6_IVYBRIDGE:
case INTEL_FAM6_IVYBRIDGE_X:
case 60: /* 22nm Haswell Core */
case 63: /* 22nm Haswell Server */
case 69: /* 22nm Haswell ULT */
case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
case INTEL_FAM6_HASWELL_CORE:
case INTEL_FAM6_HASWELL_X:
case INTEL_FAM6_HASWELL_ULT:
case INTEL_FAM6_HASWELL_GT3E:
case 61: /* 14nm Broadwell Core-M */
case 86: /* 14nm Broadwell Xeon D */
case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
case 79: /* 14nm Broadwell Server */
case INTEL_FAM6_BROADWELL_CORE:
case INTEL_FAM6_BROADWELL_XEON_D:
case INTEL_FAM6_BROADWELL_GT3E:
case INTEL_FAM6_BROADWELL_X:
case 78: /* 14nm Skylake Mobile */
case 94: /* 14nm Skylake Desktop */
case INTEL_FAM6_SKYLAKE_MOBILE:
case INTEL_FAM6_SKYLAKE_DESKTOP:
if (idx == PERF_CSTATE_CORE_C3_RES ||
idx == PERF_CSTATE_CORE_C6_RES ||
idx == PERF_CSTATE_CORE_C7_RES)
return true;
break;
case 55: /* 22nm Atom "Silvermont" */
case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
case 76: /* 14nm Atom "Airmont" */
case INTEL_FAM6_ATOM_SILVERMONT1:
case INTEL_FAM6_ATOM_SILVERMONT2:
case INTEL_FAM6_ATOM_AIRMONT:
if (idx == PERF_CSTATE_CORE_C1_RES ||
idx == PERF_CSTATE_CORE_C6_RES)
return true;
......@@ -265,48 +266,48 @@ bool test_pkg(int idx)
return false;
switch (boot_cpu_data.x86_model) {
case 30: /* 45nm Nehalem */
case 26: /* 45nm Nehalem-EP */
case 46: /* 45nm Nehalem-EX */
case INTEL_FAM6_NEHALEM:
case INTEL_FAM6_NEHALEM_EP:
case INTEL_FAM6_NEHALEM_EX:
case 37: /* 32nm Westmere */
case 44: /* 32nm Westmere-EP */
case 47: /* 32nm Westmere-EX */
case INTEL_FAM6_WESTMERE:
case INTEL_FAM6_WESTMERE_EP:
case INTEL_FAM6_WESTMERE_EX:
if (idx == PERF_CSTATE_CORE_C3_RES ||
idx == PERF_CSTATE_CORE_C6_RES ||
idx == PERF_CSTATE_CORE_C7_RES)
return true;
break;
case 42: /* 32nm SandyBridge */
case 45: /* 32nm SandyBridge-E/EN/EP */
case INTEL_FAM6_SANDYBRIDGE:
case INTEL_FAM6_SANDYBRIDGE_X:
case 58: /* 22nm IvyBridge */
case 62: /* 22nm IvyBridge-EP/EX */
case INTEL_FAM6_IVYBRIDGE:
case INTEL_FAM6_IVYBRIDGE_X:
case 60: /* 22nm Haswell Core */
case 63: /* 22nm Haswell Server */
case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
case INTEL_FAM6_HASWELL_CORE:
case INTEL_FAM6_HASWELL_X:
case INTEL_FAM6_HASWELL_GT3E:
case 61: /* 14nm Broadwell Core-M */
case 86: /* 14nm Broadwell Xeon D */
case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
case 79: /* 14nm Broadwell Server */
case INTEL_FAM6_BROADWELL_CORE:
case INTEL_FAM6_BROADWELL_XEON_D:
case INTEL_FAM6_BROADWELL_GT3E:
case INTEL_FAM6_BROADWELL_X:
case 78: /* 14nm Skylake Mobile */
case 94: /* 14nm Skylake Desktop */
case INTEL_FAM6_SKYLAKE_MOBILE:
case INTEL_FAM6_SKYLAKE_DESKTOP:
if (idx == PERF_CSTATE_PKG_C2_RES ||
idx == PERF_CSTATE_PKG_C3_RES ||
idx == PERF_CSTATE_PKG_C6_RES ||
idx == PERF_CSTATE_PKG_C7_RES)
return true;
break;
case 55: /* 22nm Atom "Silvermont" */
case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
case 76: /* 14nm Atom "Airmont" */
case INTEL_FAM6_ATOM_SILVERMONT1:
case INTEL_FAM6_ATOM_SILVERMONT2:
case INTEL_FAM6_ATOM_AIRMONT:
if (idx == PERF_CSTATE_CORE_C6_RES)
return true;
break;
case 69: /* 22nm Haswell ULT */
case INTEL_FAM6_HASWELL_ULT:
if (idx == PERF_CSTATE_PKG_C2_RES ||
idx == PERF_CSTATE_PKG_C3_RES ||
idx == PERF_CSTATE_PKG_C6_RES ||
......@@ -601,9 +602,9 @@ static int __init cstate_init(void)
{
/* SLM has different MSR for PKG C6 */
switch (boot_cpu_data.x86_model) {
case 55:
case 76:
case 77:
case INTEL_FAM6_ATOM_SILVERMONT1:
case INTEL_FAM6_ATOM_SILVERMONT2:
case INTEL_FAM6_ATOM_AIRMONT:
pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY;
}
......
arch/x86/events/intel/rapl.c
View file @ 178a6c16
......@@ -48,6 +48,7 @@
#include <linux/slab.h>
#include <linux/perf_event.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
#include "../perf_event.h"
/*
......@@ -719,28 +720,28 @@ static int __init rapl_pmu_init(void)
/* check supported CPU */
switch (boot_cpu_data.x86_model) {
case 42: /* Sandy Bridge */
case 58: /* Ivy Bridge */
case INTEL_FAM6_SANDYBRIDGE:
case INTEL_FAM6_IVYBRIDGE:
rapl_cntr_mask = RAPL_IDX_CLN;
rapl_pmu_events_group.attrs = rapl_events_cln_attr;
break;
case 63: /* Haswell-Server */
case INTEL_FAM6_HASWELL_X:
rapl_add_quirk(rapl_hsw_server_quirk);
rapl_cntr_mask = RAPL_IDX_SRV;
rapl_pmu_events_group.attrs = rapl_events_srv_attr;
break;
case 60: /* Haswell */
case 69: /* Haswell-Celeron */
case 61: /* Broadwell */
case INTEL_FAM6_HASWELL_CORE:
case INTEL_FAM6_HASWELL_ULT:
case INTEL_FAM6_BROADWELL_CORE:
rapl_cntr_mask = RAPL_IDX_HSW;
rapl_pmu_events_group.attrs = rapl_events_hsw_attr;
break;
case 45: /* Sandy Bridge-EP */
case 62: /* IvyTown */
case INTEL_FAM6_SANDYBRIDGE_X:
case INTEL_FAM6_IVYBRIDGE_X:
rapl_cntr_mask = RAPL_IDX_SRV;
rapl_pmu_events_group.attrs = rapl_events_srv_attr;
break;
case 87: /* Knights Landing */
case INTEL_FAM6_XEON_PHI_KNL:
rapl_add_quirk(rapl_hsw_server_quirk);
rapl_cntr_mask = RAPL_IDX_KNL;
rapl_pmu_events_group.attrs = rapl_events_knl_attr;
......
arch/x86/events/intel/uncore.c
View file @ 178a6c16
......@@ -966,33 +966,33 @@ static int __init uncore_pci_init(void)
int ret;
switch (boot_cpu_data.x86_model) {
case 45: /* Sandy Bridge-EP */
case INTEL_FAM6_SANDYBRIDGE_X:
ret = snbep_uncore_pci_init();
break;
case 62: /* Ivy Bridge-EP */
case INTEL_FAM6_IVYBRIDGE_X:
ret = ivbep_uncore_pci_init();
break;
case 63: /* Haswell-EP */
case INTEL_FAM6_HASWELL_X:
ret = hswep_uncore_pci_init();
break;
case 79: /* BDX-EP */
case 86: /* BDX-DE */
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_BROADWELL_XEON_D:
ret = bdx_uncore_pci_init();
break;
case 42: /* Sandy Bridge */
case INTEL_FAM6_SANDYBRIDGE:
ret = snb_uncore_pci_init();
break;
case 58: /* Ivy Bridge */
case INTEL_FAM6_IVYBRIDGE:
ret = ivb_uncore_pci_init();
break;
case 60: /* Haswell */
case 69: /* Haswell Celeron */
case INTEL_FAM6_HASWELL_CORE:
case INTEL_FAM6_HASWELL_ULT:
ret = hsw_uncore_pci_init();
break;
case 61: /* Broadwell */
case INTEL_FAM6_BROADWELL_CORE:
ret = bdw_uncore_pci_init();
break;
case 87: /* Knights Landing */
case INTEL_FAM6_XEON_PHI_KNL:
ret = knl_uncore_pci_init();
break;
default:
......@@ -1272,39 +1272,39 @@ static int __init uncore_cpu_init(void)
int ret;
switch (boot_cpu_data.x86_model) {
case 26: /* Nehalem */
case 30:
case 37: /* Westmere */
case 44:
case INTEL_FAM6_NEHALEM_EP:
case INTEL_FAM6_NEHALEM:
case INTEL_FAM6_WESTMERE:
case INTEL_FAM6_WESTMERE_EP:
nhm_uncore_cpu_init();
break;
case 42: /* Sandy Bridge */
case 58: /* Ivy Bridge */
case 60: /* Haswell */
case 69: /* Haswell */
case 70: /* Haswell */
case 61: /* Broadwell */
case 71: /* Broadwell */
case INTEL_FAM6_SANDYBRIDGE:
case INTEL_FAM6_IVYBRIDGE:
case INTEL_FAM6_HASWELL_CORE:
case INTEL_FAM6_HASWELL_ULT:
case INTEL_FAM6_HASWELL_GT3E:
case INTEL_FAM6_BROADWELL_CORE:
case INTEL_FAM6_BROADWELL_GT3E:
snb_uncore_cpu_init();
break;
case 45: /* Sandy Bridge-EP */
case INTEL_FAM6_SANDYBRIDGE_X:
snbep_uncore_cpu_init();
break;
case 46: /* Nehalem-EX */
case 47: /* Westmere-EX aka. Xeon E7 */
case INTEL_FAM6_NEHALEM_EX:
case INTEL_FAM6_WESTMERE_EX:
nhmex_uncore_cpu_init();
break;
case 62: /* Ivy Bridge-EP */
case INTEL_FAM6_IVYBRIDGE_X:
ivbep_uncore_cpu_init();
break;
case 63: /* Haswell-EP */
case INTEL_FAM6_HASWELL_X:
hswep_uncore_cpu_init();
break;
case 79: /* BDX-EP */
case 86: /* BDX-DE */
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_BROADWELL_XEON_D:
bdx_uncore_cpu_init();
break;
case 87: /* Knights Landing */
case INTEL_FAM6_XEON_PHI_KNL:
knl_uncore_cpu_init();
break;
default:
......
arch/x86/events/intel/uncore.h
View file @ 178a6c16
......@@ -2,6 +2,7 @@
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/perf_event.h>
#include <asm/intel-family.h>
#include "../perf_event.h"
#define UNCORE_PMU_NAME_LEN 32
......
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