drm/amdkfd: enable heavy-weight TLB flush on Vega20
It is to meet the requirement for memory allocation optimization on MI50. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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