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Commit 17f0b48f authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: camcc-sc7280: switch to parent_hws 

Change several entries of parent_data to use parent_hws instead, which
results in slightly more ovbious code.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-5-dmitry.baryshkov@linaro.org
parent 0e042233
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Showing with 134 additions and 134 deletions
drivers/clk/qcom/camcc-sc7280.c
View file @ 17f0b48f
......@@ -88,8 +88,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll0.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -111,8 +111,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_odd",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll0.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -163,8 +163,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll1.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -213,8 +213,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_aux",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll2.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -236,8 +236,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_aux2",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll2.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -288,8 +288,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll3.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -340,8 +340,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll4_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll4.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll4.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -392,8 +392,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll5_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll5.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll5.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -444,8 +444,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll6_out_even",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll6.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -467,8 +467,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll6_out_odd",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_pll6.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_pll6.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1227,8 +1227,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1245,8 +1245,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1263,8 +1263,8 @@ static struct clk_branch cam_cc_bps_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1281,8 +1281,8 @@ static struct clk_branch cam_cc_bps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_bps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_bps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1299,8 +1299,8 @@ static struct clk_branch cam_cc_camnoc_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1317,8 +1317,8 @@ static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_camnoc_dcd_xo_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_xo_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1335,8 +1335,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cci_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1353,8 +1353,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cci_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1371,8 +1371,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_core_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1389,8 +1389,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1407,8 +1407,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1425,8 +1425,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1443,8 +1443,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1461,8 +1461,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1479,8 +1479,8 @@ static struct clk_branch cam_cc_csi4phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi4phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_csi4phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_csi4phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1497,8 +1497,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1515,8 +1515,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1533,8 +1533,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1551,8 +1551,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1569,8 +1569,8 @@ static struct clk_branch cam_cc_csiphy4_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1587,8 +1587,8 @@ static struct clk_branch cam_cc_gdsc_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_gdsc_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_xo_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
......@@ -1605,8 +1605,8 @@ static struct clk_branch cam_cc_icp_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1623,8 +1623,8 @@ static struct clk_branch cam_cc_icp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_icp_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_icp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1641,8 +1641,8 @@ static struct clk_branch cam_cc_ife_0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1659,8 +1659,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1677,8 +1677,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1695,8 +1695,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1713,8 +1713,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1731,8 +1731,8 @@ static struct clk_branch cam_cc_ife_1_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1749,8 +1749,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1767,8 +1767,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1785,8 +1785,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1803,8 +1803,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1821,8 +1821,8 @@ static struct clk_branch cam_cc_ife_2_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1839,8 +1839,8 @@ static struct clk_branch cam_cc_ife_2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1857,8 +1857,8 @@ static struct clk_branch cam_cc_ife_2_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1875,8 +1875,8 @@ static struct clk_branch cam_cc_ife_2_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_2_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1893,8 +1893,8 @@ static struct clk_branch cam_cc_ife_2_dsp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_2_dsp_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1911,8 +1911,8 @@ static struct clk_branch cam_cc_ife_lite_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_lite_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1929,8 +1929,8 @@ static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1947,8 +1947,8 @@ static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_0_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1965,8 +1965,8 @@ static struct clk_branch cam_cc_ife_lite_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_lite_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1983,8 +1983,8 @@ static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2001,8 +2001,8 @@ static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_1_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2019,8 +2019,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_slow_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2037,8 +2037,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_fast_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2055,8 +2055,8 @@ static struct clk_branch cam_cc_ipe_0_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_camnoc_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2073,8 +2073,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_ipe_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_ipe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2091,8 +2091,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_jpeg_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_jpeg_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2109,8 +2109,8 @@ static struct clk_branch cam_cc_lrme_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_lrme_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_lrme_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2127,8 +2127,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2145,8 +2145,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2163,8 +2163,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2181,8 +2181,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2199,8 +2199,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk4_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2217,8 +2217,8 @@ static struct clk_branch cam_cc_mclk5_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk5_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_mclk5_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2235,8 +2235,8 @@ static struct clk_branch cam_cc_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "cam_cc_sleep_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &cam_cc_sleep_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_sleep_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......
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