Commit 18641fd9 authored by Huacai Chen's avatar Huacai Chen Committed by Thomas Bogendoerfer

MIPS: DTS: Fix number of msi vectors for Loongson64G

HT irqs vectors are 8 groups, each group has 32 irqs, Loongson64C CPUs
can use only 4 groups and Loongson64G CPUs can use all 8 groups. So the
number of msi vectors of Loongson64G is 192 (32*8 - 64 = 192).

Fixes: 24af1059 ("MIPS: Loongson64: DeviceTree for LS7A PCH")
Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent b91aff3b
...@@ -20,7 +20,11 @@ htvec: interrupt-controller@efdfb000080 { ...@@ -20,7 +20,11 @@ htvec: interrupt-controller@efdfb000080 {
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>, <25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>, <26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>; <27 IRQ_TYPE_LEVEL_HIGH>,
<28 IRQ_TYPE_LEVEL_HIGH>,
<29 IRQ_TYPE_LEVEL_HIGH>,
<30 IRQ_TYPE_LEVEL_HIGH>,
<31 IRQ_TYPE_LEVEL_HIGH>;
}; };
}; };
...@@ -31,7 +35,7 @@ msi: msi-controller@2ff00000 { ...@@ -31,7 +35,7 @@ msi: msi-controller@2ff00000 {
interrupt-controller; interrupt-controller;
msi-controller; msi-controller;
loongson,msi-base-vec = <64>; loongson,msi-base-vec = <64>;
loongson,msi-num-vecs = <128>; loongson,msi-num-vecs = <192>;
interrupt-parent = <&htvec>; interrupt-parent = <&htvec>;
}; };
}; };
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment