Commit 1afb7f80 authored by Paul Mackerras's avatar Paul Mackerras

Merge branch 'powerpc-next' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc

parents ff4be78b 8b05cefc
......@@ -24,6 +24,12 @@ Required properties:
"rj-master" - r.j., SSI is clock master
"ac97-slave" - AC97 mode, SSI is clock slave
"ac97-master" - AC97 mode, SSI is clock master
- fsl,playback-dma: phandle to a DMA node for the DMA channel to use for
playback of audio. This is typically dictated by SOC
design. See the notes below.
- fsl,capture-dma: phandle to a DMA node for the DMA channel to use for
capture (recording) of audio. This is typically dictated
by SOC design. See the notes below.
Optional properties:
- codec-handle : phandle to a 'codec' node that defines an audio
......@@ -36,3 +42,12 @@ Child 'codec' node required properties:
Child 'codec' node optional properties:
- clock-frequency : The frequency of the input clock, which typically
comes from an on-board dedicated oscillator.
Notes on fsl,playback-dma and fsl,capture-dma:
On SOCs that have an SSI, specific DMA channels are hard-wired for playback
and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
playback and DMA channel 3 for capture. The developer can choose which
DMA controller to use, but the channels themselves are hard-wired. The
purpose of these two properties is to represent this hardware design.
/*
* GE Fanuc SBC610 Device Tree Source
*
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Based on: SBS CM6 Device Tree Source
* Copyright 2007 SBS Technologies GmbH & Co. KG
* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
* Copyright 2006 Freescale Semiconductor Inc.
*/
/*
* Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
*/
/dts-v1/;
/ {
model = "GEF_SBC610";
compatible = "gef,sbc610";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8641@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
PowerPC,8641@1 {
device_type = "cpu";
reg = <1>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x0 0x40000000>; // set by uboot
};
soc@fef00000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>;
reg = <0xfef00000 0x100000>; // CCSRBAR 1M
bus-frequency = <0>;
i2c1: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
eti@6b {
compatible = "dallas,ds1682";
reg = <0x6b>;
};
};
i2c2: i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8641-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <0x0 0x1>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupt-parent = <&mpic>;
interrupts = <0x0 0x1>;
reg = <3>;
};
};
enet0: ethernet@24000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
phy-connection-type = "gmii";
};
enet1: ethernet@26000 {
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy2>;
phy-connection-type = "gmii";
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <0x1c 0x2>;
interrupt-parent = <&mpic>;
};
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
global-utilities@e0000 {
compatible = "fsl,mpc8641-guts";
reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
};
pci0: pcie@fef08000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xfef08000 0x1000>;
bus-range = <0x0 0xff>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <0x18 0x2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x40000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00400000>;
};
};
};
/*
* Device Tree for the MGCOGE plattform from keymile
*
* Copyright 2008 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "MGCOGE";
compatible = "keymile,mgcoge";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &eth0;
serial0 = &smc2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8247@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>; /* Filled in by U-Boot */
clock-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
};
};
localbus@f0010100 {
compatible = "fsl,mpc8247-localbus",
"fsl,pq2-localbus",
"simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xf0010100 0x40>;
ranges = <0 0 0xfe000000 0x00400000
5 0 0x50000000 0x20000000
>; /* Filled in by U-Boot */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x0 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <1>;
device-width = <1>;
partition@0 {
label = "u-boot";
reg = <0 0x40000>;
};
partition@40000 {
label = "env";
reg = <0x40000 0x20000>;
};
partition@60000 {
label = "kernel";
reg = <0x60000 0x220000>;
};
partition@280000 {
label = "dtb";
reg = <0x280000 0x20000>;
};
};
flash@5,0 {
compatible = "cfi-flash";
reg = <5 0x0 0x2000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
device-width = <2>;
partition@0 {
label = "ramdisk";
reg = <0 0x7a0000>;
};
partition@7a0000 {
label = "user";
reg = <0x7a0000 0x1860000>;
};
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus";
ranges = <0x00000000 0xf0000000 0x00053000>;
// Temporary until code stops depending on it.
device_type = "soc";
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8247-cpm", "fsl,cpm2",
"simple-bus";
reg = <0x119c0 0x30>;
ranges;
muram {
compatible = "fsl,cpm-muram";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x80 0x1f80 0x9800 0x800>;
};
};
brg@119f0 {
compatible = "fsl,mpc8247-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x119f0 0x10 0x115f0 0x10>;
};
/* Monitor port/SMC2 */
smc2: serial@11a90 {
device_type = "serial";
compatible = "fsl,mpc8247-smc-uart",
"fsl,cpm2-smc-uart";
reg = <0x11a90 0x20 0x88fc 0x02>;
interrupts = <5 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0x21200000>;
current-speed = <0>; /* Filled in by U-Boot */
};
eth0: ethernet@11a60 {
device_type = "network";
compatible = "fsl,mpc8247-scc-enet",
"fsl,cpm2-scc-enet";
reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
interrupts = <43 8>;
interrupt-parent = <&PIC>;
linux,network-index = <0>;
fsl,cpm-command = <0xce00000>;
fixed-link = <0 0 10 0 0>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8247-pic", "fsl,pq2-pic";
};
};
};
/*
* MGSUVD Device Tree Source
*
* Copyright 2008 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/dts-v1/;
/ {
model = "MGSUVD";
compatible = "keymile,mgsuvd";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,852@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <16>;
i-cache-line-size = <16>;
d-cache-size = <8192>;
i-cache-size = <8192>;
timebase-frequency = <0>; /* Filled in by u-boot */
bus-frequency = <0>; /* Filled in by u-boot */
clock-frequency = <0>; /* Filled in by u-boot */
interrupts = <15 2>; /* decrementer interrupt */
interrupt-parent = <&PIC>;
};
};
memory {
device_type = "memory";
reg = <00000000 0x4000000>; /* Filled in by u-boot */
};
localbus@fff00100 {
compatible = "fsl,mpc852-localbus", "fsl,pq1-localbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xfff00100 0x40>;
ranges = <0 0 0xf0000000 0x01000000>; /* Filled in by u-boot */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <1>;
device-width = <1>;
partition@0 {
label = "u-boot";
reg = <0 0x80000>;
};
partition@80000 {
label = "env";
reg = <0x80000 0x20000>;
};
partition@a0000 {
label = "kernel";
reg = <0xa0000 0x1e0000>;
};
partition@280000 {
label = "dtb";
reg = <0x280000 0x20000>;
};
partition@2a0000 {
label = "root";
reg = <0x2a0000 0x500000>;
};
partition@7a0000 {
label = "user";
reg = <0x7a0000 0x860000>;
};
};
};
soc@fff00000 {
compatible = "fsl,mpc852", "fsl,pq1-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 0xfff00000 0x00004000>;
PIC: interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 24>;
compatible = "fsl,mpc852-pic", "fsl,pq1-pic";
};
cpm@9c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc852-cpm", "fsl,cpm1", "simple-bus";
interrupts = <0>; /* cpm error interrupt */
interrupt-parent = <&CPM_PIC>;
reg = <0x9c0 10>;
ranges;
muram@2000 {
compatible = "fsl,cpm-muram";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x800 0x1800>;
};
};
brg@9f0 {
compatible = "fsl,mpc852-brg",
"fsl,cpm1-brg",
"fsl,cpm-brg";
reg = <0x9f0 0x10>;
clock-frequency = <0>; /* Filled in by u-boot */
};
CPM_PIC: interrupt-controller@930 {
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <5 2 0 2>;
interrupt-parent = <&PIC>;
reg = <0x930 0x20>;
compatible = "fsl,cpm1-pic";
};
/* MON-1 */
serial@a80 {
device_type = "serial";
compatible = "fsl,cpm1-smc-uart";
reg = <0xa80 0x10 0x3fc0 0x40>;
interrupts = <4>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x0090>;
current-speed = <0>; /* Filled in by u-boot */
};
ethernet@a40 {
device_type = "network";
compatible = "fsl,mpc866-scc-enet",
"fsl,cpm1-scc-enet";
reg = <0xa40 0x18 0x3e00 0x100>;
local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by u-boot */
interrupts = <28>;
interrupt-parent = <&CPM_PIC>;
fsl,cpm-command = <0x80>;
fixed-link = <0 0 10 0 0>;
};
};
};
};
......@@ -52,9 +52,26 @@ memory {
reg = <0x00000000 0x10000000>;
};
bcsr@f8000000 {
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0 0 0xfe000000 0x02000000
1 0 0xf8000000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x2000000>;
bank-width = <2>;
device-width = <1>;
};
bcsr@1,0 {
device_type = "board-control";
reg = <0xf8000000 0x8000>;
reg = <1 0 0x8000>;
};
};
soc8360@e0000000 {
......
......@@ -207,7 +207,7 @@ wdt@e4000 {
reg = <0xe4000 0x100>;
};
i2s@16000 {
ssi@16000 {
compatible = "fsl,mpc8610-ssi";
cell-index = <0>;
reg = <0x16000 0x100>;
......@@ -215,6 +215,8 @@ i2s@16000 {
interrupts = <62 2>;
fsl,mode = "i2s-slave";
codec-handle = <&cs4270>;
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
};
ssi@16100 {
......@@ -233,7 +235,7 @@ dma@21300 {
reg = <0x21300 0x4>; /* DMA general status register */
ranges = <0x0 0x21100 0x200>;
dma-channel@0 {
dma00: dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <0>;
......@@ -241,7 +243,7 @@ dma-channel@0 {
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@1 {
dma01: dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <1>;
......
......@@ -383,7 +383,84 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_OF_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
CONFIG_OF_I2C=y
# CONFIG_PARPORT is not set
......
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......@@ -579,12 +579,18 @@ interrupt_base:
FIND_PTE
andc. r13,r13,r11 /* Check permission */
bne 2f /* Bail if permission mismach */
#ifdef CONFIG_PTE_64BIT
lwz r13, 0(r12)
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
#endif
bne 2f /* Bail if permission/valid mismach */
/* Jump to common tlb load */
b finish_tlb_load
2:
......@@ -640,10 +646,20 @@ interrupt_base:
FIND_PTE
andc. r13,r13,r11 /* Check permission */
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_SMP
subf r10,r11,r12 /* create false data dep */
lwzx r13,r11,r10 /* Get upper pte bits */
#else
lwz r13,0(r12) /* Get upper pte bits */
#endif
#endif
bne 2f /* Bail if permission mismach */
#ifdef CONFIG_PTE_64BIT
lwz r13, 0(r12)
lwz r13,0(r12)
#endif
/* Jump to common TLB load point */
......@@ -702,7 +718,7 @@ interrupt_base:
/*
* Both the instruction and data TLB miss get to this
* point to load the TLB.
* r10 - EA of fault
* r10 - available to use
* r11 - TLB (info from Linux PTE)
* r12 - available to use
* r13 - upper bits of PTE (if PTE_64BIT) or available to use
......
......@@ -134,6 +134,7 @@ void ppc_enable_pmcs(void)
}
EXPORT_SYMBOL(ppc_enable_pmcs);
#if defined(CONFIG_6xx) || defined(CONFIG_PPC64)
/* XXX convert to rusty's on_one_cpu */
static unsigned long run_on_cpu(unsigned long cpu,
unsigned long (*func)(unsigned long),
......@@ -152,6 +153,7 @@ static unsigned long run_on_cpu(unsigned long cpu,
return ret;
}
#endif
#define SYSFS_PMCSETUP(NAME, ADDRESS) \
static unsigned long read_##NAME(unsigned long junk) \
......@@ -190,11 +192,11 @@ static ssize_t __used \
* that are implemented on the current processor
*/
#ifdef CONFIG_PPC64
#if defined(CONFIG_PPC64)
#define HAS_PPC_PMC_CLASSIC 1
#define HAS_PPC_PMC_IBM 1
#define HAS_PPC_PMC_PA6T 1
#elif CONFIG_6xx
#elif defined(CONFIG_6xx)
#define HAS_PPC_PMC_CLASSIC 1
#define HAS_PPC_PMC_IBM 1
#define HAS_PPC_PMC_G4 1
......
......@@ -202,7 +202,7 @@ adjust_total_lowmem(void)
cam_max_size = max_lowmem_size;
/* adjust lowmem size to max_lowmem_size */
ram = min(max_lowmem_size, (phys_addr_t)total_lowmem);
ram = min(max_lowmem_size, total_lowmem);
/* Calculate CAM values */
__cam0 = 1UL << 2 * (__ilog2(ram) / 2);
......@@ -225,7 +225,8 @@ adjust_total_lowmem(void)
printk(KERN_INFO "Memory CAM mapping: CAM0=%ldMb, CAM1=%ldMb,"
" CAM2=%ldMb residual: %ldMb\n",
__cam0 >> 20, __cam1 >> 20, __cam2 >> 20,
(total_lowmem - __cam0 - __cam1 - __cam2) >> 20);
(long int)((total_lowmem - __cam0 - __cam1 - __cam2)
>> 20));
__max_low_memory = __cam0 + __cam1 + __cam2;
__initial_memory_limit_addr = memstart_addr + __max_low_memory;
}
......@@ -38,6 +38,14 @@ config EP8248E
This board is also resold by Freescale as the QUICCStart
MPC8248 Evaluation System and/or the CWH-PPC-8248N-VE.
config MGCOGE
bool "Keymile MGCOGE"
select 8272
select 8260
select FSL_SOC
help
This enables support for the Keymile MGCOGE board.
endif
config PQ2ADS
......
......@@ -6,3 +6,4 @@ obj-$(CONFIG_CPM2) += pq2.o
obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o
obj-$(CONFIG_PQ2FADS) += pq2fads.o
obj-$(CONFIG_EP8248E) += ep8248e.o
obj-$(CONFIG_MGCOGE) += mgcoge.o
/*
* Keymile mgcoge support
* Copyright 2008 DENX Software Engineering GmbH
* Author: Heiko Schocher <hs@denx.de>
*
* based on code from:
* Copyright 2007 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <asm/io.h>
#include <asm/cpm2.h>
#include <asm/udbg.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/mpc8260.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/cpm2_pic.h>
#include "pq2.h"
static void __init mgcoge_pic_init(void)
{
struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
if (!np) {
printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
return;
}
cpm2_pic_init(np);
of_node_put(np);
}
struct cpm_pin {
int port, pin, flags;
};
static __initdata struct cpm_pin mgcoge_pins[] = {
/* SMC2 */
{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{1, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
/* SCC4 */
{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{3, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{3, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{3, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{4, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
{4, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
};
static void __init init_ioports(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mgcoge_pins); i++) {
const struct cpm_pin *pin = &mgcoge_pins[i];
cpm2_set_pin(pin->port - 1, pin->pin, pin->flags);
}
cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
}
static void __init mgcoge_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("mgcoge_setup_arch()", 0);
cpm2_reset();
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
init_ioports();
if (ppc_md.progress)
ppc_md.progress("mgcoge_setup_arch(), finish", 0);
}
static __initdata struct of_device_id of_bus_ids[] = {
{ .compatible = "simple-bus", },
{},
};
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_device_initcall(mgcoge, declare_of_platform_devices);
/*
* Called very early, device-tree isn't unflattened
*/
static int __init mgcoge_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, "keymile,mgcoge");
}
define_machine(mgcoge)
{
.name = "Keymile MGCOGE",
.probe = mgcoge_probe,
.setup_arch = mgcoge_setup_arch,
.init_IRQ = mgcoge_pic_init,
.get_irq = cpm2_get_irq,
.calibrate_decr = generic_calibrate_decr,
.restart = pq2_restart,
.progress = udbg_progress,
};
......@@ -156,7 +156,7 @@ static void __init init_ioports(void)
int i;
for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
struct cpm_pin *pin = &sbc8560_pins[i];
const struct cpm_pin *pin = &sbc8560_pins[i];
cpm2_set_pin(pin->port, pin->pin, pin->flags);
}
......
......@@ -31,6 +31,13 @@ config MPC8610_HPCD
help
This option enables support for the MPC8610 HPCD board.
config GEF_SBC610
bool "GE Fanuc SBC610"
select DEFAULT_UIMAGE
select HAS_RAPIDIO
help
This option enables support for GE Fanuc's SBC610.
endif
config MPC8641
......@@ -39,7 +46,7 @@ config MPC8641
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
default y if MPC8641_HPCN || SBC8641D
default y if MPC8641_HPCN || SBC8641D || GEF_SBC610
config MPC8610
bool
......
......@@ -7,3 +7,4 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
/*
* GE Fanuc SBC610 board support
*
* Author: Martyn Welch <martyn.welch@gefanuc.com>
*
* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
* Copyright 2006 Freescale Semiconductor Inc.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/of_platform.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc86xx.h>
#include <asm/prom.h>
#include <mm/mmu_decl.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
#include "mpc86xx.h"
#undef DEBUG
#ifdef DEBUG
#define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
#else
#define DBG (fmt...) do { } while (0)
#endif
static void __init gef_sbc610_setup_arch(void)
{
#ifdef CONFIG_PCI
struct device_node *np;
for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
fsl_add_bridge(np, 1);
}
#endif
printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC610 6U VPX SBC\n");
#ifdef CONFIG_SMP
mpc86xx_smp_init();
#endif
}
static void gef_sbc610_show_cpuinfo(struct seq_file *m)
{
struct device_node *root;
uint memsize = total_memory;
const char *model = "";
uint svid = mfspr(SPRN_SVR);
seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
root = of_find_node_by_path("/");
if (root)
model = of_get_property(root, "model", NULL);
seq_printf(m, "Machine\t\t: %s\n", model);
of_node_put(root);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
}
/*
* Called very early, device-tree isn't unflattened
*
* This function is called to determine whether the BSP is compatible with the
* supplied device-tree, which is assumed to be the correct one for the actual
* board. It is expected thati, in the future, a kernel may support multiple
* boards.
*/
static int __init gef_sbc610_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (of_flat_dt_is_compatible(root, "gef,sbc610"))
return 1;
return 0;
}
static long __init mpc86xx_time_init(void)
{
unsigned int temp;
/* Set the time base to zero */
mtspr(SPRN_TBWL, 0);
mtspr(SPRN_TBWU, 0);
temp = mfspr(SPRN_HID0);
temp |= HID0_TBEN;
mtspr(SPRN_HID0, temp);
asm volatile("isync");
return 0;
}
static __initdata struct of_device_id of_bus_ids[] = {
{ .compatible = "simple-bus", },
{},
};
static int __init declare_of_platform_devices(void)
{
printk(KERN_DEBUG "Probe platform devices\n");
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_device_initcall(gef_sbc610, declare_of_platform_devices);
define_machine(gef_sbc610) {
.name = "GE Fanuc SBC610",
.probe = gef_sbc610_probe,
.setup_arch = gef_sbc610_setup_arch,
.init_IRQ = mpc86xx_init_irq,
.show_cpuinfo = gef_sbc610_show_cpuinfo,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
};
......@@ -49,6 +49,12 @@ config PPC_ADDER875
This enables support for the Analogue & Micro Adder 875
board.
config PPC_MGSUVD
bool "MGSUVD"
select CPM1
help
This enables support for the Keymile MGSUVD board.
endchoice
menu "Freescale Ethernet driver platform-specific options"
......
......@@ -6,3 +6,4 @@ obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o
obj-$(CONFIG_PPC_EP88XC) += ep88xc.o
obj-$(CONFIG_PPC_ADDER875) += adder875.o
obj-$(CONFIG_PPC_MGSUVD) += mgsuvd.o
/*
*
* Platform setup for the Keymile mgsuvd board
*
* Heiko Schocher <hs@denx.de>
*
* Copyright 2008 DENX Software Engineering GmbH
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/ioport.h>
#include <linux/of_platform.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/processor.h>
#include <asm/cpm1.h>
#include <asm/prom.h>
#include <asm/fs_pd.h>
#include "mpc8xx.h"
struct cpm_pin {
int port, pin, flags;
};
static __initdata struct cpm_pin mgsuvd_pins[] = {
/* SMC1 */
{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
/* SCC3 */
{CPM_PORTA, 10, CPM_PIN_INPUT},
{CPM_PORTA, 11, CPM_PIN_INPUT},
{CPM_PORTA, 3, CPM_PIN_INPUT},
{CPM_PORTA, 2, CPM_PIN_INPUT},
{CPM_PORTC, 13, CPM_PIN_INPUT},
};
static void __init init_ioports(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mgsuvd_pins); i++) {
struct cpm_pin *pin = &mgsuvd_pins[i];
cpm1_set_pin(pin->port, pin->pin, pin->flags);
}
setbits16(&mpc8xx_immr->im_ioport.iop_pcso, 0x300);
cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RX);
cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_TX);
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
}
static void __init mgsuvd_setup_arch(void)
{
cpm_reset();
init_ioports();
}
static __initdata struct of_device_id of_bus_ids[] = {
{ .compatible = "simple-bus" },
{},
};
static int __init declare_of_platform_devices(void)
{
of_platform_bus_probe(NULL, of_bus_ids, NULL);
return 0;
}
machine_device_initcall(mgsuvd, declare_of_platform_devices);
static int __init mgsuvd_probe(void)
{
unsigned long root = of_get_flat_dt_root();
return of_flat_dt_is_compatible(root, "keymile,mgsuvd");
}
define_machine(mgsuvd) {
.name = "MGSUVD",
.probe = mgsuvd_probe,
.setup_arch = mgsuvd_setup_arch,
.init_IRQ = mpc8xx_pics_init,
.get_irq = mpc8xx_get_irq,
.restart = mpc8xx_restart,
.calibrate_decr = mpc8xx_calibrate_decr,
.set_rtc_time = mpc8xx_set_rtc_time,
.get_rtc_time = mpc8xx_get_rtc_time,
};
......@@ -546,15 +546,11 @@ static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
return !!(in_be16(&iop->dat) & pin_mask);
}
static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
if (value)
cpm1_gc->cpdata |= pin_mask;
......@@ -562,6 +558,18 @@ static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
cpm1_gc->cpdata &= ~pin_mask;
out_be16(&iop->dat, cpm1_gc->cpdata);
}
static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
__cpm1_gpio16_set(mm_gc, pin_mask, value);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
}
......@@ -569,14 +577,17 @@ static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
u16 pin_mask;
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
setbits16(&iop->dir, pin_mask);
__cpm1_gpio16_set(mm_gc, pin_mask, val);
cpm1_gpio16_set(gc, gpio, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
return 0;
}
......@@ -584,13 +595,17 @@ static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio16_chip *cpm1_gc = to_cpm1_gpio16_chip(mm_gc);
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
u16 pin_mask;
unsigned long flags;
u16 pin_mask = 1 << (15 - gpio);
pin_mask = 1 << (15 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
clrbits16(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
return 0;
}
......@@ -655,15 +670,11 @@ static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
return !!(in_be32(&iop->dat) & pin_mask);
}
static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
if (value)
cpm1_gc->cpdata |= pin_mask;
......@@ -671,6 +682,18 @@ static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
cpm1_gc->cpdata &= ~pin_mask;
out_be32(&iop->dat, cpm1_gc->cpdata);
}
static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
__cpm1_gpio32_set(mm_gc, pin_mask, value);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
}
......@@ -678,14 +701,17 @@ static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
u32 pin_mask;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
setbits32(&iop->dir, pin_mask);
__cpm1_gpio32_set(mm_gc, pin_mask, val);
cpm1_gpio32_set(gc, gpio, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
return 0;
}
......@@ -693,13 +719,17 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct cpm1_gpio32_chip *cpm1_gc = to_cpm1_gpio32_chip(mm_gc);
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
u32 pin_mask;
unsigned long flags;
u32 pin_mask = 1 << (31 - gpio);
pin_mask = 1 << (31 - gpio);
spin_lock_irqsave(&cpm1_gc->lock, flags);
clrbits32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
return 0;
}
......
......@@ -1136,42 +1136,6 @@ config SERIAL_CPM_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
config SERIAL_CPM_SCC1
bool "Support for SCC1 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SCC1 as a serial port
config SERIAL_CPM_SCC2
bool "Support for SCC2 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SCC2 as a serial port
config SERIAL_CPM_SCC3
bool "Support for SCC3 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SCC3 as a serial port
config SERIAL_CPM_SCC4
bool "Support for SCC4 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SCC4 as a serial port
config SERIAL_CPM_SMC1
bool "Support for SMC1 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SMC1 as a serial port
config SERIAL_CPM_SMC2
bool "Support for SMC2 serial port"
depends on SERIAL_CPM=y
help
Select this option to use SMC2 as a serial port
config SERIAL_SGI_L1_CONSOLE
bool "SGI Altix L1 serial console support"
depends on IA64_GENERIC || IA64_SGI_SN2
......
......@@ -1333,6 +1333,9 @@ static int __devinit cpm_uart_probe(struct of_device *ofdev,
if (ret)
return ret;
/* initialize the device pointer for the port */
pinfo->port.dev = &ofdev->dev;
return uart_add_one_port(&cpm_reg, &pinfo->port);
}
......
......@@ -100,7 +100,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
dma_addr = (u32)cpm_dpram_phys(mem_addr);
} else
mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr,
GFP_KERNEL);
if (mem_addr == NULL) {
......@@ -127,7 +127,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
pinfo->rx_fifosize) +
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
pinfo->tx_fifosize), pinfo->mem_addr,
......
......@@ -136,7 +136,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
dma_addr = virt_to_bus(mem_addr);
}
else
mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr,
GFP_KERNEL);
if (mem_addr == NULL) {
......@@ -163,7 +163,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
pinfo->rx_fifosize) +
L1_CACHE_ALIGN(pinfo->tx_nrfifos *
pinfo->tx_fifosize), (void __force *)pinfo->mem_addr,
......
......@@ -1009,7 +1009,7 @@ static int qe_uart_request_port(struct uart_port *port)
rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
bd_virt = dma_alloc_coherent(NULL, rx_size + tx_size, &bd_dma_addr,
bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
GFP_KERNEL);
if (!bd_virt) {
dev_err(port->dev, "could not allocate buffer descriptors\n");
......@@ -1051,7 +1051,7 @@ static void qe_uart_release_port(struct uart_port *port)
container_of(port, struct uart_qe_port, port);
struct ucc_slow_private *uccs = qe_port->us_private;
dma_free_coherent(NULL, qe_port->bd_size, qe_port->bd_virt,
dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
qe_port->bd_dma_addr);
ucc_slow_free(uccs);
......
......@@ -25,7 +25,7 @@
#ifndef __MATH_EMU_OP_2_H__
#define __MATH_EMU_OP_2_H__
#define _FP_FRAC_DECL_2(X) _FP_W_TYPE X##_f0, X##_f1
#define _FP_FRAC_DECL_2(X) _FP_W_TYPE X##_f0 = 0, X##_f1 = 0
#define _FP_FRAC_COPY_2(D,S) (D##_f0 = S##_f0, D##_f1 = S##_f1)
#define _FP_FRAC_SET_2(X,I) __FP_FRAC_SET_2(X, I)
#define _FP_FRAC_HIGH_2(X) (X##_f1)
......
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