Commit 2021d5b7 authored by Neil Armstrong's avatar Neil Armstrong

drm/meson: Convert existing documentation to actual kerneldoc

Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 8cceda53
...@@ -24,7 +24,9 @@ ...@@ -24,7 +24,9 @@
#include "meson_canvas.h" #include "meson_canvas.h"
#include "meson_registers.h" #include "meson_registers.h"
/* /**
* DOC: Canvas
*
* CANVAS is a memory zone where physical memory frames information * CANVAS is a memory zone where physical memory frames information
* are stored for the VIU to scanout. * are stored for the VIU to scanout.
*/ */
......
...@@ -52,13 +52,14 @@ ...@@ -52,13 +52,14 @@
#define DRIVER_NAME "meson" #define DRIVER_NAME "meson"
#define DRIVER_DESC "Amlogic Meson DRM driver" #define DRIVER_DESC "Amlogic Meson DRM driver"
/* /**
* Video Processing Unit * DOC: Video Processing Unit
* *
* VPU Handles the Global Video Processing, it includes management of the * VPU Handles the Global Video Processing, it includes management of the
* clocks gates, blocks reset lines and power domains. * clocks gates, blocks reset lines and power domains.
* *
* What is missing : * What is missing :
*
* - Full reset of entire video processing HW blocks * - Full reset of entire video processing HW blocks
* - Scaling and setup of the VPU clock * - Scaling and setup of the VPU clock
* - Bus clock gates * - Bus clock gates
......
...@@ -42,11 +42,17 @@ ...@@ -42,11 +42,17 @@
#define DRIVER_NAME "meson-dw-hdmi" #define DRIVER_NAME "meson-dw-hdmi"
#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver" #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
/* /**
* DOC: HDMI Output
*
* HDMI Output is composed of : * HDMI Output is composed of :
*
* - A Synopsys DesignWare HDMI Controller IP * - A Synopsys DesignWare HDMI Controller IP
* - A TOP control block controlling the Clocks and PHY * - A TOP control block controlling the Clocks and PHY
* - A custom HDMI PHY in order convert video to TMDS signal * - A custom HDMI PHY in order convert video to TMDS signal
*
* .. code::
*
* ___________________________________ * ___________________________________
* | HDMI TOP |<= HPD * | HDMI TOP |<= HPD
* |___________________________________| * |___________________________________|
...@@ -55,6 +61,7 @@ ...@@ -55,6 +61,7 @@
* | Controller |________________| * | Controller |________________|
* |___________________________________|<=> DDC * |___________________________________|<=> DDC
* *
*
* The HDMI TOP block only supports HPD sensing. * The HDMI TOP block only supports HPD sensing.
* The Synopsys HDMI Controller interrupt is routed * The Synopsys HDMI Controller interrupt is routed
* through the TOP Block interrupt. * through the TOP Block interrupt.
...@@ -78,6 +85,7 @@ ...@@ -78,6 +85,7 @@
* audio source interfaces. * audio source interfaces.
* *
* We handle the following features : * We handle the following features :
*
* - HPD Rise & Fall interrupt * - HPD Rise & Fall interrupt
* - HDMI Controller Interrupt * - HDMI Controller Interrupt
* - HDMI PHY Init for 480i to 1080p60 * - HDMI PHY Init for 480i to 1080p60
...@@ -85,6 +93,7 @@ ...@@ -85,6 +93,7 @@
* - VENC Mode setup for 480i to 1080p60 * - VENC Mode setup for 480i to 1080p60
* *
* What is missing : * What is missing :
*
* - PHY, Clock and Mode setup for 2k && 4k modes * - PHY, Clock and Mode setup for 2k && 4k modes
* - SDDC Scrambling mode for HDMI 2.0a * - SDDC Scrambling mode for HDMI 2.0a
* - HDCP Setup * - HDCP Setup
......
...@@ -23,15 +23,23 @@ ...@@ -23,15 +23,23 @@
#include "meson_drv.h" #include "meson_drv.h"
#include "meson_vclk.h" #include "meson_vclk.h"
/* /**
* DOC: Video Clocks
*
* VCLK is the "Pixel Clock" frequency generator from a dedicated PLL. * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
* We handle the following encodings : * We handle the following encodings :
*
* - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
* - HDMI Pixel Clocks generation * - HDMI Pixel Clocks generation
*
* What is missing : * What is missing :
*
* - Genenate Pixel clocks for 2K/4K 10bit formats * - Genenate Pixel clocks for 2K/4K 10bit formats
* *
* Clock generator scheme : * Clock generator scheme :
*
* .. code::
*
* __________ _________ _____ * __________ _________ _____
* | | | | | |--ENCI * | | | | | |--ENCI
* | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
......
...@@ -26,23 +26,30 @@ ...@@ -26,23 +26,30 @@
#include "meson_vclk.h" #include "meson_vclk.h"
#include "meson_registers.h" #include "meson_registers.h"
/* /**
* DOC: Video Encoder
*
* VENC Handle the pixels encoding to the output formats. * VENC Handle the pixels encoding to the output formats.
* We handle the following encodings : * We handle the following encodings :
*
* - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
* - TMDS/HDMI Encoding via ENCI_DIV and ENCP * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
* - Setup of more clock rates for HDMI modes * - Setup of more clock rates for HDMI modes
* *
* What is missing : * What is missing :
*
* - LCD Panel encoding via ENCL * - LCD Panel encoding via ENCL
* - TV Panel encoding via ENCT * - TV Panel encoding via ENCT
* *
* VENC paths : * VENC paths :
*
* .. code::
*
* _____ _____ ____________________ * _____ _____ ____________________
* vd1---| |-| | | VENC /---------|----VDAC * vd1---| |-| | | VENC /---------|----VDAC
* vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|\ * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
* osd1--| |-| | | \ | X--HDMI-TX * osd1--| |-| | | \ | X--HDMI-TX
* osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|/ * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
* | | | * | | |
* | \--ENCL-----------|----LVDS * | \--ENCL-----------|----LVDS
* |____________________| * |____________________|
......
...@@ -28,9 +28,12 @@ ...@@ -28,9 +28,12 @@
#include "meson_canvas.h" #include "meson_canvas.h"
#include "meson_registers.h" #include "meson_registers.h"
/* /**
* DOC: Video Input Unit
*
* VIU Handles the Pixel scanout and the basic Colorspace conversions * VIU Handles the Pixel scanout and the basic Colorspace conversions
* We handle the following features : * We handle the following features :
*
* - OSD1 RGB565/RGB888/xRGB8888 scanout * - OSD1 RGB565/RGB888/xRGB8888 scanout
* - RGB conversion to x/cb/cr * - RGB conversion to x/cb/cr
* - Progressive or Interlace buffer scanout * - Progressive or Interlace buffer scanout
...@@ -38,6 +41,7 @@ ...@@ -38,6 +41,7 @@
* - HDR OSD matrix for GXL/GXM * - HDR OSD matrix for GXL/GXM
* *
* What is missing : * What is missing :
*
* - BGR888/xBGR8888/BGRx8888/BGRx8888 modes * - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
* - YUV4:2:2 Y0CbY1Cr scanout * - YUV4:2:2 Y0CbY1Cr scanout
* - Conversion to YUV 4:4:4 from 4:2:2 input * - Conversion to YUV 4:4:4 from 4:2:2 input
......
...@@ -25,16 +25,20 @@ ...@@ -25,16 +25,20 @@
#include "meson_vpp.h" #include "meson_vpp.h"
#include "meson_registers.h" #include "meson_registers.h"
/* /**
* DOC: Video Post Processing
*
* VPP Handles all the Post Processing after the Scanout from the VIU * VPP Handles all the Post Processing after the Scanout from the VIU
* We handle the following post processings : * We handle the following post processings :
* - Postblend : Blends the OSD1 only *
* - Postblend, Blends the OSD1 only
* We exclude OSD2, VS1, VS1 and Preblend output * We exclude OSD2, VS1, VS1 and Preblend output
* - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
* use it only for interlace scanout * use it only for interlace scanout
* - Intermediate FIFO with default Amlogic values * - Intermediate FIFO with default Amlogic values
* *
* What is missing : * What is missing :
*
* - Preblend for video overlay pre-scaling * - Preblend for video overlay pre-scaling
* - OSD2 support for cursor framebuffer * - OSD2 support for cursor framebuffer
* - Video pre-scaling before postblend * - Video pre-scaling before postblend
......
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