PPC32: cope with PPC750FX rev 2.0 errata where we can't enable DPM

(dynamic power management)

arch/ppc/kernel/cputable.c

@@ -154,6 +154,24 @@ struct cpu_spec	cpu_specs[] = {
 	32, 32,
 	__setup_cpu_750
     },
+    {	/* 750FX rev 2.0 must disable HID0[DPM] */
+    	0xffffffff, 0x70000200, "750FX",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP |
+	CPU_FTR_NO_DPM,
+	COMMON_PPC,
+	32, 32,
+	__setup_cpu_750
+    },
+    {	/* 750FX (All revs except 2.0) */
+    	0xffff0000, 0x70000000, "750FX",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
+	CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP,
+	COMMON_PPC,
+	32, 32,
+	__setup_cpu_750
+    },
+ 
     {	/* 740/750 (L2CR bit need fixup for 740) */
     	0xffff0000, 0x00080000, "740/750",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB |
@@ -327,21 +345,49 @@ struct cpu_spec	cpu_specs[] = {
     	0xffff0000, 0x41610000, "NP405L",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
     	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
-	16, 8,
+	32, 32,
 	0, /*__setup_cpu_405 */
     },
     {	/* NP4GS3 */
     	0xffff0000, 0x40B10000, "NP4GS3",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
     	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
-	16, 8,
+	32, 32,
 	0, /*__setup_cpu_405 */
     },
     {   /* NP405H */
         0xffff0000, 0x41410000, "NP405H",
         CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
         PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
-        16, 8,
+        32, 32,
+        0, /*__setup_cpu_405 */
+     },
+     {	/* 405GPr */
+    	0xffff0000, 0x50910000, "405GPr",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+	32, 32,
+	0, /*__setup_cpu_405 */
+    },
+    {   /* STBx25xx */
+        0xffff0000, 0x51510000, "STBx25xx",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+        32, 32,
+        0, /*__setup_cpu_405 */
+     },
+     {	/* 405LP */
+    	0xffff0000, 0x41F10000, "405LP",
+    	CPU_FTR_SPLIT_ID_CACHE |  CPU_FTR_USE_TB,
+    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+	32, 32,
+	0, /*__setup_cpu_405 */
+     },
+     {	/* Xilinx Virtex-II Pro  */
+	0xffff0000, 0x20010000, "Virtex-II Pro",
+	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+	32, 32,
 	0, /*__setup_cpu_405 */
      },
 

arch/ppc/kernel/head.S

@@ -1317,7 +1317,9 @@ setup_604_hid0:
 setup_750_7400_hid0:
 	mfspr	r11,HID0
 	ori	r11,r11,HID0_SGE | HID0_ABE | HID0_BHTE | HID0_BTIC
+BEGIN_FTR_SECTION
 	oris	r11,r11,HID0_DPM@h	/* enable dynamic power mgmt */
+END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
 	li	r3,HID0_SPD
 	andc	r11,r11,r3		/* clear SPD: enable speculative */
  	li	r3,0
@@ -1356,7 +1358,9 @@ setup_7450_23_hid0:
 	/* All of the bits we have to set.....
 	*/
 	ori	r11,r11,HID0_SGE | HID0_FOLD | HID0_BHTE | HID0_BTIC | HID0_LRSTK
+BEGIN_FTR_SECTION
 	oris	r11,r11,HID0_DPM@h	/* enable dynamic power mgmt */
+END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
 
 	/* All of the bits we have to clear....
 	*/

arch/ppc/kernel/ppc6xx_idle.c

@@ -52,7 +52,10 @@ ppc6xx_idle(void)
 	if (!need_resched()) {
 		__asm__ __volatile__("mfspr %0,1008":"=r"(hid0):);
 		hid0 &= ~(HID0_NAP | HID0_SLEEP | HID0_DOZE);
-		hid0 |= (powersave_nap ? HID0_NAP : HID0_DOZE) | HID0_DPM;
+		hid0 |= (powersave_nap ? HID0_NAP : HID0_DOZE);
+		if (!(cur_cpu_spec[smp_processor_id()]->cpu_features
+		      & CPU_FTR_NO_DPM))
+			hid0 |= HID0_DPM;
 		__asm__ __volatile__("mtspr 1008,%0"::"r"(hid0));
 		/* Flush pending data streams, consider this instruction
 		 * exist on all altivec capable CPUs

include/asm-ppc/cputable.h

@@ -66,6 +66,7 @@ extern struct cpu_spec		*cur_cpu_spec[];
 #define CPU_FTR_HPTE_TABLE		0x00000200
 #define CPU_FTR_CAN_NAP			0x00000400
 #define CPU_FTR_L3CR			0x00000800
+#define CPU_FTR_NO_DPM			0x00008000
 
 #ifdef __ASSEMBLY__