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Commit 24ce1938 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: rtd520: cleanup rtd_dio_insn_config() 

Add a local variable to make this function a bit cleaner and
remove the unnecessary comments.

The comedi core expects this function to return the number of
data parameters used. Change the return from '1' to 'insn->n'
to make this more apparent.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 45b6937a
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drivers/staging/comedi/drivers/rtd520.h
View file @ 24ce1938
...@@ -127,152 +127,6 @@ ...@@ -127,152 +127,6 @@
#define FS_DIN_HEMPTY (1 << 13) /* DIN FIFO half empty */ #define FS_DIN_HEMPTY (1 << 13) /* DIN FIFO half empty */
#define FS_DIN_NOT_FULL (1 << 14) /* DIN FIFO not full */ #define FS_DIN_NOT_FULL (1 << 14) /* DIN FIFO not full */
/* Timer Status Word Bits (GetTimerStatus) */
#define TS_PCLK_GATE (1 << 0) /* Pacer Clock Gate enabled */
#define TS_BCLK_GATE (1 << 1) /* Burst Clock Gate running */
#define TS_DCNT_GATE (1 << 2) /* Pacer Clock Delayed Start Trig. */
#define TS_ACNT_GATE (1 << 3) /* Pacer Clock About Trig. */
#define TS_PCLK_RUN (1 << 4) /* Pacer Clock Shutdown Flag */
/* External Trigger polarity select */
/* External Interrupt polarity select */
#define POL_POSITIVE 0x0 /* positive edge */
#define POL_NEGATIVE 0x1 /* negative edge */
/* User Output Signal select (SetUout0Source, SetUout1Source) */
#define UOUT_ADC 0x0 /* A/D Conversion Signal */
#define UOUT_DAC1 0x1 /* D/A1 Update */
#define UOUT_DAC2 0x2 /* D/A2 Update */
#define UOUT_SOFTWARE 0x3 /* Software Programmable */
/* Pacer clock select (SetPacerSource) */
#define PCLK_INTERNAL 1 /* Internal Pacer Clock */
#define PCLK_EXTERNAL 0 /* External Pacer Clock */
/* A/D Sample Counter Sources (SetAdcntSource, SetupSampleCounter) */
#define ADC_SCNT_CGT_RESET 0x0 /* needs restart with StartPacer */
#define ADC_SCNT_FIFO_WRITE 0x1
/* A/D Conversion Signal Select (for SetConversionSelect) */
#define ADC_START_SOFTWARE 0x0 /* Software A/D Start */
#define ADC_START_PCLK 0x1 /* Pacer Clock (Ext. Int. see Func.509) */
#define ADC_START_BCLK 0x2 /* Burst Clock */
#define ADC_START_DIGITAL_IT 0x3 /* Digital Interrupt */
#define ADC_START_DAC1_MARKER1 0x4 /* D/A 1 Data Marker 1 */
#define ADC_START_DAC2_MARKER1 0x5 /* D/A 2 Data Marker 1 */
#define ADC_START_SBUS0 0x6 /* SyncBus 0 */
#define ADC_START_SBUS1 0x7 /* SyncBus 1 */
#define ADC_START_SBUS2 0x8 /* SyncBus 2 */
/* Burst Clock start trigger select (SetBurstStart) */
#define BCLK_START_SOFTWARE 0x0 /* Software A/D Start (StartBurst) */
#define BCLK_START_PCLK 0x1 /* Pacer Clock */
#define BCLK_START_ETRIG 0x2 /* External Trigger */
#define BCLK_START_DIGITAL_IT 0x3 /* Digital Interrupt */
#define BCLK_START_SBUS0 0x4 /* SyncBus 0 */
#define BCLK_START_SBUS1 0x5 /* SyncBus 1 */
#define BCLK_START_SBUS2 0x6 /* SyncBus 2 */
/* Pacer Clock start trigger select (SetPacerStart) */
#define PCLK_START_SOFTWARE 0x0 /* Software Pacer Start (StartPacer) */
#define PCLK_START_ETRIG 0x1 /* External trigger */
#define PCLK_START_DIGITAL_IT 0x2 /* Digital interrupt */
#define PCLK_START_UTC2 0x3 /* User TC 2 out */
#define PCLK_START_SBUS0 0x4 /* SyncBus 0 */
#define PCLK_START_SBUS1 0x5 /* SyncBus 1 */
#define PCLK_START_SBUS2 0x6 /* SyncBus 2 */
#define PCLK_START_D_SOFTWARE 0x8 /* Delayed Software Pacer Start */
#define PCLK_START_D_ETRIG 0x9 /* Delayed external trigger */
#define PCLK_START_D_DIGITAL_IT 0xA /* Delayed digital interrupt */
#define PCLK_START_D_UTC2 0xB /* Delayed User TC 2 out */
#define PCLK_START_D_SBUS0 0xC /* Delayed SyncBus 0 */
#define PCLK_START_D_SBUS1 0xD /* Delayed SyncBus 1 */
#define PCLK_START_D_SBUS2 0xE /* Delayed SyncBus 2 */
#define PCLK_START_ETRIG_GATED 0xF /* External Trigger Gated controlled mode */
/* Pacer Clock Stop Trigger select (SetPacerStop) */
#define PCLK_STOP_SOFTWARE 0x0 /* Software Pacer Stop (StopPacer) */
#define PCLK_STOP_ETRIG 0x1 /* External Trigger */
#define PCLK_STOP_DIGITAL_IT 0x2 /* Digital Interrupt */
#define PCLK_STOP_ACNT 0x3 /* About Counter */
#define PCLK_STOP_UTC2 0x4 /* User TC2 out */
#define PCLK_STOP_SBUS0 0x5 /* SyncBus 0 */
#define PCLK_STOP_SBUS1 0x6 /* SyncBus 1 */
#define PCLK_STOP_SBUS2 0x7 /* SyncBus 2 */
#define PCLK_STOP_A_SOFTWARE 0x8 /* About Software Pacer Stop */
#define PCLK_STOP_A_ETRIG 0x9 /* About External Trigger */
#define PCLK_STOP_A_DIGITAL_IT 0xA /* About Digital Interrupt */
#define PCLK_STOP_A_UTC2 0xC /* About User TC2 out */
#define PCLK_STOP_A_SBUS0 0xD /* About SyncBus 0 */
#define PCLK_STOP_A_SBUS1 0xE /* About SyncBus 1 */
#define PCLK_STOP_A_SBUS2 0xF /* About SyncBus 2 */
/* About Counter Stop Enable */
#define ACNT_STOP 0x0 /* stop enable */
#define ACNT_NO_STOP 0x1 /* stop disabled */
/* DAC update source (SetDAC1Start & SetDAC2Start) */
#define DAC_START_SOFTWARE 0x0 /* Software Update */
#define DAC_START_CGT 0x1 /* CGT controlled Update */
#define DAC_START_DAC_CLK 0x2 /* D/A Clock */
#define DAC_START_EPCLK 0x3 /* External Pacer Clock */
#define DAC_START_SBUS0 0x4 /* SyncBus 0 */
#define DAC_START_SBUS1 0x5 /* SyncBus 1 */
#define DAC_START_SBUS2 0x6 /* SyncBus 2 */
/* DAC Cycle Mode (SetDAC1Cycle, SetDAC2Cycle, SetupDAC) */
#define DAC_CYCLE_SINGLE 0x0 /* not cycle */
#define DAC_CYCLE_MULTI 0x1 /* cycle */
/* 8254 Operation Modes (Set8254Mode, SetupTimerCounter) */
#define M8254_EVENT_COUNTER 0 /* Event Counter */
#define M8254_HW_ONE_SHOT 1 /* Hardware-Retriggerable One-Shot */
#define M8254_RATE_GENERATOR 2 /* Rate Generator */
#define M8254_SQUARE_WAVE 3 /* Square Wave Mode */
#define M8254_SW_STROBE 4 /* Software Triggered Strobe */
#define M8254_HW_STROBE 5 /* Hardware Triggered Strobe (Retriggerable) */
/* User Timer/Counter 0 Clock Select (SetUtc0Clock) */
#define CUTC0_8MHZ 0x0 /* 8MHz */
#define CUTC0_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */
#define CUTC0_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */
#define CUTC0_EXT_PCLK 0x3 /* Ext. Pacer Clock */
/* User Timer/Counter 1 Clock Select (SetUtc1Clock) */
#define CUTC1_8MHZ 0x0 /* 8MHz */
#define CUTC1_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */
#define CUTC1_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */
#define CUTC1_EXT_PCLK 0x3 /* Ext. Pacer Clock */
#define CUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */
#define CUTC1_DIN_SIGNAL 0x5 /* High-Speed Digital Input Sampling signal */
/* User Timer/Counter 2 Clock Select (SetUtc2Clock) */
#define CUTC2_8MHZ 0x0 /* 8MHz */
#define CUTC2_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */
#define CUTC2_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */
#define CUTC2_EXT_PCLK 0x3 /* Ext. Pacer Clock */
#define CUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */
/* User Timer/Counter 0 Gate Select (SetUtc0Gate) */
#define GUTC0_NOT_GATED 0x0 /* Not gated */
#define GUTC0_GATED 0x1 /* Gated */
#define GUTC0_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */
#define GUTC0_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */
/* User Timer/Counter 1 Gate Select (SetUtc1Gate) */
#define GUTC1_NOT_GATED 0x0 /* Not gated */
#define GUTC1_GATED 0x1 /* Gated */
#define GUTC1_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */
#define GUTC1_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */
#define GUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */
/* User Timer/Counter 2 Gate Select (SetUtc2Gate) */
#define GUTC2_NOT_GATED 0x0 /* Not gated */
#define GUTC2_GATED 0x1 /* Gated */
#define GUTC2_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */
#define GUTC2_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */
#define GUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */
/* Interrupt Source Masks (SetITMask, ClearITMask, GetITStatus) */ /* Interrupt Source Masks (SetITMask, ClearITMask, GetITStatus) */
#define IRQM_ADC_FIFO_WRITE 0x0001 /* ADC FIFO Write */ #define IRQM_ADC_FIFO_WRITE 0x0001 /* ADC FIFO Write */
#define IRQM_CGT_RESET 0x0002 /* Reset CGT */ #define IRQM_CGT_RESET 0x0002 /* Reset CGT */
...@@ -289,74 +143,3 @@ ...@@ -289,74 +143,3 @@
#define IRQM_EXTERNAL_IT 0x2000 /* External Interrupt */ #define IRQM_EXTERNAL_IT 0x2000 /* External Interrupt */
#define IRQM_ETRIG_RISING 0x4000 /* External Trigger rising-edge */ #define IRQM_ETRIG_RISING 0x4000 /* External Trigger rising-edge */
#define IRQM_ETRIG_FALLING 0x8000 /* External Trigger falling-edge */ #define IRQM_ETRIG_FALLING 0x8000 /* External Trigger falling-edge */
/* DMA Request Sources (LAS0) */
#define DMAS_DISABLED 0x0 /* DMA Disabled */
#define DMAS_ADC_SCNT 0x1 /* ADC Sample Counter */
#define DMAS_DAC1_UCNT 0x2 /* D/A1 Update Counter */
#define DMAS_DAC2_UCNT 0x3 /* D/A2 Update Counter */
#define DMAS_UTC1 0x4 /* User TC1 out */
#define DMAS_ADFIFO_HALF_FULL 0x8 /* A/D FIFO half full */
#define DMAS_DAC1_FIFO_HALF_EMPTY 0x9 /* D/A1 FIFO half empty */
#define DMAS_DAC2_FIFO_HALF_EMPTY 0xA /* D/A2 FIFO half empty */
/* DMA Local Addresses (0x40000000+LAS1 offset) */
#define DMALADDR_ADC 0x40000000 /* A/D FIFO */
#define DMALADDR_HDIN 0x40000004 /* High Speed Digital Input FIFO */
#define DMALADDR_DAC1 0x40000008 /* D/A1 FIFO */
#define DMALADDR_DAC2 0x4000000C /* D/A2 FIFO */
/* Port 0 compare modes (SetDIO0CompareMode) */
#define DIO_MODE_EVENT 0 /* Event Mode */
#define DIO_MODE_MATCH 1 /* Match Mode */
/* Digital Table Enable (Port 1 disable) */
#define DTBL_DISABLE 0 /* Enable Digital Table */
#define DTBL_ENABLE 1 /* Disable Digital Table */
/* Sampling Signal for High Speed Digital Input (SetHdinStart) */
#define HDIN_SOFTWARE 0x0 /* Software Trigger */
#define HDIN_ADC 0x1 /* A/D Conversion Signal */
#define HDIN_UTC0 0x2 /* User TC out 0 */
#define HDIN_UTC1 0x3 /* User TC out 1 */
#define HDIN_UTC2 0x4 /* User TC out 2 */
#define HDIN_EPCLK 0x5 /* External Pacer Clock */
#define HDIN_ETRG 0x6 /* External Trigger */
/* Channel Gain Table / Channel Gain Latch */
#define CSC_LATCH 0 /* Channel Gain Latch mode */
#define CSC_CGT 1 /* Channel Gain Table mode */
/* Channel Gain Table Pause Enable */
#define CGT_PAUSE_DISABLE 0 /* Channel Gain Table Pause Disable */
#define CGT_PAUSE_ENABLE 1 /* Channel Gain Table Pause Enable */
/* DAC output type/range (p63) */
#define AOUT_UNIP5 0 /* 0..+5 Volt */
#define AOUT_UNIP10 1 /* 0..+10 Volt */
#define AOUT_BIP5 2 /* -5..+5 Volt */
#define AOUT_BIP10 3 /* -10..+10 Volt */
/* Ghannel Gain Table field definitions (p61) */
/* Gain */
#define GAIN1 0
#define GAIN2 1
#define GAIN4 2
#define GAIN8 3
#define GAIN16 4
#define GAIN32 5
#define GAIN64 6
#define GAIN128 7
/* Input range/polarity */
#define AIN_BIP5 0 /* -5..+5 Volt */
#define AIN_BIP10 1 /* -10..+10 Volt */
#define AIN_UNIP10 2 /* 0..+10 Volt */
/* non referenced single ended select bit */
#define NRSE_AGND 0 /* AGND referenced SE input */
#define NRSE_AINS 1 /* AIN SENSE referenced SE input */
/* single ended vs differential */
#define GND_SE 0 /* Single-Ended */
#define GND_DIFF 1 /* Differential */
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