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Commit 24da741c authored by Tony Lindgren's avatar Tony Lindgren
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Merge branch 'dm814x-soc' into omap-for-v4.3/soc 

Update dm814x changes for sparse fixes to make data structures
static.

Conflicts:
	arch/arm/mach-omap2/omap_hwmod_81xx_data.c
parents 97d9a3d0 0f3ccb24
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Showing with 569 additions and 213 deletions
arch/arm/mach-omap2/board-generic.c
View file @ 24da741c
......@@ -169,7 +169,7 @@ static const char *const ti814x_boards_compat[] __initconst = {
NULL,
};
DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)")
DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = ti81xx_map_io,
.init_early = ti814x_init_early,
......
arch/arm/mach-omap2/clockdomain.h
View file @ 24da741c
......@@ -216,7 +216,8 @@ extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init ti81xx_clockdomains_init(void);
extern void __init ti814x_clockdomains_init(void);
extern void __init ti816x_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);
......
arch/arm/mach-omap2/clockdomains81xx_data.c
View file @ 24da741c
......@@ -165,7 +165,24 @@ static struct clockdomain default_l3_slow_816x_clkdm = {
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain *clockdomains_ti81xx[] __initdata = {
static struct clockdomain *clockdomains_ti814x[] __initdata = {
&alwon_l3_slow_81xx_clkdm,
&alwon_l3_med_81xx_clkdm,
&alwon_l3_fast_81xx_clkdm,
&alwon_ethernet_81xx_clkdm,
&mmu_81xx_clkdm,
&mmu_cfg_81xx_clkdm,
NULL,
};
void __init ti814x_clockdomains_init(void)
{
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
clkdm_register_clkdms(clockdomains_ti814x);
clkdm_complete_init();
}
static struct clockdomain *clockdomains_ti816x[] __initdata = {
&alwon_mpu_816x_clkdm,
&alwon_l3_slow_81xx_clkdm,
&alwon_l3_med_81xx_clkdm,
......@@ -185,10 +202,10 @@ static struct clockdomain *clockdomains_ti81xx[] __initdata = {
NULL,
};
void __init ti81xx_clockdomains_init(void)
void __init ti816x_clockdomains_init(void)
{
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
clkdm_register_clkdms(clockdomains_ti81xx);
clkdm_register_clkdms(clockdomains_ti816x);
clkdm_complete_init();
}
#endif
arch/arm/mach-omap2/control.c
View file @ 24da741c
......@@ -652,6 +652,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,am4-scm", .data = &ctrl_data },
{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
{ .compatible = "ti,dm814-scm", .data = &ctrl_data },
{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
......
arch/arm/mach-omap2/io.c
View file @ 24da741c
......@@ -608,11 +608,11 @@ void __init ti814x_init_early(void)
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
ti81xx_hwmod_init();
ti814x_clockdomains_init();
dm814x_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
omap_clk_soc_init = dm814x_dt_clk_init;
}
void __init ti816x_init_early(void)
......@@ -625,11 +625,11 @@ void __init ti816x_init_early(void)
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
ti81xx_hwmod_init();
ti816x_clockdomains_init();
dm816x_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = ti81xx_dt_clk_init;
omap_clk_soc_init = dm816x_dt_clk_init;
}
#endif
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ 24da741c
......@@ -3891,7 +3891,8 @@ void __init omap_hwmod_init(void)
soc_ops.init_clkdm = _init_clkdm;
soc_ops.update_context_lost = _omap4_update_context_lost;
soc_ops.get_context_lost = _omap4_get_context_lost;
} else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
} else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
soc_is_am43xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;
......
arch/arm/mach-omap2/omap_hwmod.h
View file @ 24da741c
......@@ -759,7 +759,8 @@ extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int ti81xx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
extern int dra7xx_hwmod_init(void);
int am43xx_hwmod_init(void);
......
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View file @ 24da741c
......@@ -32,21 +32,59 @@
*/
/*
* The alwon .clkctrl_offs field is offset from the CM_ALWON, that's
* TRM 18.7.17 CM_ALWON device register values minus 0x1400.
* Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
* also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
*/
#define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140
#define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144
#define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148
#define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c
#define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150
#define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154
#define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158
#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c
#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160
#define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164
#define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168
#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c
#define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190
#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194
#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198
#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c
#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8
#define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4
#define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0
#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4
#define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4
#define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8
#define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec
#define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0
#define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4
#define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8
#define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc
#define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200
#define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204
/* Registers specific to dm814x */
#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c
#define DM814X_CM_ALWON_ATL_CLKCTRL 0x170
#define DM814X_CM_ALWON_MLB_CLKCTRL 0x174
#define DM814X_CM_ALWON_PATA_CLKCTRL 0x178
#define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180
#define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184
#define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188
#define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4
#define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8
#define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc
#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0
#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218
#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c
#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220
#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224
#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228
/* Registers specific to dm816x */
#define DM816X_DM_ALWON_BASE 0x1400
#define DM816X_CM_ALWON_MCASP0_CLKCTRL (0x1540 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MCASP1_CLKCTRL (0x1544 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MCASP2_CLKCTRL (0x1548 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MCBSP_CLKCTRL (0x154c - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_UART_0_CLKCTRL (0x1550 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_UART_1_CLKCTRL (0x1554 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_UART_2_CLKCTRL (0x1558 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_GPIO_0_CLKCTRL (0x155c - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_GPIO_1_CLKCTRL (0x1560 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_I2C_0_CLKCTRL (0x1564 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_I2C_1_CLKCTRL (0x1568 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
......@@ -54,29 +92,11 @@
#define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_WDTIMER_CLKCTRL (0x158c - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SPI_CLKCTRL (0x1590 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MAILBOX_CLKCTRL (0x1594 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SPINBOX_CLKCTRL (0x1598 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MMUDATA_CLKCTRL (0x159c - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MMUCFG_CLKCTRL (0x15a8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_CONTRL_CLKCTRL (0x15c4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_GPMC_CLKCTRL (0x15d0 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_ETHERNET_0_CLKCTRL (0x15d4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_L3_CLKCTRL (0x15e4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_L4HS_CLKCTRL (0x15e8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_L4LS_CLKCTRL (0x15ec - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_RTC_CLKCTRL (0x15f0 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TPCC_CLKCTRL (0x15f4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TPTC0_CLKCTRL (0x15f8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TPTC1_CLKCTRL (0x15fc - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TPTC2_CLKCTRL (0x1600 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TPTC3_CLKCTRL (0x1604 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE)
......@@ -88,28 +108,28 @@
#define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET)
/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
static struct omap_hwmod dm816x_alwon_l3_slow_hwmod = {
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
.name = "alwon_l3_slow",
.clkdm_name = "alwon_l3s_clkdm",
.class = &l3_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod dm816x_default_l3_slow_hwmod = {
static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
.name = "default_l3_slow",
.clkdm_name = "default_l3_slow_clkdm",
.class = &l3_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod dm816x_alwon_l3_med_hwmod = {
static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
.name = "l3_med",
.clkdm_name = "alwon_l3_med_clkdm",
.class = &l3_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = {
static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
.name = "l3_fast",
.clkdm_name = "alwon_l3_fast_clkdm",
.class = &l3_hwmod_class,
......@@ -120,7 +140,7 @@ static struct omap_hwmod dm816x_alwon_l3_fast_hwmod = {
* L4 standard peripherals, see TRM table 1-12 for devices using this.
* See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
*/
static struct omap_hwmod dm816x_l4_ls_hwmod = {
static struct omap_hwmod dm81xx_l4_ls_hwmod = {
.name = "l4_ls",
.clkdm_name = "alwon_l3s_clkdm",
.class = &l4_hwmod_class,
......@@ -131,27 +151,54 @@ static struct omap_hwmod dm816x_l4_ls_hwmod = {
* table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
* table 1-73 for devices using 250MHz SYSCLK5 clock.
*/
static struct omap_hwmod dm816x_l4_hs_hwmod = {
static struct omap_hwmod dm81xx_l4_hs_hwmod = {
.name = "l4_hs",
.clkdm_name = "alwon_l3_med_clkdm",
.class = &l4_hwmod_class,
};
/* L3 slow -> L4 ls peripheral interface running at 125MHz */
static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_ls = {
.master = &dm816x_alwon_l3_slow_hwmod,
.slave = &dm816x_l4_ls_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
.master = &dm81xx_alwon_l3_slow_hwmod,
.slave = &dm81xx_l4_ls_hwmod,
.user = OCP_USER_MPU,
};
/* L3 med -> L4 fast peripheral interface running at 250MHz */
static struct omap_hwmod_ocp_if dm816x_alwon_l3_slow__l4_hs = {
.master = &dm816x_alwon_l3_med_hwmod,
.slave = &dm816x_l4_hs_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
.master = &dm81xx_alwon_l3_med_hwmod,
.slave = &dm81xx_l4_hs_hwmod,
.user = OCP_USER_MPU,
};
/* MPU */
static struct omap_hwmod dm814x_mpu_hwmod = {
.name = "mpu",
.clkdm_name = "alwon_l3s_clkdm",
.class = &mpu_hwmod_class,
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "mpu_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
.master = &dm814x_mpu_hwmod,
.slave = &dm81xx_alwon_l3_slow_hwmod,
.user = OCP_USER_MPU,
};
/* L3 med peripheral interface running at 200MHz */
static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
.master = &dm814x_mpu_hwmod,
.slave = &dm81xx_alwon_l3_med_hwmod,
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_mpu_hwmod = {
.name = "mpu",
.clkdm_name = "alwon_mpu_clkdm",
......@@ -168,14 +215,14 @@ static struct omap_hwmod dm816x_mpu_hwmod = {
static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
.master = &dm816x_mpu_hwmod,
.slave = &dm816x_alwon_l3_slow_hwmod,
.slave = &dm81xx_alwon_l3_slow_hwmod,
.user = OCP_USER_MPU,
};
/* L3 med peripheral interface running at 250MHz */
static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
.master = &dm816x_mpu_hwmod,
.slave = &dm816x_alwon_l3_med_hwmod,
.slave = &dm81xx_alwon_l3_med_hwmod,
.user = OCP_USER_MPU,
};
......@@ -197,13 +244,13 @@ static struct omap_hwmod_class uart_class = {
.sysc = &uart_sysc,
};
static struct omap_hwmod dm816x_uart1_hwmod = {
static struct omap_hwmod dm81xx_uart1_hwmod = {
.name = "uart1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_UART_0_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -211,20 +258,20 @@ static struct omap_hwmod dm816x_uart1_hwmod = {
.flags = DEBUG_TI81XXUART1_FLAGS,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__uart1 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_uart1_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_uart1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_uart2_hwmod = {
static struct omap_hwmod dm81xx_uart2_hwmod = {
.name = "uart2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_UART_1_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -232,20 +279,20 @@ static struct omap_hwmod dm816x_uart2_hwmod = {
.flags = DEBUG_TI81XXUART2_FLAGS,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__uart2 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_uart2_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_uart2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_uart3_hwmod = {
static struct omap_hwmod dm81xx_uart3_hwmod = {
.name = "uart3",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_UART_2_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -253,9 +300,9 @@ static struct omap_hwmod dm816x_uart3_hwmod = {
.flags = DEBUG_TI81XXUART3_FLAGS,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__uart3 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_uart3_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_uart3_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
......@@ -276,23 +323,23 @@ static struct omap_hwmod_class wd_timer_class = {
.reset = &omap2_wd_timer_reset,
};
static struct omap_hwmod dm816x_wd_timer_hwmod = {
static struct omap_hwmod dm81xx_wd_timer_hwmod = {
.name = "wd_timer",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk18_ck",
.flags = HWMOD_NO_IDLEST,
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_WDTIMER_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &wd_timer_class,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__wd_timer1 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_wd_timer_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_wd_timer_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
......@@ -320,27 +367,27 @@ static struct omap_hwmod dm81xx_i2c1_hwmod = {
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_I2C_0_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
.class = &i2c_class,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c1 = {
.master = &dm816x_l4_ls_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_i2c1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_i2c2_hwmod = {
static struct omap_hwmod dm81xx_i2c2_hwmod = {
.name = "i2c2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_I2C_1_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -358,9 +405,9 @@ static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__i2c2 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_i2c2_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_i2c2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
......@@ -378,7 +425,7 @@ static struct omap_hwmod dm81xx_elm_hwmod = {
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_elm_hwmod,
.user = OCP_USER_MPU,
};
......@@ -417,7 +464,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
.main_clk = "sysclk6_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_GPIO_0_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -427,7 +474,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_gpio1_hwmod,
.user = OCP_USER_MPU,
};
......@@ -443,7 +490,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
.main_clk = "sysclk6_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_GPIO_1_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -453,7 +500,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
};
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_gpio2_hwmod,
.user = OCP_USER_MPU,
};
......@@ -482,14 +529,14 @@ static struct omap_hwmod dm81xx_gpmc_hwmod = {
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_GPMC_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
.master = &dm816x_alwon_l3_slow_hwmod,
.master = &dm81xx_alwon_l3_slow_hwmod,
.slave = &dm81xx_gpmc_hwmod,
.user = OCP_USER_MPU,
};
......@@ -522,7 +569,7 @@ static struct omap_hwmod dm81xx_usbss_hwmod = {
};
static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
.master = &dm816x_default_l3_slow_hwmod,
.master = &dm81xx_default_l3_slow_hwmod,
.slave = &dm81xx_usbss_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -547,6 +594,22 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
.timer_capability = OMAP_TIMER_ALWON,
};
static struct omap_hwmod dm814x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer_sys_ck",
.dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer1_hwmod,
.clk = "timer_sys_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
......@@ -562,12 +625,28 @@ static struct omap_hwmod dm816x_timer1_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm814x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer_sys_ck",
.dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer2_hwmod,
.clk = "timer_sys_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod dm816x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
......@@ -583,7 +662,7 @@ static struct omap_hwmod dm816x_timer2_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -604,7 +683,7 @@ static struct omap_hwmod dm816x_timer3_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer3_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -625,7 +704,7 @@ static struct omap_hwmod dm816x_timer4_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer4_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -646,7 +725,7 @@ static struct omap_hwmod dm816x_timer5_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer5_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -667,7 +746,7 @@ static struct omap_hwmod dm816x_timer6_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer6_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -688,12 +767,68 @@ static struct omap_hwmod dm816x_timer7_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_timer7_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
/* CPSW on dm814x */
static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSS_HAS_RESET_STATUS,
.idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO,
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
.name = "cpgmac0",
.sysc = &dm814x_cpgmac_sysc,
};
static struct omap_hwmod dm814x_cpgmac0_hwmod = {
.name = "cpgmac0",
.class = &dm814x_cpgmac0_hwmod_class,
.clkdm_name = "alwon_ethernet_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "cpsw_125mhz_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
.name = "davinci_mdio",
};
static struct omap_hwmod dm814x_mdio_hwmod = {
.name = "davinci_mdio",
.class = &dm814x_mdio_hwmod_class,
.clkdm_name = "alwon_ethernet_clkdm",
.main_clk = "cpsw_125mhz_gclk",
};
static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
.master = &dm81xx_l4_hs_hwmod,
.slave = &dm814x_cpgmac0_hwmod,
.clk = "cpsw_125mhz_gclk",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
.master = &dm814x_cpgmac0_hwmod,
.slave = &dm814x_mdio_hwmod,
.user = OCP_USER_MPU,
.flags = HWMOD_NO_IDLEST,
};
/* EMAC Ethernet */
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
.rev_offs = 0x0,
......@@ -717,21 +852,21 @@ static struct omap_hwmod dm816x_emac0_hwmod = {
.class = &dm816x_emac_hwmod_class,
};
static struct omap_hwmod_ocp_if dm816x_l4_hs__emac0 = {
.master = &dm816x_l4_hs_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
.master = &dm81xx_l4_hs_hwmod,
.slave = &dm816x_emac0_hwmod,
.clk = "sysclk5_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm816x_mdio_hwmod_class = {
static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
.name = "davinci_mdio",
.sysc = &dm816x_emac_sysc,
};
static struct omap_hwmod dm816x_emac0_mdio_hwmod = {
static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
.name = "davinci_mdio",
.class = &dm816x_mdio_hwmod_class,
.class = &dm81xx_mdio_hwmod_class,
.clkdm_name = "alwon_ethernet_clkdm",
.main_clk = "sysclk24_ck",
.flags = HWMOD_NO_IDLEST,
......@@ -741,15 +876,15 @@ static struct omap_hwmod dm816x_emac0_mdio_hwmod = {
*/
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_ETHERNET_0_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_emac0__mdio = {
.master = &dm816x_l4_hs_hwmod,
.slave = &dm816x_emac0_mdio_hwmod,
static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
.master = &dm81xx_l4_hs_hwmod,
.slave = &dm81xx_emac0_mdio_hwmod,
.user = OCP_USER_MPU,
};
......@@ -768,7 +903,7 @@ static struct omap_hwmod dm816x_emac1_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
.master = &dm816x_l4_hs_hwmod,
.master = &dm81xx_l4_hs_hwmod,
.slave = &dm816x_emac1_hwmod,
.clk = "sysclk5_ck",
.user = OCP_USER_MPU,
......@@ -815,7 +950,7 @@ static struct omap_hwmod dm816x_mmc1_hwmod = {
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
.master = &dm816x_l4_ls_hwmod,
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm816x_mmc1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
......@@ -843,13 +978,13 @@ static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
.num_chipselect = 4,
};
static struct omap_hwmod dm816x_mcspi1_hwmod = {
static struct omap_hwmod dm81xx_mcspi1_hwmod = {
.name = "mcspi1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk10_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_SPI_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
......@@ -857,14 +992,14 @@ static struct omap_hwmod dm816x_mcspi1_hwmod = {
.dev_attr = &dm816x_mcspi1_dev_attr,
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__mcspi1 = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_mcspi1_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_mcspi1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = {
static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
......@@ -874,55 +1009,55 @@ static struct omap_hwmod_class_sysconfig dm816x_mailbox_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class dm816x_mailbox_hwmod_class = {
static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &dm816x_mailbox_sysc,
.sysc = &dm81xx_mailbox_sysc,
};
static struct omap_hwmod dm816x_mailbox_hwmod = {
static struct omap_hwmod dm81xx_mailbox_hwmod = {
.name = "mailbox",
.clkdm_name = "alwon_l3s_clkdm",
.class = &dm816x_mailbox_hwmod_class,
.class = &dm81xx_mailbox_hwmod_class,
.main_clk = "sysclk6_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_MAILBOX_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_l4_ls__mailbox = {
.master = &dm816x_l4_ls_hwmod,
.slave = &dm816x_mailbox_hwmod,
static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_mailbox_hwmod,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_class dm816x_tpcc_hwmod_class = {
static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
.name = "tpcc",
};
static struct omap_hwmod dm816x_tpcc_hwmod = {
static struct omap_hwmod dm81xx_tpcc_hwmod = {
.name = "tpcc",
.class = &dm816x_tpcc_hwmod_class,
.class = &dm81xx_tpcc_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TPCC_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tpcc = {
.master = &dm816x_alwon_l3_fast_hwmod,
.slave = &dm816x_tpcc_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tpcc_hwmod,
.clk = "sysclk4_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = {
static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
{
.pa_start = 0x49800000,
.pa_end = 0x49800000 + SZ_8K - 1,
......@@ -931,40 +1066,40 @@ static struct omap_hwmod_addr_space dm816x_tptc0_addr_space[] = {
{ },
};
static struct omap_hwmod_class dm816x_tptc0_hwmod_class = {
static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
.name = "tptc0",
};
static struct omap_hwmod dm816x_tptc0_hwmod = {
static struct omap_hwmod dm81xx_tptc0_hwmod = {
.name = "tptc0",
.class = &dm816x_tptc0_hwmod_class,
.class = &dm81xx_tptc0_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TPTC0_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc0 = {
.master = &dm816x_alwon_l3_fast_hwmod,
.slave = &dm816x_tptc0_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc0_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc0_addr_space,
.addr = dm81xx_tptc0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm816x_tptc0__alwon_l3_fast = {
.master = &dm816x_tptc0_hwmod,
.slave = &dm816x_alwon_l3_fast_hwmod,
static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
.master = &dm81xx_tptc0_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc0_addr_space,
.addr = dm81xx_tptc0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = {
static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
{
.pa_start = 0x49900000,
.pa_end = 0x49900000 + SZ_8K - 1,
......@@ -973,40 +1108,40 @@ static struct omap_hwmod_addr_space dm816x_tptc1_addr_space[] = {
{ },
};
static struct omap_hwmod_class dm816x_tptc1_hwmod_class = {
static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
.name = "tptc1",
};
static struct omap_hwmod dm816x_tptc1_hwmod = {
static struct omap_hwmod dm81xx_tptc1_hwmod = {
.name = "tptc1",
.class = &dm816x_tptc1_hwmod_class,
.class = &dm81xx_tptc1_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TPTC1_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc1 = {
.master = &dm816x_alwon_l3_fast_hwmod,
.slave = &dm816x_tptc1_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc1_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc1_addr_space,
.addr = dm81xx_tptc1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm816x_tptc1__alwon_l3_fast = {
.master = &dm816x_tptc1_hwmod,
.slave = &dm816x_alwon_l3_fast_hwmod,
static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
.master = &dm81xx_tptc1_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc1_addr_space,
.addr = dm81xx_tptc1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = {
static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
{
.pa_start = 0x49a00000,
.pa_end = 0x49a00000 + SZ_8K - 1,
......@@ -1015,40 +1150,40 @@ static struct omap_hwmod_addr_space dm816x_tptc2_addr_space[] = {
{ },
};
static struct omap_hwmod_class dm816x_tptc2_hwmod_class = {
static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
.name = "tptc2",
};
static struct omap_hwmod dm816x_tptc2_hwmod = {
static struct omap_hwmod dm81xx_tptc2_hwmod = {
.name = "tptc2",
.class = &dm816x_tptc2_hwmod_class,
.class = &dm81xx_tptc2_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TPTC2_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc2 = {
.master = &dm816x_alwon_l3_fast_hwmod,
.slave = &dm816x_tptc2_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc2_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc2_addr_space,
.addr = dm81xx_tptc2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm816x_tptc2__alwon_l3_fast = {
.master = &dm816x_tptc2_hwmod,
.slave = &dm816x_alwon_l3_fast_hwmod,
static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
.master = &dm81xx_tptc2_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc2_addr_space,
.addr = dm81xx_tptc2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = {
static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
{
.pa_start = 0x49b00000,
.pa_end = 0x49b00000 + SZ_8K - 1,
......@@ -1057,50 +1192,96 @@ static struct omap_hwmod_addr_space dm816x_tptc3_addr_space[] = {
{ },
};
static struct omap_hwmod_class dm816x_tptc3_hwmod_class = {
static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
.name = "tptc3",
};
static struct omap_hwmod dm816x_tptc3_hwmod = {
static struct omap_hwmod dm81xx_tptc3_hwmod = {
.name = "tptc3",
.class = &dm816x_tptc3_hwmod_class,
.class = &dm81xx_tptc3_hwmod_class,
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "sysclk4_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = DM816X_CM_ALWON_TPTC3_CLKCTRL,
.clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_ocp_if dm816x_alwon_l3_fast__tptc3 = {
.master = &dm816x_alwon_l3_fast_hwmod,
.slave = &dm816x_tptc3_hwmod,
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
.master = &dm81xx_alwon_l3_fast_hwmod,
.slave = &dm81xx_tptc3_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc3_addr_space,
.addr = dm81xx_tptc3_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if dm816x_tptc3__alwon_l3_fast = {
.master = &dm816x_tptc3_hwmod,
.slave = &dm816x_alwon_l3_fast_hwmod,
static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
.master = &dm81xx_tptc3_hwmod,
.slave = &dm81xx_alwon_l3_fast_hwmod,
.clk = "sysclk4_ck",
.addr = dm816x_tptc3_addr_space,
.addr = dm81xx_tptc3_addr_space,
.user = OCP_USER_MPU,
};
/*
* REVISIT: Test and enable the following once clocks work:
* dm81xx_l4_ls__gpio1
* dm81xx_l4_ls__gpio2
* dm81xx_l4_ls__mailbox
* dm81xx_alwon_l3_slow__gpmc
* dm81xx_default_l3_slow__usbss
*
* Also note that some devices share a single clkctrl_offs..
* For example, i2c1 and 3 share one, and i2c2 and 4 share one.
*/
static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm814x_mpu__alwon_l3_slow,
&dm814x_mpu__alwon_l3_med,
&dm81xx_alwon_l3_slow__l4_ls,
&dm81xx_alwon_l3_slow__l4_hs,
&dm81xx_l4_ls__uart1,
&dm81xx_l4_ls__uart2,
&dm81xx_l4_ls__uart3,
&dm81xx_l4_ls__wd_timer1,
&dm81xx_l4_ls__i2c1,
&dm81xx_l4_ls__i2c2,
&dm81xx_l4_ls__elm,
&dm81xx_l4_ls__mcspi1,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
&dm81xx_alwon_l3_fast__tptc2,
&dm81xx_alwon_l3_fast__tptc3,
&dm81xx_tptc0__alwon_l3_fast,
&dm81xx_tptc1__alwon_l3_fast,
&dm81xx_tptc2__alwon_l3_fast,
&dm81xx_tptc3__alwon_l3_fast,
&dm814x_l4_ls__timer1,
&dm814x_l4_ls__timer2,
&dm814x_l4_hs__cpgmac0,
&dm814x_cpgmac0__mdio,
NULL,
};
int __init dm814x_hwmod_init(void)
{
omap_hwmod_init();
return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
}
static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm816x_mpu__alwon_l3_slow,
&dm816x_mpu__alwon_l3_med,
&dm816x_alwon_l3_slow__l4_ls,
&dm816x_alwon_l3_slow__l4_hs,
&dm816x_l4_ls__uart1,
&dm816x_l4_ls__uart2,
&dm816x_l4_ls__uart3,
&dm816x_l4_ls__wd_timer1,
&dm816x_l4_ls__i2c1,
&dm816x_l4_ls__i2c2,
&dm81xx_alwon_l3_slow__l4_ls,
&dm81xx_alwon_l3_slow__l4_hs,
&dm81xx_l4_ls__uart1,
&dm81xx_l4_ls__uart2,
&dm81xx_l4_ls__uart3,
&dm81xx_l4_ls__wd_timer1,
&dm81xx_l4_ls__i2c1,
&dm81xx_l4_ls__i2c2,
&dm81xx_l4_ls__gpio1,
&dm81xx_l4_ls__gpio2,
&dm81xx_l4_ls__elm,
......@@ -1112,26 +1293,26 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm816x_l4_ls__timer5,
&dm816x_l4_ls__timer6,
&dm816x_l4_ls__timer7,
&dm816x_l4_ls__mcspi1,
&dm816x_l4_ls__mailbox,
&dm816x_l4_hs__emac0,
&dm816x_emac0__mdio,
&dm81xx_l4_ls__mcspi1,
&dm81xx_l4_ls__mailbox,
&dm81xx_l4_hs__emac0,
&dm81xx_emac0__mdio,
&dm816x_l4_hs__emac1,
&dm816x_alwon_l3_fast__tpcc,
&dm816x_alwon_l3_fast__tptc0,
&dm816x_alwon_l3_fast__tptc1,
&dm816x_alwon_l3_fast__tptc2,
&dm816x_alwon_l3_fast__tptc3,
&dm816x_tptc0__alwon_l3_fast,
&dm816x_tptc1__alwon_l3_fast,
&dm816x_tptc2__alwon_l3_fast,
&dm816x_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
&dm81xx_alwon_l3_fast__tptc2,
&dm81xx_alwon_l3_fast__tptc3,
&dm81xx_tptc0__alwon_l3_fast,
&dm81xx_tptc1__alwon_l3_fast,
&dm81xx_tptc2__alwon_l3_fast,
&dm81xx_tptc3__alwon_l3_fast,
&dm81xx_alwon_l3_slow__gpmc,
&dm81xx_default_l3_slow__usbss,
NULL,
};
int __init ti81xx_hwmod_init(void)
int __init dm816x_hwmod_init(void)
{
omap_hwmod_init();
return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
......
arch/arm/mach-omap2/powerdomains3xxx_data.c
View file @ 24da741c
......@@ -349,6 +349,41 @@ static struct powerdomain device_81xx_pwrdm = {
.voltdm = { .name = "core" },
};
static struct powerdomain gem_814x_pwrdm = {
.name = "gem_pwrdm",
.prcm_offs = TI814X_PRM_DSP_MOD,
.pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "dsp" },
};
static struct powerdomain ivahd_814x_pwrdm = {
.name = "ivahd_pwrdm",
.prcm_offs = TI814X_PRM_HDVICP_MOD,
.pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "iva" },
};
static struct powerdomain hdvpss_814x_pwrdm = {
.name = "hdvpss_pwrdm",
.prcm_offs = TI814X_PRM_HDVPSS_MOD,
.pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "dsp" },
};
static struct powerdomain sgx_814x_pwrdm = {
.name = "sgx_pwrdm",
.prcm_offs = TI814X_PRM_GFX_MOD,
.pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "core" },
};
static struct powerdomain isp_814x_pwrdm = {
.name = "isp_pwrdm",
.prcm_offs = TI814X_PRM_ISP_MOD,
.pwrsts = PWRSTS_OFF_ON,
.voltdm = { .name = "core" },
};
static struct powerdomain active_816x_pwrdm = {
.name = "active_pwrdm",
.prcm_offs = TI816X_PRM_ACTIVE_MOD,
......@@ -448,7 +483,18 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
NULL
};
static struct powerdomain *powerdomains_ti81xx[] __initdata = {
static struct powerdomain *powerdomains_ti814x[] __initdata = {
&alwon_81xx_pwrdm,
&device_81xx_pwrdm,
&gem_814x_pwrdm,
&ivahd_814x_pwrdm,
&hdvpss_814x_pwrdm,
&sgx_814x_pwrdm,
&isp_814x_pwrdm,
NULL
};
static struct powerdomain *powerdomains_ti816x[] __initdata = {
&alwon_81xx_pwrdm,
&device_81xx_pwrdm,
&active_816x_pwrdm,
......@@ -460,6 +506,73 @@ static struct powerdomain *powerdomains_ti81xx[] __initdata = {
NULL
};
/* TI81XX specific ops */
#define TI81XX_PM_PWSTCTRL 0x0000
#define TI81XX_RM_RSTCTRL 0x0010
#define TI81XX_PM_PWSTST 0x0004
static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
return 0;
}
static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
TI81XX_PM_PWSTCTRL,
OMAP_POWERSTATE_MASK);
}
static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
TI81XX_PM_PWSTST,
OMAP_POWERSTATEST_MASK);
}
static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
TI81XX_PM_PWSTST,
OMAP3430_LOGICSTATEST_MASK);
}
static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
u32 c = 0;
while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
TI81XX_PM_PWSTST) &
OMAP_INTRANSITION_MASK) &&
(c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
pr_err("powerdomain: %s timeout waiting for transition\n",
pwrdm->name);
return -EAGAIN;
}
pr_debug("powerdomain: completed transition in %d loops\n", c);
return 0;
}
/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
static struct pwrdm_ops ti81xx_pwrdm_operations = {
.pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
.pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
.pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
};
void __init omap3xxx_powerdomains_init(void)
{
unsigned int rev;
......@@ -467,15 +580,18 @@ void __init omap3xxx_powerdomains_init(void)
if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
return;
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
rev = omap_rev();
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
pwrdm_register_pwrdms(powerdomains_am35x);
} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
rev == TI8148_REV_ES2_1) {
pwrdm_register_pwrdms(powerdomains_ti814x);
} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
pwrdm_register_pwrdms(powerdomains_ti81xx);
pwrdm_register_pwrdms(powerdomains_ti816x);
} else {
pwrdm_register_pwrdms(powerdomains_omap3430_common);
......
arch/arm/mach-omap2/prcm-common.h
View file @ 24da741c
......@@ -51,6 +51,12 @@
/*
* TI81XX PRM module offsets
*/
#define TI814X_PRM_DSP_MOD 0x0a00
#define TI814X_PRM_HDVICP_MOD 0x0c00
#define TI814X_PRM_ISP_MOD 0x0d00
#define TI814X_PRM_HDVPSS_MOD 0x0e00
#define TI814X_PRM_GFX_MOD 0x0f00
#define TI81XX_PRM_DEVICE_MOD 0x0000
#define TI816X_PRM_ACTIVE_MOD 0x0a00
#define TI81XX_PRM_DEFAULT_MOD 0x0b00
......
drivers/clk/ti/Makefile
View file @ 24da741c
......@@ -2,7 +2,7 @@ obj-y += clk.o autoidle.o clockdomain.o
clk-common = dpll.o composite.o divider.o gate.o \
fixed-factor.o mux.o apll.o
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
clk-3xxx.o
......
drivers/clk/ti/clk-814x.c 0 → 100644
View file @ 24da741c
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*/
#include <linux/kernel.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
static struct ti_dt_clk dm814_clks[] = {
DT_CLK(NULL, "devosc_ck", "devosc_ck"),
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
{ .node_name = NULL },
};
int __init dm814x_dt_clk_init(void)
{
ti_dt_clocks_register(dm814_clks);
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(NULL, 0);
return 0;
}
drivers/clk/ti/clk-816x.c
View file @ 24da741c
......@@ -42,7 +42,7 @@ static const char *enable_init_clks[] = {
"ddr_pll_clk3",
};
int __init ti81xx_dt_clk_init(void)
int __init dm816x_dt_clk_init(void)
{
ti_dt_clocks_register(dm816x_clks);
omap2_clk_disable_autoidle_all();
......
include/linux/clk/ti.h
View file @ 24da741c
......@@ -329,7 +329,8 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
int omap3430_dt_clk_init(void);
int omap3630_dt_clk_init(void);
int am35xx_dt_clk_init(void);
int ti81xx_dt_clk_init(void);
int dm814x_dt_clk_init(void);
int dm816x_dt_clk_init(void);
int omap4xxx_dt_clk_init(void);
int omap5xxx_dt_clk_init(void);
int dra7xx_dt_clk_init(void);
......
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