Commit 24e6458d authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Bartlomiej Zolnierkiewicz

slc90e66: carry over fixes from piix driver

Synchronize with version 0.46 of the Intel PIIX/ICH driver:

- carry over Alan's and my own fixes in the tuneproc() method and my cleanups
  both there and in the ratemask() method;

- SLC90E66 only supports MW DMA modes 1/2 and SW DMA mode 2 (just like Intel
  chips), so don't claim support for other MW/SW DMA modes;

- don't check dor non-NULL drive->id in the ide_dma_check() method -- this is
  assumed to be true in all other drivers;

- do some coding/formatting cleanups while at it...
Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent 30dfd12f
/* /*
* linux/drivers/ide/pci/slc90e66.c Version 0.12 May 12, 2006 * linux/drivers/ide/pci/slc90e66.c Version 0.13 December 30, 2006
* *
* Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
* Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com>
...@@ -26,7 +26,7 @@ static u8 slc90e66_ratemask (ide_drive_t *drive) ...@@ -26,7 +26,7 @@ static u8 slc90e66_ratemask (ide_drive_t *drive)
u8 mode = 2; u8 mode = 2;
if (!eighty_ninty_three(drive)) if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1); mode = min_t(u8, mode, 1);
return mode; return mode;
} }
...@@ -65,12 +65,13 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio) ...@@ -65,12 +65,13 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
{ {
ide_hwif_t *hwif = HWIF(drive); ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev; struct pci_dev *dev = hwif->pci_dev;
int is_slave = (&hwif->drives[1] == drive); int is_slave = drive->dn & 1;
int master_port = hwif->channel ? 0x42 : 0x40; int master_port = hwif->channel ? 0x42 : 0x40;
int slave_port = 0x44; int slave_port = 0x44;
unsigned long flags; unsigned long flags;
u16 master_data; u16 master_data;
u8 slave_data; u8 slave_data;
int control = 0;
/* ISP RTC */ /* ISP RTC */
static const u8 timings[][2]= { static const u8 timings[][2]= {
{ 0, 0 }, { 0, 0 },
...@@ -79,22 +80,32 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio) ...@@ -79,22 +80,32 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
{ 2, 1 }, { 2, 1 },
{ 2, 3 }, }; { 2, 3 }, };
pio = ide_get_best_pio_mode(drive, pio, 5, NULL); pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
spin_lock_irqsave(&ide_lock, flags); spin_lock_irqsave(&ide_lock, flags);
pci_read_config_word(dev, master_port, &master_data); pci_read_config_word(dev, master_port, &master_data);
if (is_slave) {
master_data = master_data | 0x4000;
if (pio > 1) if (pio > 1)
control |= 1; /* Programmable timing on */
if (drive->media == ide_disk)
control |= 4; /* Prefetch, post write */
if (pio > 2)
control |= 2; /* IORDY */
if (is_slave) {
master_data |= 0x4000;
master_data &= ~0x0070;
if (pio > 1) {
/* enable PPE, IE and TIME */ /* enable PPE, IE and TIME */
master_data = master_data | 0x0070; master_data = master_data | (control << 4);
}
pci_read_config_byte(dev, slave_port, &slave_data); pci_read_config_byte(dev, slave_port, &slave_data);
slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
} else { } else {
master_data = master_data & 0xccf8; master_data &= ~0x3307;
if (pio > 1) if (pio > 1) {
/* enable PPE, IE and TIME */ /* enable PPE, IE and TIME */
master_data = master_data | 0x0007; master_data = master_data | control;
}
master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
} }
pci_write_config_word(dev, master_port, master_data); pci_write_config_word(dev, master_port, master_data);
...@@ -173,7 +184,7 @@ static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive) ...@@ -173,7 +184,7 @@ static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
drive->init_speed = 0; drive->init_speed = 0;
if (id && (id->capability & 1) && drive->autodma) { if ((id->capability & 1) && drive->autodma) {
if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive)) if (ide_use_dma(drive) && slc90e66_config_drive_for_dma(drive))
return hwif->ide_dma_on(drive); return hwif->ide_dma_on(drive);
...@@ -213,14 +224,16 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif) ...@@ -213,14 +224,16 @@ static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
hwif->atapi_dma = 1; hwif->atapi_dma = 1;
hwif->ultra_mask = 0x1f; hwif->ultra_mask = 0x1f;
hwif->mwdma_mask = 0x07; hwif->mwdma_mask = 0x06;
hwif->swdma_mask = 0x07; hwif->swdma_mask = 0x04;
if (!(hwif->udma_four)) if (!hwif->udma_four) {
/* bit[0(1)]: 0:80, 1:40 */ /* bit[0(1)]: 0:80, 1:40 */
hwif->udma_four = (reg47 & mask) ? 0 : 1; hwif->udma_four = (reg47 & mask) ? 0 : 1;
}
hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate; hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
if (!noautodma) if (!noautodma)
hwif->autodma = 1; hwif->autodma = 1;
hwif->drives[0].autodma = hwif->autodma; hwif->drives[0].autodma = hwif->autodma;
......
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