Commit 25b73c78 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman

staging: comedi: comedi.h: remove the extra indents

The extra indents in this file cause git diff to not know the
section where changes are being made. This results in diff outputs
like:

@@ -365,7 +365,10 @@

instead of the more informational:

@@ -365,6 +365,7 @@ struct comedi_cmd {

Remove all the extra indents.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ian Abbott <abbotti@mev.co.uk>
Acked-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 5d5d7c3b
......@@ -208,7 +208,7 @@
/* subdevice types */
enum comedi_subdevice_type {
enum comedi_subdevice_type {
COMEDI_SUBD_UNUSED, /* unused by driver */
COMEDI_SUBD_AI, /* analog input */
COMEDI_SUBD_AO, /* analog output */
......@@ -222,11 +222,11 @@
COMEDI_SUBD_PROC, /* processor, DSP */
COMEDI_SUBD_SERIAL, /* serial IO */
COMEDI_SUBD_PWM /* PWM */
};
};
/* configuration instructions */
enum configuration_ids {
enum configuration_ids {
INSN_CONFIG_DIO_INPUT = 0,
INSN_CONFIG_DIO_OUTPUT = 1,
INSN_CONFIG_DIO_OPENDRAIN = 2,
......@@ -241,7 +241,7 @@
INSN_CONFIG_FILTER = 24,
INSN_CONFIG_CHANGE_NOTIFY = 25,
/*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
INSN_CONFIG_SERIAL_CLOCK = 26, /*ALPHA*/
INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
INSN_CONFIG_DIO_QUERY = 28,
INSN_CONFIG_PWM_OUTPUT = 29,
......@@ -272,7 +272,7 @@
INSN_CONFIG_8254_READ_STATUS = 4098,
INSN_CONFIG_SET_ROUTING = 4099,
INSN_CONFIG_GET_ROUTING = 4109,
/* PWM */
/* PWM */
INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
......@@ -281,19 +281,19 @@
INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
/* gets H bridge data: duty cycle and the sign bit */
INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
};
};
enum comedi_io_direction {
enum comedi_io_direction {
COMEDI_INPUT = 0,
COMEDI_OUTPUT = 1,
COMEDI_OPENDRAIN = 2
};
};
enum comedi_support_level {
enum comedi_support_level {
COMEDI_UNKNOWN_SUPPORT = 0,
COMEDI_SUPPORTED,
COMEDI_UNSUPPORTED
};
};
/* ioctls */
......@@ -317,7 +317,7 @@
/* structures */
struct comedi_trig {
struct comedi_trig {
unsigned int subdev; /* subdevice */
unsigned int mode; /* mode */
unsigned int flags;
......@@ -330,23 +330,23 @@
unsigned int trigvar1;
unsigned int data_len;
unsigned int unused[3];
};
};
struct comedi_insn {
struct comedi_insn {
unsigned int insn;
unsigned int n;
unsigned int __user *data;
unsigned int subdev;
unsigned int chanspec;
unsigned int unused[3];
};
};
struct comedi_insnlist {
struct comedi_insnlist {
unsigned int n_insns;
struct comedi_insn __user *insns;
};
};
struct comedi_cmd {
struct comedi_cmd {
unsigned int subdev;
unsigned int flags;
......@@ -370,28 +370,28 @@
short __user *data; /* data list, size depends on subd flags */
unsigned int data_len;
};
};
struct comedi_chaninfo {
struct comedi_chaninfo {
unsigned int subdev;
unsigned int __user *maxdata_list;
unsigned int __user *flaglist;
unsigned int __user *rangelist;
unsigned int unused[4];
};
};
struct comedi_rangeinfo {
struct comedi_rangeinfo {
unsigned int range_type;
void __user *range_ptr;
};
};
struct comedi_krange {
struct comedi_krange {
int min; /* fixed point, multiply by 1e-6 */
int max; /* fixed point, multiply by 1e-6 */
unsigned int flags;
};
};
struct comedi_subdinfo {
struct comedi_subdinfo {
unsigned int type;
unsigned int n_chan;
unsigned int subd_flags;
......@@ -404,9 +404,9 @@
/* see support_level enum for values */
unsigned insn_bits_support;
unsigned int unused[8];
};
};
struct comedi_devinfo {
struct comedi_devinfo {
unsigned int version_code;
unsigned int n_subdevs;
char driver_name[COMEDI_NAMELEN];
......@@ -414,14 +414,14 @@
int read_subdevice;
int write_subdevice;
int unused[30];
};
};
struct comedi_devconfig {
struct comedi_devconfig {
char board_name[COMEDI_NAMELEN];
int options[COMEDI_NDEVCONFOPTS];
};
};
struct comedi_bufconfig {
struct comedi_bufconfig {
unsigned int subdevice;
unsigned int flags;
......@@ -429,9 +429,9 @@
unsigned int size;
unsigned int unused[4];
};
};
struct comedi_bufinfo {
struct comedi_bufinfo {
unsigned int subdevice;
unsigned int bytes_read;
......@@ -443,7 +443,7 @@
unsigned int bytes_written;
unsigned int unused[4];
};
};
/* range stuff */
......@@ -495,7 +495,7 @@
*/
enum i8254_mode {
enum i8254_mode {
I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
I8254_MODE2 = (2 << 1), /* Rate generator */
......@@ -506,30 +506,30 @@
I8254_BCD = 1, /* use binary-coded decimal instead of binary
* (pretty useless) */
I8254_BINARY = 0
};
};
static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
{
static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
{
if (pfi_channel < 10)
return 0x1 + pfi_channel;
else
return 0xb + pfi_channel;
}
}
static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
{
static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
{
if (rtsi_channel < 7)
return 0xb + rtsi_channel;
else
return 0x1b;
}
}
/* mode bits for NI general-purpose counters, set with
* INSN_CONFIG_SET_COUNTER_MODE */
#define NI_GPCT_COUNTING_MODE_SHIFT 16
#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
enum ni_gpct_mode_bits {
enum ni_gpct_mode_bits {
NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
......@@ -591,11 +591,11 @@
NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
NI_GPCT_OR_GATE_BIT = 0x10000000,
NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
};
};
/* Bits for setting a clock source with
* INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
enum ni_gpct_clock_source_bits {
enum ni_gpct_clock_source_bits {
NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
......@@ -615,26 +615,26 @@
/* divide source by 8 */
NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
};
static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
{
};
static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
{
/* NI 660x-specific */
return 0x10 + n;
}
static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
{
}
static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
{
return 0x18 + n;
}
static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
{
}
static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
{
/* no pfi on NI 660x */
return 0x20 + n;
}
}
/* Possibilities for setting a gate source with
INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
May be bitwise-or'd with CR_EDGE or CR_INVERT. */
enum ni_gpct_gate_select {
enum ni_gpct_gate_select {
/* m-series gates */
NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
NI_GPCT_AI_START2_GATE_SELECT = 0x12,
......@@ -654,44 +654,44 @@ May be bitwise-or'd with CR_EDGE or CR_INVERT. */
* we should add them here with an offset of 0x300 when
* known. */
NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
};
static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
{
};
static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
{
return 0x102 + n;
}
static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
{
}
static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
{
return NI_USUAL_RTSI_SELECT(n);
}
static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
{
}
static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
{
return NI_USUAL_PFI_SELECT(n);
}
static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
{
}
static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
{
return 0x202 + n;
}
}
/* Possibilities for setting a source with
INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
enum ni_gpct_other_index {
enum ni_gpct_other_index {
NI_GPCT_SOURCE_ENCODER_A,
NI_GPCT_SOURCE_ENCODER_B,
NI_GPCT_SOURCE_ENCODER_Z
};
enum ni_gpct_other_select {
};
enum ni_gpct_other_select {
/* m-series gates */
/* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
};
static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
{
};
static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
{
return NI_USUAL_PFI_SELECT(n);
}
}
/* start sources for ni general-purpose counters for use with
INSN_CONFIG_ARM */
enum ni_gpct_arm_source {
enum ni_gpct_arm_source {
NI_GPCT_ARM_IMMEDIATE = 0x0,
NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
* and the adjacent paired
......@@ -702,10 +702,10 @@ INSN_CONFIG_ARM */
* through to the hardware. This will at least allow someone to
* figure out what the bits do later. */
NI_GPCT_ARM_UNKNOWN = 0x1000,
};
};
/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
enum ni_gpct_filter_select {
enum ni_gpct_filter_select {
NI_GPCT_FILTER_OFF = 0x0,
NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
......@@ -713,19 +713,19 @@ INSN_CONFIG_ARM */
NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
};
};
/* PFI digital filtering options for ni m-series for use with
* INSN_CONFIG_FILTER. */
enum ni_pfi_filter_select {
enum ni_pfi_filter_select {
NI_PFI_FILTER_OFF = 0x0,
NI_PFI_FILTER_125ns = 0x1,
NI_PFI_FILTER_6425ns = 0x2,
NI_PFI_FILTER_2550us = 0x3
};
};
/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
enum ni_mio_clock_source {
enum ni_mio_clock_source {
NI_MIO_INTERNAL_CLOCK = 0,
NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use
NI_MIO_PLL_RTSI_CLOCK() */
......@@ -733,16 +733,16 @@ INSN_CONFIG_ARM */
NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
NI_MIO_PLL_PXI10_CLOCK = 3,
NI_MIO_PLL_RTSI0_CLOCK = 4
};
static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
{
};
static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
{
return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
}
}
/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
The numbers assigned are not arbitrary, they correspond to the bits required
to program the board. */
enum ni_rtsi_routing {
enum ni_rtsi_routing {
NI_RTSI_OUTPUT_ADR_START1 = 0,
NI_RTSI_OUTPUT_ADR_START2 = 1,
NI_RTSI_OUTPUT_SCLKG = 2,
......@@ -754,18 +754,18 @@ INSN_CONFIG_ARM */
NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI
* clock on line 7 */
};
static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
{
};
static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
{
return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
}
}
/* Signals which can be routed to an NI PFI pin on an m-series board with
* INSN_CONFIG_SET_ROUTING. These numbers are also returned by
* INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
* cannot be changed. The numbers assigned are not arbitrary, they correspond
* to the bits required to program the board. */
enum ni_pfi_routing {
enum ni_pfi_routing {
NI_PFI_OUTPUT_PFI_DEFAULT = 0,
NI_PFI_OUTPUT_AI_START1 = 1,
NI_PFI_OUTPUT_AI_START2 = 2,
......@@ -790,11 +790,11 @@ INSN_CONFIG_ARM */
NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
NI_PFI_OUTPUT_CDI_SAMPLE = 29,
NI_PFI_OUTPUT_CDO_UPDATE = 30
};
static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
{
};
static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
{
return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
}
}
/* Signals which can be routed to output on a NI PFI pin on a 660x board
with INSN_CONFIG_SET_ROUTING. The numbers assigned are
......@@ -802,34 +802,34 @@ INSN_CONFIG_ARM */
to program the board. Lines 0 to 7 can only be set to
NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
NI_660X_PFI_OUTPUT_COUNTER. */
enum ni_660x_pfi_routing {
enum ni_660x_pfi_routing {
NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */
};
};
/* NI External Trigger lines. These values are not arbitrary, but are related
* to the bits required to program the board (offset by 1 for historical
* reasons). */
static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
{
static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
{
return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
}
static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
{
}
static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
{
return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
}
}
/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
enum comedi_counter_status_flags {
enum comedi_counter_status_flags {
COMEDI_COUNTER_ARMED = 0x1,
COMEDI_COUNTER_COUNTING = 0x2,
COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
};
};
/* Clock sources for CDIO subdevice on NI m-series boards. Used as the
* scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
* with CR_INVERT to change polarity. */
enum ni_m_series_cdio_scan_begin_src {
enum ni_m_series_cdio_scan_begin_src {
NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
......@@ -840,39 +840,38 @@ INSN_CONFIG_ARM */
NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
};
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
{
};
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
{
return NI_USUAL_PFI_SELECT(pfi_channel);
}
static inline unsigned
NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
{
}
static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
{
return NI_USUAL_RTSI_SELECT(rtsi_channel);
}
}
/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
* boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to
* change polarity. */
static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
{
static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
{
return NI_USUAL_PFI_SELECT(pfi_channel);
}
static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
{
}
static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
{
return NI_USUAL_RTSI_SELECT(rtsi_channel);
}
}
/* Bits for setting a clock source with
* INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
enum ni_freq_out_clock_source_bits {
enum ni_freq_out_clock_source_bits {
NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */
};
};
/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
* 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
enum amplc_dio_clock_source {
enum amplc_dio_clock_source {
AMPLC_DIO_CLK_CLKN, /* per channel external clock
input/output pin (pin is only an
input when clock source set to this
......@@ -890,11 +889,11 @@ INSN_CONFIG_ARM */
subdevice is the last counter
subdevice) */
AMPLC_DIO_CLK_EXT /* per chip external input pin */
};
};
/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
* 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
enum amplc_dio_gate_source {
enum amplc_dio_gate_source {
AMPLC_DIO_GAT_VCC, /* internal high logic level */
AMPLC_DIO_GAT_GND, /* internal low logic level */
AMPLC_DIO_GAT_GATN, /* per channel external gate input */
......@@ -909,6 +908,6 @@ INSN_CONFIG_ARM */
AMPLC_DIO_GAT_RESERVED5,
AMPLC_DIO_GAT_RESERVED6,
AMPLC_DIO_GAT_RESERVED7
};
};
#endif /* _COMEDI_H */
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