Commit 263432b0 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'ast-updates' of ssh://people.freedesktop.org/~/linux into drm-next

Pull in latest updates to AST driver.

* 'ast-updates' of ssh://people.freedesktop.org/~/linux:
  drm/ast: initial DP501 support (v0.2)
  drm/ast: rename the mindwm/moutdwm and deinline them
  drm/ast: resync the dram post code with upstream
  drm/ast: add AST 2400 support.
  drm/ast: add widescreen + rb modes from X.org driver (v2)
parents e5daa1dd 83c6620b
......@@ -4,6 +4,6 @@
ccflags-y := -Iinclude/drm
ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o
ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o ast_dp501.o
obj-$(CONFIG_DRM_AST) := ast.o
#include <linux/firmware.h>
#include <drm/drmP.h>
#include "ast_drv.h"
MODULE_FIRMWARE("ast_dp501_fw.bin");
int ast_load_dp501_microcode(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
static char *fw_name = "ast_dp501_fw.bin";
int err;
err = request_firmware(&ast->dp501_fw, fw_name, dev->dev);
if (err)
return err;
return 0;
}
static void send_ack(struct ast_private *ast)
{
u8 sendack;
sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
sendack |= 0x80;
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
}
static void send_nack(struct ast_private *ast)
{
u8 sendack;
sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
sendack &= ~0x80;
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
}
static bool wait_ack(struct ast_private *ast)
{
u8 waitack;
u32 retry = 0;
do {
waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
waitack &= 0x80;
udelay(100);
} while ((!waitack) && (retry++ < 1000));
if (retry < 1000)
return true;
else
return false;
}
static bool wait_nack(struct ast_private *ast)
{
u8 waitack;
u32 retry = 0;
do {
waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
waitack &= 0x80;
udelay(100);
} while ((waitack) && (retry++ < 1000));
if (retry < 1000)
return true;
else
return false;
}
static void set_cmd_trigger(struct ast_private *ast)
{
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
}
static void clear_cmd_trigger(struct ast_private *ast)
{
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
}
#if 0
static bool wait_fw_ready(struct ast_private *ast)
{
u8 waitready;
u32 retry = 0;
do {
waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
waitready &= 0x40;
udelay(100);
} while ((!waitready) && (retry++ < 1000));
if (retry < 1000)
return true;
else
return false;
}
#endif
static bool ast_write_cmd(struct drm_device *dev, u8 data)
{
struct ast_private *ast = dev->dev_private;
int retry = 0;
if (wait_nack(ast)) {
send_nack(ast);
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
send_ack(ast);
set_cmd_trigger(ast);
do {
if (wait_ack(ast)) {
clear_cmd_trigger(ast);
send_nack(ast);
return true;
}
} while (retry++ < 100);
}
clear_cmd_trigger(ast);
send_nack(ast);
return false;
}
static bool ast_write_data(struct drm_device *dev, u8 data)
{
struct ast_private *ast = dev->dev_private;
if (wait_nack(ast)) {
send_nack(ast);
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
send_ack(ast);
if (wait_ack(ast)) {
send_nack(ast);
return true;
}
}
send_nack(ast);
return false;
}
#if 0
static bool ast_read_data(struct drm_device *dev, u8 *data)
{
struct ast_private *ast = dev->dev_private;
u8 tmp;
*data = 0;
if (wait_ack(ast) == false)
return false;
tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
*data = tmp;
if (wait_nack(ast) == false) {
send_nack(ast);
return false;
}
send_nack(ast);
return true;
}
static void clear_cmd(struct ast_private *ast)
{
send_nack(ast);
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
}
#endif
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
{
ast_write_cmd(dev, 0x40);
ast_write_data(dev, mode);
msleep(10);
}
static u32 get_fw_base(struct ast_private *ast)
{
return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
}
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
{
struct ast_private *ast = dev->dev_private;
u32 i, data;
u32 boot_address;
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (data) {
boot_address = get_fw_base(ast);
for (i = 0; i < size; i += 4)
*(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
return true;
}
return false;
}
bool ast_launch_m68k(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u32 i, data, len = 0;
u32 boot_address;
u8 *fw_addr = NULL;
u8 jreg;
data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
if (!data) {
if (ast->dp501_fw_addr) {
fw_addr = ast->dp501_fw_addr;
len = 32*1024;
} else if (ast->dp501_fw) {
fw_addr = (u8 *)ast->dp501_fw->data;
len = ast->dp501_fw->size;
}
/* Get BootAddress */
ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
data = ast_mindwm(ast, 0x1e6e0004);
switch (data & 0x03) {
case 0:
boot_address = 0x44000000;
break;
default:
case 1:
boot_address = 0x48000000;
break;
case 2:
boot_address = 0x50000000;
break;
case 3:
boot_address = 0x60000000;
break;
}
boot_address -= 0x200000; /* -2MB */
/* copy image to buffer */
for (i = 0; i < len; i += 4) {
data = *(u32 *)(fw_addr + i);
ast_moutdwm(ast, boot_address + i, data);
}
/* Init SCU */
ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
/* Launch FW */
ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
ast_moutdwm(ast, 0x1e6e2100, 1);
/* Update Scratch */
data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
data |= 0x800;
ast_moutdwm(ast, 0x1e6e2040, data);
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
jreg |= 0x02;
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
}
return true;
}
u8 ast_get_dp501_max_clk(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u32 boot_address, offset, data;
u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
boot_address = get_fw_base(ast);
/* validate FW version */
offset = 0xf000;
data = ast_mindwm(ast, boot_address + offset);
if ((data & 0xf0) != 0x10) /* version: 1x */
return maxclk;
/* Read Link Capability */
offset = 0xf014;
*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
if (linkcap[2] == 0) {
linkrate = linkcap[0];
linklanes = linkcap[1];
data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
if (data > 0xff)
data = 0xff;
maxclk = (u8)data;
}
return maxclk;
}
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
{
struct ast_private *ast = dev->dev_private;
u32 i, boot_address, offset, data;
boot_address = get_fw_base(ast);
/* validate FW version */
offset = 0xf000;
data = ast_mindwm(ast, boot_address + offset);
if ((data & 0xf0) != 0x10)
return false;
/* validate PnP Monitor */
offset = 0xf010;
data = ast_mindwm(ast, boot_address + offset);
if (!(data & 0x01))
return false;
/* Read EDID */
offset = 0xf020;
for (i = 0; i < 128; i += 4) {
data = ast_mindwm(ast, boot_address + offset + i);
*(u32 *)(ediddata + i) = data;
}
return true;
}
static bool ast_init_dvo(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u8 jreg;
u32 data;
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
ast_write32(ast, 0x12000, 0x1688a8a8);
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
if (!(jreg & 0x80)) {
/* Init SCU DVO Settings */
data = ast_read32(ast, 0x12008);
/* delay phase */
data &= 0xfffff8ff;
data |= 0x00000500;
ast_write32(ast, 0x12008, data);
if (ast->chip == AST2300) {
data = ast_read32(ast, 0x12084);
/* multi-pins for DVO single-edge */
data |= 0xfffe0000;
ast_write32(ast, 0x12084, data);
data = ast_read32(ast, 0x12088);
/* multi-pins for DVO single-edge */
data |= 0x000fffff;
ast_write32(ast, 0x12088, data);
data = ast_read32(ast, 0x12090);
/* multi-pins for DVO single-edge */
data &= 0xffffffcf;
data |= 0x00000020;
ast_write32(ast, 0x12090, data);
} else { /* AST2400 */
data = ast_read32(ast, 0x12088);
/* multi-pins for DVO single-edge */
data |= 0x30000000;
ast_write32(ast, 0x12088, data);
data = ast_read32(ast, 0x1208c);
/* multi-pins for DVO single-edge */
data |= 0x000000cf;
ast_write32(ast, 0x1208c, data);
data = ast_read32(ast, 0x120a4);
/* multi-pins for DVO single-edge */
data |= 0xffff0000;
ast_write32(ast, 0x120a4, data);
data = ast_read32(ast, 0x120a8);
/* multi-pins for DVO single-edge */
data |= 0x0000000f;
ast_write32(ast, 0x120a8, data);
data = ast_read32(ast, 0x12094);
/* multi-pins for DVO single-edge */
data |= 0x00000002;
ast_write32(ast, 0x12094, data);
}
}
/* Force to DVO */
data = ast_read32(ast, 0x1202c);
data &= 0xfffbffff;
ast_write32(ast, 0x1202c, data);
/* Init VGA DVO Settings */
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
return true;
}
void ast_init_3rdtx(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u8 jreg;
u32 data;
if (ast->chip == AST2300 || ast->chip == AST2400) {
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
switch (jreg & 0x0e) {
case 0x04:
ast_init_dvo(dev);
break;
case 0x08:
ast_launch_m68k(dev);
break;
case 0x0c:
ast_init_dvo(dev);
break;
default:
if (ast->tx_chip_type == AST_TX_SIL164)
ast_init_dvo(dev);
else {
ast_write32(ast, 0x12000, 0x1688a8a8);
data = ast_read32(ast, 0x1202c);
data &= 0xfffcffff;
ast_write32(ast, 0, data);
}
}
}
}
......@@ -61,9 +61,17 @@ enum ast_chip {
AST2200,
AST2150,
AST2300,
AST2400,
AST1180,
};
enum ast_tx_chip {
AST_TX_NONE,
AST_TX_SIL164,
AST_TX_ITE66121,
AST_TX_DP501,
};
#define AST_DRAM_512Mx16 0
#define AST_DRAM_1Gx16 1
#define AST_DRAM_512Mx32 2
......@@ -102,6 +110,12 @@ struct ast_private {
* we have. */
struct ttm_bo_kmap_obj cache_kmap;
int next_cursor;
bool support_wide_screen;
enum ast_tx_chip tx_chip_type;
u8 dp501_maxclk;
u8 *dp501_fw_addr;
const struct firmware *dp501_fw; /* dp501 fw */
};
int ast_driver_load(struct drm_device *dev, unsigned long flags);
......@@ -368,4 +382,14 @@ int ast_mmap(struct file *filp, struct vm_area_struct *vma);
/* ast post */
void ast_post_gpu(struct drm_device *dev);
u32 ast_mindwm(struct ast_private *ast, u32 r);
void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
/* ast dp501 */
int ast_load_dp501_microcode(struct drm_device *dev);
void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
bool ast_launch_m68k(struct drm_device *dev);
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
u8 ast_get_dp501_max_clk(struct drm_device *dev);
void ast_init_3rdtx(struct drm_device *dev);
#endif
......@@ -66,12 +66,16 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
static int ast_detect_chip(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
uint32_t data, jreg;
if (dev->pdev->device == PCI_CHIP_AST1180) {
ast->chip = AST1100;
DRM_INFO("AST 1180 detected\n");
} else {
if (dev->pdev->revision >= 0x20) {
if (dev->pdev->revision >= 0x30) {
ast->chip = AST2400;
DRM_INFO("AST 2400 detected\n");
} else if (dev->pdev->revision >= 0x20) {
ast->chip = AST2300;
DRM_INFO("AST 2300 detected\n");
} else if (dev->pdev->revision >= 0x10) {
......@@ -104,6 +108,59 @@ static int ast_detect_chip(struct drm_device *dev)
DRM_INFO("AST 2000 detected\n");
}
}
switch (ast->chip) {
case AST1180:
ast->support_wide_screen = true;
break;
case AST2000:
ast->support_wide_screen = false;
break;
default:
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
if (!(jreg & 0x80))
ast->support_wide_screen = true;
else if (jreg & 0x01)
ast->support_wide_screen = true;
else {
ast->support_wide_screen = false;
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
data = ast_read32(ast, 0x1207c);
data &= 0x300;
if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
ast->support_wide_screen = true;
if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
ast->support_wide_screen = true;
}
break;
}
ast->tx_chip_type = AST_TX_NONE;
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
if (jreg & 0x80)
ast->tx_chip_type = AST_TX_SIL164;
if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
switch (jreg) {
case 0x04:
ast->tx_chip_type = AST_TX_SIL164;
break;
case 0x08:
ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
if (ast->dp501_fw_addr) {
/* backup firmware */
if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
kfree(ast->dp501_fw_addr);
ast->dp501_fw_addr = NULL;
}
}
/* fallthrough */
case 0x0c:
ast->tx_chip_type = AST_TX_DP501;
}
}
return 0;
}
......@@ -129,7 +186,7 @@ static int ast_get_dram_info(struct drm_device *dev)
else
ast->dram_bus_width = 32;
if (ast->chip == AST2300) {
if (ast->chip == AST2300 || ast->chip == AST2400) {
switch (data & 0x03) {
case 0:
ast->dram_type = AST_DRAM_512Mx16;
......@@ -257,17 +314,32 @@ static u32 ast_get_vram_info(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
u8 jreg;
u32 vram_size;
ast_open_key(ast);
vram_size = AST_VIDMEM_DEFAULT_SIZE;
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
switch (jreg & 3) {
case 0: return AST_VIDMEM_SIZE_8M;
case 1: return AST_VIDMEM_SIZE_16M;
case 2: return AST_VIDMEM_SIZE_32M;
case 3: return AST_VIDMEM_SIZE_64M;
case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
}
return AST_VIDMEM_DEFAULT_SIZE;
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
switch (jreg & 0x03) {
case 1:
vram_size -= 0x100000;
break;
case 2:
vram_size -= 0x200000;
break;
case 3:
vram_size -= 0x400000;
break;
}
return vram_size;
}
int ast_driver_load(struct drm_device *dev, unsigned long flags)
......@@ -316,6 +388,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
if (ast->chip == AST2100 ||
ast->chip == AST2200 ||
ast->chip == AST2300 ||
ast->chip == AST2400 ||
ast->chip == AST1180) {
dev->mode_config.max_width = 1920;
dev->mode_config.max_height = 2048;
......@@ -343,6 +416,7 @@ int ast_driver_unload(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
kfree(ast->dp501_fw_addr);
ast_mode_fini(dev);
ast_fbdev_fini(dev);
drm_mode_config_cleanup(dev);
......
......@@ -115,10 +115,16 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
else
vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
break;
case 1360:
vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
break;
case 1440:
vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
break;
case 1600:
if (crtc->mode.crtc_vdisplay == 900)
vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
else
vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
break;
case 1680:
......@@ -175,6 +181,8 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
if (vbios_mode->enh_table->flags & NewModeInfo) {
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
......@@ -184,6 +192,7 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
}
}
return true;
......@@ -389,7 +398,7 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
/* Set Threshold */
if (ast->chip == AST2300) {
if (ast->chip == AST2300 || ast->chip == AST2400) {
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
} else if (ast->chip == AST2100 ||
......@@ -451,9 +460,13 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
if (ast->tx_chip_type == AST_TX_DP501)
ast_set_dp501_video_output(crtc->dev, 1);
ast_crtc_load_lut(crtc);
break;
case DRM_MODE_DPMS_OFF:
if (ast->tx_chip_type == AST_TX_DP501)
ast_set_dp501_video_output(crtc->dev, 0);
ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
break;
}
......@@ -729,9 +742,23 @@ static int ast_encoder_init(struct drm_device *dev)
static int ast_get_modes(struct drm_connector *connector)
{
struct ast_connector *ast_connector = to_ast_connector(connector);
struct ast_private *ast = connector->dev->dev_private;
struct edid *edid;
int ret;
bool flags = false;
if (ast->tx_chip_type == AST_TX_DP501) {
ast->dp501_maxclk = 0xff;
edid = kmalloc(128, GFP_KERNEL);
if (!edid)
return -ENOMEM;
flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
if (flags)
ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
else
kfree(edid);
}
if (!flags)
edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
if (edid) {
drm_mode_connector_update_edid_property(&ast_connector->base, edid);
......@@ -743,6 +770,61 @@ static int ast_get_modes(struct drm_connector *connector)
return 0;
}
static int ast_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct ast_private *ast = connector->dev->dev_private;
int flags = MODE_NOMODE;
uint32_t jtemp;
if (ast->support_wide_screen) {
if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
return MODE_OK;
if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
return MODE_OK;
if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
return MODE_OK;
if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
return MODE_OK;
if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
return MODE_OK;
if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
return MODE_OK;
if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
if (jtemp & 0x01)
return MODE_NOMODE;
else
return MODE_OK;
}
}
}
switch (mode->hdisplay) {
case 640:
if (mode->vdisplay == 480) flags = MODE_OK;
break;
case 800:
if (mode->vdisplay == 600) flags = MODE_OK;
break;
case 1024:
if (mode->vdisplay == 768) flags = MODE_OK;
break;
case 1280:
if (mode->vdisplay == 1024) flags = MODE_OK;
break;
case 1600:
if (mode->vdisplay == 1200) flags = MODE_OK;
break;
default:
return flags;
}
return flags;
}
static void ast_connector_destroy(struct drm_connector *connector)
{
struct ast_connector *ast_connector = to_ast_connector(connector);
......@@ -759,6 +841,7 @@ ast_connector_detect(struct drm_connector *connector, bool force)
}
static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
.mode_valid = ast_mode_valid,
.get_modes = ast_get_modes,
.best_encoder = ast_best_single_encoder,
};
......
......@@ -78,7 +78,7 @@ ast_set_def_ext_reg(struct drm_device *dev)
for (i = 0x81; i <= 0x8f; i++)
ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
if (ast->chip == AST2300) {
if (ast->chip == AST2300 || ast->chip == AST2400) {
if (dev->pdev->revision >= 0x20)
ext_reg_info = extreginfo_ast2300;
else
......@@ -102,23 +102,32 @@ ast_set_def_ext_reg(struct drm_device *dev)
/* Enable RAMDAC for A1 */
reg = 0x04;
if (ast->chip == AST2300)
if (ast->chip == AST2300 || ast->chip == AST2400)
reg |= 0x20;
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
}
static inline u32 mindwm(struct ast_private *ast, u32 r)
u32 ast_mindwm(struct ast_private *ast, u32 r)
{
uint32_t data;
ast_write32(ast, 0xf004, r & 0xffff0000);
ast_write32(ast, 0xf000, 0x1);
do {
data = ast_read32(ast, 0xf004) & 0xffff0000;
} while (data != (r & 0xffff0000));
return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
}
static inline void moutdwm(struct ast_private *ast, u32 r, u32 v)
void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
{
uint32_t data;
ast_write32(ast, 0xf004, r & 0xffff0000);
ast_write32(ast, 0xf000, 0x1);
do {
data = ast_read32(ast, 0xf004) & 0xffff0000;
} while (data != (r & 0xffff0000));
ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
}
......@@ -154,28 +163,28 @@ static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x40;
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
if (++timeout > TIMEOUT_AST2150) {
moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0xffffffff;
}
} while (!data);
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x40;
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
if (++timeout > TIMEOUT_AST2150) {
moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0xffffffff;
}
} while (!data);
data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
moutdwm(ast, 0x1e6e0070, 0x00000000);
data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return data;
}
......@@ -184,18 +193,18 @@ static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x40;
data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
if (++timeout > TIMEOUT_AST2150) {
moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0xffffffff;
}
} while (!data);
data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
moutdwm(ast, 0x1e6e0070, 0x00000000);
data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return data;
}
#endif
......@@ -215,7 +224,7 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw)
u32 patcnt, loop;
for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
if (cbrtest_ast2150(ast))
break;
......@@ -237,7 +246,7 @@ static void cbrdlli_ast2150(struct ast_private *ast, int busw)
passcnt = 0;
for (dlli = 0; dlli < 100; dlli++) {
moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
data = cbrscan_ast2150(ast, busw);
if (data != 0) {
if (data & 0x1) {
......@@ -254,7 +263,7 @@ static void cbrdlli_ast2150(struct ast_private *ast, int busw)
goto cbr_start;
dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
}
......@@ -365,10 +374,12 @@ void ast_post_gpu(struct drm_device *dev)
ast_open_key(ast);
ast_set_def_ext_reg(dev);
if (ast->chip == AST2300)
if (ast->chip == AST2300 || ast->chip == AST2400)
ast_init_dram_2300(dev);
else
ast_init_dram_reg(dev);
ast_init_3rdtx(dev);
}
/* AST 2300 DRAM settings */
......@@ -403,6 +414,7 @@ struct ast2300_dram_param {
/*
* DQSI DLL CBR Setting
*/
#define CBR_SIZE0 ((1 << 10) - 1)
#define CBR_SIZE1 ((4 << 10) - 1)
#define CBR_SIZE2 ((64 << 10) - 1)
#define CBR_PASSNUM 5
......@@ -423,88 +435,84 @@ static const u32 pattern[8] = {
0x7C61D253
};
#if 0 /* unused in DDX, included for completeness */
static int mmc_test_burst(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x3000;
data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
if (data & 0x2000) {
return 0;
}
if (++timeout > TIMEOUT) {
moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 0;
}
} while (!data);
moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
return 1;
}
#endif
static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x1000;
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
if (++timeout > TIMEOUT) {
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return -1;
}
} while (!data);
data = mindwm(ast, 0x1e6e0078);
data = ast_mindwm(ast, 0x1e6e0078);
data = (data | (data >> 16)) & 0xffff;
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return data;
}
#if 0 /* Unused in DDX here for completeness */
static int mmc_test_single(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x3000;
data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
if (data & 0x2000)
return 0;
if (++timeout > TIMEOUT) {
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return 0;
}
} while (!data);
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return 1;
}
#endif
static int mmc_test_single2(struct ast_private *ast, u32 datagen)
{
u32 data, timeout;
moutdwm(ast, 0x1e6e0070, 0x00000000);
moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
timeout = 0;
do {
data = mindwm(ast, 0x1e6e0070) & 0x1000;
data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
if (++timeout > TIMEOUT) {
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return -1;
}
} while (!data);
data = mindwm(ast, 0x1e6e0078);
data = ast_mindwm(ast, 0x1e6e0078);
data = (data | (data >> 16)) & 0xffff;
moutdwm(ast, 0x1e6e0070, 0x0);
ast_moutdwm(ast, 0x1e6e0070, 0x0);
return data;
}
......@@ -533,7 +541,7 @@ static int cbr_scan(struct ast_private *ast)
data2 = 3;
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
if ((data = cbr_test(ast)) != 0) {
data2 &= data;
......@@ -568,7 +576,7 @@ static u32 cbr_scan2(struct ast_private *ast)
data2 = 0xffff;
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
for (loop = 0; loop < CBR_PASSNUM2; loop++) {
if ((data = cbr_test2(ast)) != 0) {
data2 &= data;
......@@ -583,106 +591,35 @@ static u32 cbr_scan2(struct ast_private *ast)
return data2;
}
#if 0 /* unused in DDX - added for completeness */
static void finetuneDQI(struct ast_private *ast, struct ast2300_dram_param *param)
static u32 cbr_test3(struct ast_private *ast)
{
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
gold_sadj[0] = (mindwm(ast, 0x1E6E0024) >> 16) & 0xffff;
gold_sadj[1] = gold_sadj[0] >> 8;
gold_sadj[0] = gold_sadj[0] & 0xff;
gold_sadj[0] = (gold_sadj[0] + gold_sadj[1]) >> 1;
gold_sadj[1] = gold_sadj[0];
if (!mmc_test_burst(ast, 0))
return 0;
if (!mmc_test_single(ast, 0))
return 0;
return 1;
}
for (cnt = 0; cnt < 16; cnt++) {
dllmin[cnt] = 0xff;
dllmax[cnt] = 0x0;
}
passcnt = 0;
for (dlli = 0; dlli < 76; dlli++) {
moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
/* Wait DQSI latch phase calibration */
moutdwm(ast, 0x1E6E0074, 0x00000010);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
static u32 cbr_scan3(struct ast_private *ast)
{
u32 patcnt, loop;
moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
data = cbr_scan2(ast);
if (data != 0) {
mask = 0x00010001;
for (cnt = 0; cnt < 16; cnt++) {
if (data & mask) {
if (dllmin[cnt] > dlli) {
dllmin[cnt] = dlli;
}
if (dllmax[cnt] < dlli) {
dllmax[cnt] = dlli;
}
}
mask <<= 1;
}
passcnt++;
} else if (passcnt >= CBR_THRESHOLD) {
for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
for (loop = 0; loop < 2; loop++) {
if (cbr_test3(ast))
break;
}
if (loop == 2)
return 0;
}
data = 0;
for (cnt = 0; cnt < 8; cnt++) {
data >>= 3;
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
if (gold_sadj[0] >= dlli) {
dlli = (gold_sadj[0] - dlli) >> 1;
if (dlli > 3) {
dlli = 3;
}
} else {
dlli = (dlli - gold_sadj[0]) >> 1;
if (dlli > 4) {
dlli = 4;
}
dlli = (8 - dlli) & 0x7;
}
data |= dlli << 21;
}
}
moutdwm(ast, 0x1E6E0080, data);
data = 0;
for (cnt = 8; cnt < 16; cnt++) {
data >>= 3;
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD)) {
dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
if (gold_sadj[1] >= dlli) {
dlli = (gold_sadj[1] - dlli) >> 1;
if (dlli > 3) {
dlli = 3;
} else {
dlli = (dlli - 1) & 0x7;
}
} else {
dlli = (dlli - gold_sadj[1]) >> 1;
dlli += 1;
if (dlli > 4) {
dlli = 4;
}
dlli = (8 - dlli) & 0x7;
}
data |= dlli << 21;
}
}
moutdwm(ast, 0x1E6E0084, data);
} /* finetuneDQI */
#endif
return 1;
}
static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
{
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt;
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
bool status = false;
FINETUNE_START:
for (cnt = 0; cnt < 16; cnt++) {
dllmin[cnt] = 0xff;
......@@ -690,16 +627,8 @@ static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *pa
}
passcnt = 0;
for (dlli = 0; dlli < 76; dlli++) {
moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
/* Wait DQSI latch phase calibration */
moutdwm(ast, 0x1E6E0074, 0x00000010);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
data = cbr_scan2(ast);
if (data != 0) {
mask = 0x00010001;
......@@ -727,9 +656,13 @@ static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *pa
passcnt++;
}
}
if (retry++ > 10)
goto FINETUNE_DONE;
if (passcnt != 16) {
goto FINETUNE_START;
}
status = true;
FINETUNE_DONE:
gold_sadj[0] = gold_sadj[0] >> 4;
gold_sadj[1] = gold_sadj[0];
......@@ -753,7 +686,7 @@ static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *pa
data |= dlli << 21;
}
}
moutdwm(ast, 0x1E6E0080, data);
ast_moutdwm(ast, 0x1E6E0080, data);
data = 0;
for (cnt = 8; cnt < 16; cnt++) {
......@@ -778,162 +711,116 @@ static void finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *pa
data |= dlli << 21;
}
}
moutdwm(ast, 0x1E6E0084, data);
ast_moutdwm(ast, 0x1E6E0084, data);
return status;
} /* finetuneDQI_L */
static void finetuneDQI_L2(struct ast_private *ast, struct ast2300_dram_param *param)
static void finetuneDQSI(struct ast_private *ast)
{
u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, data2;
u32 dlli, dqsip, dqidly;
u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
u32 g_dqidly, g_dqsip, g_margin, g_side;
u16 pass[32][2][2];
char tag[2][76];
/* Disable DQI CBR */
reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
reg_mcr18 &= 0x0000ffff;
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
for (cnt = 0; cnt < 16; cnt++) {
dllmin[cnt] = 0xff;
dllmax[cnt] = 0x0;
}
passcnt = 0;
for (dlli = 0; dlli < 76; dlli++) {
moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
/* Wait DQSI latch phase calibration */
moutdwm(ast, 0x1E6E0074, 0x00000010);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
data = cbr_scan2(ast);
if (data != 0) {
mask = 0x00010001;
for (cnt = 0; cnt < 16; cnt++) {
if (data & mask) {
if (dllmin[cnt] > dlli) {
dllmin[cnt] = dlli;
}
if (dllmax[cnt] < dlli) {
dllmax[cnt] = dlli;
}
}
mask <<= 1;
}
passcnt++;
} else if (passcnt >= CBR_THRESHOLD2) {
tag[0][dlli] = 0x0;
tag[1][dlli] = 0x0;
}
for (dqidly = 0; dqidly < 32; dqidly++) {
pass[dqidly][0][0] = 0xff;
pass[dqidly][0][1] = 0x0;
pass[dqidly][1][0] = 0xff;
pass[dqidly][1][1] = 0x0;
}
for (dqidly = 0; dqidly < 32; dqidly++) {
passcnt[0] = passcnt[1] = 0;
for (dqsip = 0; dqsip < 2; dqsip++) {
ast_moutdwm(ast, 0x1E6E000C, 0);
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
for (dlli = 0; dlli < 76; dlli++) {
ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
ast_moutdwm(ast, 0x1E6E0070, 0);
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
if (cbr_scan3(ast)) {
if (dlli == 0)
break;
}
}
gold_sadj[0] = 0x0;
gold_sadj[1] = 0xFF;
for (cnt = 0; cnt < 8; cnt++) {
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
if (gold_sadj[0] < dllmin[cnt]) {
gold_sadj[0] = dllmin[cnt];
}
if (gold_sadj[1] > dllmax[cnt]) {
gold_sadj[1] = dllmax[cnt];
}
}
}
gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
gold_sadj[1] = mindwm(ast, 0x1E6E0080);
data = 0;
for (cnt = 0; cnt < 8; cnt++) {
data >>= 3;
data2 = gold_sadj[1] & 0x7;
gold_sadj[1] >>= 3;
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
if (gold_sadj[0] >= dlli) {
dlli = (gold_sadj[0] - dlli) >> 1;
if (dlli > 0) {
dlli = 1;
}
if (data2 != 3) {
data2 = (data2 + dlli) & 0x7;
}
} else {
dlli = (dlli - gold_sadj[0]) >> 1;
if (dlli > 0) {
dlli = 1;
}
if (data2 != 4) {
data2 = (data2 - dlli) & 0x7;
}
}
}
data |= data2 << 21;
}
moutdwm(ast, 0x1E6E0080, data);
gold_sadj[0] = 0x0;
gold_sadj[1] = 0xFF;
for (cnt = 8; cnt < 16; cnt++) {
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
if (gold_sadj[0] < dllmin[cnt]) {
gold_sadj[0] = dllmin[cnt];
}
if (gold_sadj[1] > dllmax[cnt]) {
gold_sadj[1] = dllmax[cnt];
}
}
}
gold_sadj[0] = (gold_sadj[1] + gold_sadj[0]) >> 1;
gold_sadj[1] = mindwm(ast, 0x1E6E0084);
data = 0;
for (cnt = 8; cnt < 16; cnt++) {
data >>= 3;
data2 = gold_sadj[1] & 0x7;
gold_sadj[1] >>= 3;
if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
dlli = (dllmin[cnt] + dllmax[cnt]) >> 1;
if (gold_sadj[0] >= dlli) {
dlli = (gold_sadj[0] - dlli) >> 1;
if (dlli > 0) {
dlli = 1;
}
if (data2 != 3) {
data2 = (data2 + dlli) & 0x7;
}
} else {
dlli = (dlli - gold_sadj[0]) >> 1;
if (dlli > 0) {
dlli = 1;
}
if (data2 != 4) {
data2 = (data2 - dlli) & 0x7;
}
}
}
data |= data2 << 21;
}
moutdwm(ast, 0x1E6E0084, data);
} /* finetuneDQI_L2 */
passcnt[dqsip]++;
tag[dqsip][dlli] = 'P';
if (dlli < pass[dqidly][dqsip][0])
pass[dqidly][dqsip][0] = (u16) dlli;
if (dlli > pass[dqidly][dqsip][1])
pass[dqidly][dqsip][1] = (u16) dlli;
} else if (passcnt[dqsip] >= 5)
break;
else {
pass[dqidly][dqsip][0] = 0xff;
pass[dqidly][dqsip][1] = 0x0;
}
}
}
if (passcnt[0] == 0 && passcnt[1] == 0)
dqidly++;
}
/* Search margin */
g_dqidly = g_dqsip = g_margin = g_side = 0;
for (dqidly = 0; dqidly < 32; dqidly++) {
for (dqsip = 0; dqsip < 2; dqsip++) {
if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
continue;
diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
if ((diff+2) < g_margin)
continue;
passcnt[0] = passcnt[1] = 0;
for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
if (passcnt[0] > passcnt[1])
passcnt[0] = passcnt[1];
passcnt[1] = 0;
if (passcnt[0] > g_side)
passcnt[1] = passcnt[0] - g_side;
if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
g_margin = diff;
g_dqidly = dqidly;
g_dqsip = dqsip;
g_side = passcnt[0];
} else if (passcnt[1] > 1 && g_side < 8) {
if (diff > g_margin)
g_margin = diff;
g_dqidly = dqidly;
g_dqsip = dqsip;
g_side = passcnt[0];
}
}
}
reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
}
static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
{
u32 dllmin[2], dllmax[2], dlli, data, data2, passcnt;
u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
bool status = false;
finetuneDQI_L(ast, param);
finetuneDQI_L2(ast, param);
finetuneDQSI(ast);
if (finetuneDQI_L(ast, param) == false)
return status;
CBR_START2:
dllmin[0] = dllmin[1] = 0xff;
dllmax[0] = dllmax[1] = 0x0;
passcnt = 0;
for (dlli = 0; dlli < 76; dlli++) {
moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
/* Wait DQSI latch phase calibration */
moutdwm(ast, 0x1E6E0074, 0x00000010);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
data = cbr_scan(ast);
if (data != 0) {
if (data & 0x1) {
......@@ -957,44 +844,31 @@ static void cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
break;
}
}
if (retry++ > 10)
goto CBR_DONE2;
if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
goto CBR_START2;
}
if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
goto CBR_START2;
}
status = true;
CBR_DONE2:
dlli = (dllmin[1] + dllmax[1]) >> 1;
dlli <<= 8;
dlli += (dllmin[0] + dllmax[0]) >> 1;
moutdwm(ast, 0x1E6E0068, (mindwm(ast, 0x1E6E0068) & 0xFFFF) | (dlli << 16));
data = (mindwm(ast, 0x1E6E0080) >> 24) & 0x1F;
data2 = (mindwm(ast, 0x1E6E0018) & 0xff80ffff) | (data << 16);
moutdwm(ast, 0x1E6E0018, data2);
moutdwm(ast, 0x1E6E0024, 0x8001 | (data << 1) | (param->dll2_finetune_step << 8));
/* Wait DQSI latch phase calibration */
moutdwm(ast, 0x1E6E0074, 0x00000010);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0070, 0x00000003);
do {
data = mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
return status;
} /* CBRDLL2 */
static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
{
u32 trap, trap_AC2, trap_MRS;
moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
/* Ger trap info */
trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
trap_AC2 = 0x00020000 + (trap << 16);
trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
trap_MRS = 0x00000010 + (trap << 4);
......@@ -1008,22 +882,35 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
switch (param->dram_freq) {
case 336:
moutdwm(ast, 0x1E6E2020, 0x0190);
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
param->wodt = 0;
param->reg_AC1 = 0x22202725;
param->reg_AC2 = 0xAA007613 | trap_AC2;
param->reg_DQSIC = 0x000000BA;
param->reg_MRS = 0x04001400 | trap_MRS;
param->reg_EMRS = 0x00000000;
param->reg_IOZ = 0x00000034;
param->reg_IOZ = 0x00000023;
param->reg_DQIDLY = 0x00000074;
param->reg_FREQ = 0x00004DC0;
param->madj_max = 96;
param->dll2_finetune_step = 3;
switch (param->dram_chipid) {
default:
case AST_DRAM_512Mx16:
case AST_DRAM_1Gx16:
param->reg_AC2 = 0xAA007613 | trap_AC2;
break;
case AST_DRAM_2Gx16:
param->reg_AC2 = 0xAA00761C | trap_AC2;
break;
case AST_DRAM_4Gx16:
param->reg_AC2 = 0xAA007636 | trap_AC2;
break;
}
break;
default:
case 396:
moutdwm(ast, 0x1E6E2020, 0x03F1);
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
param->wodt = 1;
param->reg_AC1 = 0x33302825;
param->reg_AC2 = 0xCC009617 | trap_AC2;
......@@ -1033,7 +920,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->reg_IOZ = 0x00000034;
param->reg_DRV = 0x000000FA;
param->reg_DQIDLY = 0x00000089;
param->reg_FREQ = 0x000050C0;
param->reg_FREQ = 0x00005040;
param->madj_max = 96;
param->dll2_finetune_step = 4;
......@@ -1053,14 +940,14 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
break;
case 408:
moutdwm(ast, 0x1E6E2020, 0x01F0);
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
param->wodt = 1;
param->reg_AC1 = 0x33302825;
param->reg_AC2 = 0xCC009617 | trap_AC2;
param->reg_DQSIC = 0x000000E2;
param->reg_MRS = 0x04001600 | trap_MRS;
param->reg_EMRS = 0x00000000;
param->reg_IOZ = 0x00000034;
param->reg_IOZ = 0x00000023;
param->reg_DRV = 0x000000FA;
param->reg_DQIDLY = 0x00000089;
param->reg_FREQ = 0x000050C0;
......@@ -1083,7 +970,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
break;
case 456:
moutdwm(ast, 0x1E6E2020, 0x0230);
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
param->wodt = 0;
param->reg_AC1 = 0x33302926;
param->reg_AC2 = 0xCD44961A;
......@@ -1097,7 +984,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 4;
break;
case 504:
moutdwm(ast, 0x1E6E2020, 0x0270);
ast_moutdwm(ast, 0x1E6E2020, 0x0270);
param->wodt = 1;
param->reg_AC1 = 0x33302926;
param->reg_AC2 = 0xDE44A61D;
......@@ -1111,7 +998,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 4;
break;
case 528:
moutdwm(ast, 0x1E6E2020, 0x0290);
ast_moutdwm(ast, 0x1E6E2020, 0x0290);
param->wodt = 1;
param->rodt = 1;
param->reg_AC1 = 0x33302926;
......@@ -1127,7 +1014,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 576:
moutdwm(ast, 0x1E6E2020, 0x0140);
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
param->reg_MADJ = 0x00136868;
param->reg_SADJ = 0x00004534;
param->wodt = 1;
......@@ -1145,7 +1032,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 600:
moutdwm(ast, 0x1E6E2020, 0x02E1);
ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
param->reg_MADJ = 0x00136868;
param->reg_SADJ = 0x00004534;
param->wodt = 1;
......@@ -1163,7 +1050,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 624:
moutdwm(ast, 0x1E6E2020, 0x0160);
ast_moutdwm(ast, 0x1E6E2020, 0x0160);
param->reg_MADJ = 0x00136868;
param->reg_SADJ = 0x00004534;
param->wodt = 1;
......@@ -1218,106 +1105,98 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
{
u32 data, data2;
u32 data, data2, retry = 0;
moutdwm(ast, 0x1E6E0000, 0xFC600309);
moutdwm(ast, 0x1E6E0018, 0x00000100);
moutdwm(ast, 0x1E6E0024, 0x00000000);
moutdwm(ast, 0x1E6E0034, 0x00000000);
ddr3_init_start:
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
udelay(10);
moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
udelay(10);
moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
udelay(10);
moutdwm(ast, 0x1E6E0004, param->dram_config);
moutdwm(ast, 0x1E6E0008, 0x90040f);
moutdwm(ast, 0x1E6E0010, param->reg_AC1);
moutdwm(ast, 0x1E6E0014, param->reg_AC2);
moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
moutdwm(ast, 0x1E6E0080, 0x00000000);
moutdwm(ast, 0x1E6E0084, 0x00000000);
moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
moutdwm(ast, 0x1E6E0018, 0x4040A170);
moutdwm(ast, 0x1E6E0018, 0x20402370);
moutdwm(ast, 0x1E6E0038, 0x00000000);
moutdwm(ast, 0x1E6E0040, 0xFF444444);
moutdwm(ast, 0x1E6E0044, 0x22222222);
moutdwm(ast, 0x1E6E0048, 0x22222222);
moutdwm(ast, 0x1E6E004C, 0x00000002);
moutdwm(ast, 0x1E6E0050, 0x80000000);
moutdwm(ast, 0x1E6E0050, 0x00000000);
moutdwm(ast, 0x1E6E0054, 0);
moutdwm(ast, 0x1E6E0060, param->reg_DRV);
moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0074, 0x00000000);
moutdwm(ast, 0x1E6E0078, 0x00000000);
moutdwm(ast, 0x1E6E007C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast_moutdwm(ast, 0x1E6E0054, 0);
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
/* Wait MCLK2X lock to MCLK */
do {
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
} while (!(data & 0x08000000));
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00005C04);
udelay(10);
moutdwm(ast, 0x1E6E000C, 0x00000000);
moutdwm(ast, 0x1E6E0034, 0x00000000);
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
data = (data >> 8) & 0xff;
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
if ((data2 & 0xff) > param->madj_max) {
break;
}
moutdwm(ast, 0x1E6E0064, data2);
ast_moutdwm(ast, 0x1E6E0064, data2);
if (data2 & 0x00100000) {
data2 = ((data2 & 0xff) >> 3) + 3;
} else {
data2 = ((data2 & 0xff) >> 2) + 5;
}
data = mindwm(ast, 0x1E6E0068) & 0xffff00ff;
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
data2 += data & 0xff;
data = data | (data2 << 8);
moutdwm(ast, 0x1E6E0068, data);
ast_moutdwm(ast, 0x1E6E0068, data);
udelay(10);
moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000);
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
udelay(10);
data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
moutdwm(ast, 0x1E6E0018, data);
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
ast_moutdwm(ast, 0x1E6E0018, data);
data = data | 0x200;
moutdwm(ast, 0x1E6E0018, data);
ast_moutdwm(ast, 0x1E6E0018, data);
do {
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
} while (!(data & 0x08000000));
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00005C04);
udelay(10);
moutdwm(ast, 0x1E6E000C, 0x00000000);
moutdwm(ast, 0x1E6E0034, 0x00000000);
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
data = (data >> 8) & 0xff;
}
data = mindwm(ast, 0x1E6E0018) | 0xC00;
moutdwm(ast, 0x1E6E0018, data);
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
ast_moutdwm(ast, 0x1E6E0018, data);
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00000040);
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
udelay(50);
/* Mode Register Setting */
moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
moutdwm(ast, 0x1E6E0028, 0x00000005);
moutdwm(ast, 0x1E6E0028, 0x00000007);
moutdwm(ast, 0x1E6E0028, 0x00000003);
moutdwm(ast, 0x1E6E0028, 0x00000001);
moutdwm(ast, 0x1E6E002C, param->reg_MRS);
moutdwm(ast, 0x1E6E000C, 0x00005C08);
moutdwm(ast, 0x1E6E0028, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
data = 0;
if (param->wodt) {
data = 0x300;
......@@ -1325,30 +1204,23 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
if (param->rodt) {
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
}
moutdwm(ast, 0x1E6E0034, data | 0x3);
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
/* Wait DQI delay lock */
do {
data = mindwm(ast, 0x1E6E0080);
} while (!(data & 0x40000000));
/* Wait DQSI delay lock */
do {
data = mindwm(ast, 0x1E6E0020);
} while (!(data & 0x00000800));
/* Calibrate the DQSI delay */
cbr_dll2(ast, param);
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
goto ddr3_init_start;
moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
/* ECC Memory Initialization */
#ifdef ECC
moutdwm(ast, 0x1E6E007C, 0x00000000);
moutdwm(ast, 0x1E6E0070, 0x221);
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0070, 0x221);
do {
data = mindwm(ast, 0x1E6E0070);
data = ast_mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0050, 0x80000000);
moutdwm(ast, 0x1E6E0050, 0x00000000);
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
#endif
......@@ -1358,10 +1230,10 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
{
u32 trap, trap_AC2, trap_MRS;
moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
/* Ger trap info */
trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
trap_AC2 = (trap << 20) | (trap << 16);
trap_AC2 += 0x00110000;
trap_MRS = 0x00000040 | (trap << 4);
......@@ -1375,7 +1247,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
switch (param->dram_freq) {
case 264:
moutdwm(ast, 0x1E6E2020, 0x0130);
ast_moutdwm(ast, 0x1E6E2020, 0x0130);
param->wodt = 0;
param->reg_AC1 = 0x11101513;
param->reg_AC2 = 0x78117011;
......@@ -1390,7 +1262,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 336:
moutdwm(ast, 0x1E6E2020, 0x0190);
ast_moutdwm(ast, 0x1E6E2020, 0x0190);
param->wodt = 1;
param->reg_AC1 = 0x22202613;
param->reg_AC2 = 0xAA009016 | trap_AC2;
......@@ -1403,10 +1275,25 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->reg_FREQ = 0x00004DC0;
param->madj_max = 96;
param->dll2_finetune_step = 3;
switch (param->dram_chipid) {
default:
case AST_DRAM_512Mx16:
param->reg_AC2 = 0xAA009012 | trap_AC2;
break;
case AST_DRAM_1Gx16:
param->reg_AC2 = 0xAA009016 | trap_AC2;
break;
case AST_DRAM_2Gx16:
param->reg_AC2 = 0xAA009023 | trap_AC2;
break;
case AST_DRAM_4Gx16:
param->reg_AC2 = 0xAA00903B | trap_AC2;
break;
}
break;
default:
case 396:
moutdwm(ast, 0x1E6E2020, 0x03F1);
ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
param->wodt = 1;
param->rodt = 0;
param->reg_AC1 = 0x33302714;
......@@ -1417,7 +1304,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->reg_DRV = 0x000000FA;
param->reg_IOZ = 0x00000034;
param->reg_DQIDLY = 0x00000089;
param->reg_FREQ = 0x000050C0;
param->reg_FREQ = 0x00005040;
param->madj_max = 96;
param->dll2_finetune_step = 4;
......@@ -1440,7 +1327,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
break;
case 408:
moutdwm(ast, 0x1E6E2020, 0x01F0);
ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
param->wodt = 1;
param->rodt = 0;
param->reg_AC1 = 0x33302714;
......@@ -1473,7 +1360,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
break;
case 456:
moutdwm(ast, 0x1E6E2020, 0x0230);
ast_moutdwm(ast, 0x1E6E2020, 0x0230);
param->wodt = 0;
param->reg_AC1 = 0x33302815;
param->reg_AC2 = 0xCD44B01E;
......@@ -1488,7 +1375,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 504:
moutdwm(ast, 0x1E6E2020, 0x0261);
ast_moutdwm(ast, 0x1E6E2020, 0x0261);
param->wodt = 1;
param->rodt = 1;
param->reg_AC1 = 0x33302815;
......@@ -1504,7 +1391,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 528:
moutdwm(ast, 0x1E6E2020, 0x0120);
ast_moutdwm(ast, 0x1E6E2020, 0x0120);
param->wodt = 1;
param->rodt = 1;
param->reg_AC1 = 0x33302815;
......@@ -1520,7 +1407,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 552:
moutdwm(ast, 0x1E6E2020, 0x02A1);
ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
param->wodt = 1;
param->rodt = 1;
param->reg_AC1 = 0x43402915;
......@@ -1536,7 +1423,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
param->dll2_finetune_step = 3;
break;
case 576:
moutdwm(ast, 0x1E6E2020, 0x0140);
ast_moutdwm(ast, 0x1E6E2020, 0x0140);
param->wodt = 1;
param->rodt = 1;
param->reg_AC1 = 0x43402915;
......@@ -1588,110 +1475,102 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
{
u32 data, data2;
moutdwm(ast, 0x1E6E0000, 0xFC600309);
moutdwm(ast, 0x1E6E0018, 0x00000100);
moutdwm(ast, 0x1E6E0024, 0x00000000);
moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
u32 data, data2, retry = 0;
ddr2_init_start:
ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
udelay(10);
moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
udelay(10);
moutdwm(ast, 0x1E6E0004, param->dram_config);
moutdwm(ast, 0x1E6E0008, 0x90040f);
moutdwm(ast, 0x1E6E0010, param->reg_AC1);
moutdwm(ast, 0x1E6E0014, param->reg_AC2);
moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
moutdwm(ast, 0x1E6E0080, 0x00000000);
moutdwm(ast, 0x1E6E0084, 0x00000000);
moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
moutdwm(ast, 0x1E6E0018, 0x4040A130);
moutdwm(ast, 0x1E6E0018, 0x20402330);
moutdwm(ast, 0x1E6E0038, 0x00000000);
moutdwm(ast, 0x1E6E0040, 0xFF808000);
moutdwm(ast, 0x1E6E0044, 0x88848466);
moutdwm(ast, 0x1E6E0048, 0x44440008);
moutdwm(ast, 0x1E6E004C, 0x00000000);
moutdwm(ast, 0x1E6E0050, 0x80000000);
moutdwm(ast, 0x1E6E0050, 0x00000000);
moutdwm(ast, 0x1E6E0054, 0);
moutdwm(ast, 0x1E6E0060, param->reg_DRV);
moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0074, 0x00000000);
moutdwm(ast, 0x1E6E0078, 0x00000000);
moutdwm(ast, 0x1E6E007C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
ast_moutdwm(ast, 0x1E6E0054, 0);
ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
/* Wait MCLK2X lock to MCLK */
do {
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
} while (!(data & 0x08000000));
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00005C04);
udelay(10);
moutdwm(ast, 0x1E6E000C, 0x00000000);
moutdwm(ast, 0x1E6E0034, 0x00000000);
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
data = (data >> 8) & 0xff;
while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
if ((data2 & 0xff) > param->madj_max) {
break;
}
moutdwm(ast, 0x1E6E0064, data2);
ast_moutdwm(ast, 0x1E6E0064, data2);
if (data2 & 0x00100000) {
data2 = ((data2 & 0xff) >> 3) + 3;
} else {
data2 = ((data2 & 0xff) >> 2) + 5;
}
data = mindwm(ast, 0x1E6E0068) & 0xffff00ff;
data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
data2 += data & 0xff;
data = data | (data2 << 8);
moutdwm(ast, 0x1E6E0068, data);
ast_moutdwm(ast, 0x1E6E0068, data);
udelay(10);
moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000);
ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
udelay(10);
data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
moutdwm(ast, 0x1E6E0018, data);
data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
ast_moutdwm(ast, 0x1E6E0018, data);
data = data | 0x200;
moutdwm(ast, 0x1E6E0018, data);
ast_moutdwm(ast, 0x1E6E0018, data);
do {
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
} while (!(data & 0x08000000));
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00005C04);
udelay(10);
moutdwm(ast, 0x1E6E000C, 0x00000000);
moutdwm(ast, 0x1E6E0034, 0x00000000);
data = mindwm(ast, 0x1E6E001C);
data = ast_mindwm(ast, 0x1E6E001C);
data = (data >> 8) & 0xff;
}
data = mindwm(ast, 0x1E6E0018) | 0xC00;
moutdwm(ast, 0x1E6E0018, data);
ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
ast_moutdwm(ast, 0x1E6E0018, data);
moutdwm(ast, 0x1E6E0034, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
udelay(50);
/* Mode Register Setting */
moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
moutdwm(ast, 0x1E6E0028, 0x00000005);
moutdwm(ast, 0x1E6E0028, 0x00000007);
moutdwm(ast, 0x1E6E0028, 0x00000003);
moutdwm(ast, 0x1E6E0028, 0x00000001);
moutdwm(ast, 0x1E6E000C, 0x00005C08);
moutdwm(ast, 0x1E6E002C, param->reg_MRS);
moutdwm(ast, 0x1E6E0028, 0x00000001);
moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
moutdwm(ast, 0x1E6E0028, 0x00000003);
moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
moutdwm(ast, 0x1E6E0028, 0x00000003);
moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
data = 0;
if (param->wodt) {
data = 0x500;
......@@ -1699,30 +1578,23 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
if (param->rodt) {
data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
}
moutdwm(ast, 0x1E6E0034, data | 0x3);
moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
/* Wait DQI delay lock */
do {
data = mindwm(ast, 0x1E6E0080);
} while (!(data & 0x40000000));
/* Wait DQSI delay lock */
do {
data = mindwm(ast, 0x1E6E0020);
} while (!(data & 0x00000800));
/* Calibrate the DQSI delay */
cbr_dll2(ast, param);
if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
goto ddr2_init_start;
/* ECC Memory Initialization */
#ifdef ECC
moutdwm(ast, 0x1E6E007C, 0x00000000);
moutdwm(ast, 0x1E6E0070, 0x221);
ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
ast_moutdwm(ast, 0x1E6E0070, 0x221);
do {
data = mindwm(ast, 0x1E6E0070);
data = ast_mindwm(ast, 0x1E6E0070);
} while (!(data & 0x00001000));
moutdwm(ast, 0x1E6E0070, 0x00000000);
moutdwm(ast, 0x1E6E0050, 0x80000000);
moutdwm(ast, 0x1E6E0050, 0x00000000);
ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
#endif
}
......@@ -1768,8 +1640,8 @@ static void ast_init_dram_2300(struct drm_device *dev)
ddr2_init(ast, &param);
}
temp = mindwm(ast, 0x1e6e2040);
moutdwm(ast, 0x1e6e2040, temp | 0x40);
temp = ast_mindwm(ast, 0x1e6e2040);
ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
}
/* wait ready */
......
......@@ -42,7 +42,7 @@
#define HBorder 0x00000020
#define VBorder 0x00000010
#define WideScreenMode 0x00000100
#define NewModeInfo 0x00000200
/* DCLK Index */
#define VCLK25_175 0x00
......@@ -67,6 +67,11 @@
#define VCLK106_5 0x12
#define VCLK146_25 0x13
#define VCLK148_5 0x14
#define VCLK71 0x15
#define VCLK88_75 0x16
#define VCLK119 0x17
#define VCLK85_5 0x18
#define VCLK97_75 0x19
static struct ast_vbios_dclk_info dclk_table[] = {
{0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */
......@@ -90,6 +95,10 @@ static struct ast_vbios_dclk_info dclk_table[] = {
{0x28, 0x49, 0x80}, /* 12: VCLK106.5 */
{0x37, 0x49, 0x80}, /* 13: VCLK146.25 */
{0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */
{0x47, 0x6c, 0x80}, /* 15: VCLK71 */
{0x25, 0x65, 0x80}, /* 16: VCLK88.75 */
{0x77, 0x58, 0x80}, /* 17: VCLK119 */
{0x32, 0x67, 0x80}, /* 18: VCLK85_5 */
};
static struct ast_vbios_stdtable vbios_stdtable[] = {
......@@ -225,41 +234,63 @@ static struct ast_vbios_enhtable res_1600x1200[] = {
(SyncPP | Charx8Dot), 0xFF, 1, 0x33 },
};
static struct ast_vbios_enhtable res_1920x1200[] = {
{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
(SyncNP | Charx8Dot), 60, 1, 0x34 },
{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
(SyncNP | Charx8Dot), 0xFF, 1, 0x34 },
/* 16:9 */
static struct ast_vbios_enhtable res_1360x768[] = {
{1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */
(SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 },
{1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */
(SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 },
};
static struct ast_vbios_enhtable res_1600x900[] = {
{1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A },
{1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* end */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x3A }
};
static struct ast_vbios_enhtable res_1920x1080[] = {
{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 },
{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 },
};
/* 16:10 */
static struct ast_vbios_enhtable res_1280x800[] = {
{1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 35 },
{1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x35 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 },
{1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x35 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x35 },
};
static struct ast_vbios_enhtable res_1440x900[] = {
{1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
{1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x36 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 },
{1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x36 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x36 },
};
static struct ast_vbios_enhtable res_1680x1050[] = {
{1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x37 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 },
{2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x37 },
(SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x37 },
};
/* HDTV */
static struct ast_vbios_enhtable res_1920x1080[] = {
{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 60, 1, 0x38 },
{2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode), 0xFF, 1, 0x38 },
static struct ast_vbios_enhtable res_1920x1200[] = {
{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 },
{2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */
(SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 },
};
#endif
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