Commit 268a491a authored by Dinh Nguyen's avatar Dinh Nguyen

arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"

The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 728390fc
...@@ -502,7 +502,7 @@ uart1: serial@ffc02100 { ...@@ -502,7 +502,7 @@ uart1: serial@ffc02100 {
}; };
usb0: usb@ffb00000 { usb0: usb@ffb00000 {
compatible = "snps,dwc2"; compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb00000 0x40000>; reg = <0xffb00000 0x40000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy0>; phys = <&usbphy0>;
...@@ -515,7 +515,7 @@ usb0: usb@ffb00000 { ...@@ -515,7 +515,7 @@ usb0: usb@ffb00000 {
}; };
usb1: usb@ffb40000 { usb1: usb@ffb40000 {
compatible = "snps,dwc2"; compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb40000 0x40000>; reg = <0xffb40000 0x40000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy0>; phys = <&usbphy0>;
......
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