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Commit 27eee235 authored by John W. Linville's avatar John W. Linville
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Merge branch 'master' of git://git.infradead.org/users/rafal/b43-next

parents ec094144 0c201cfb
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Showing with 661 additions and 442 deletions
drivers/net/wireless/b43/phy_ht.c
View file @ 27eee235
...@@ -30,6 +30,17 @@ ...@@ -30,6 +30,17 @@
#include "radio_2059.h" #include "radio_2059.h"
#include "main.h" #include "main.h"
/* Force values to keep compatibility with wl */
enum ht_rssi_type {
HT_RSSI_W1 = 0,
HT_RSSI_W2 = 1,
HT_RSSI_NB = 2,
HT_RSSI_IQ = 3,
HT_RSSI_TSSI_2G = 4,
HT_RSSI_TSSI_5G = 5,
HT_RSSI_TBD = 6,
};
/************************************************** /**************************************************
* Radio 2059. * Radio 2059.
**************************************************/ **************************************************/
...@@ -37,8 +48,9 @@ ...@@ -37,8 +48,9 @@
static void b43_radio_2059_channel_setup(struct b43_wldev *dev, static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
const struct b43_phy_ht_channeltab_e_radio2059 *e) const struct b43_phy_ht_channeltab_e_radio2059 *e)
{ {
u8 i; static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
u16 routing; u16 r;
int core;
b43_radio_write(dev, 0x16, e->radio_syn16); b43_radio_write(dev, 0x16, e->radio_syn16);
b43_radio_write(dev, 0x17, e->radio_syn17); b43_radio_write(dev, 0x17, e->radio_syn17);
...@@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev, ...@@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
b43_radio_write(dev, 0x41, e->radio_syn41); b43_radio_write(dev, 0x41, e->radio_syn41);
b43_radio_write(dev, 0x43, e->radio_syn43); b43_radio_write(dev, 0x43, e->radio_syn43);
b43_radio_write(dev, 0x47, e->radio_syn47); b43_radio_write(dev, 0x47, e->radio_syn47);
b43_radio_write(dev, 0x4a, e->radio_syn4a);
b43_radio_write(dev, 0x58, e->radio_syn58); for (core = 0; core < 3; core++) {
b43_radio_write(dev, 0x5a, e->radio_syn5a); r = routing[core];
b43_radio_write(dev, 0x6a, e->radio_syn6a); b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
b43_radio_write(dev, 0x6d, e->radio_syn6d); b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
b43_radio_write(dev, 0x6e, e->radio_syn6e); b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
b43_radio_write(dev, 0x92, e->radio_syn92); b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
b43_radio_write(dev, 0x98, e->radio_syn98); b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
for (i = 0; i < 2; i++) { b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
routing = i ? R2059_RXRX1 : R2059_TXRX0; b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
} }
udelay(50); udelay(50);
...@@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev, ...@@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
static void b43_radio_2059_init(struct b43_wldev *dev) static void b43_radio_2059_init(struct b43_wldev *dev)
{ {
const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 }; const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
const u16 radio_values[3][2] = { const u16 radio_values[3][2] = {
{ 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
}; };
...@@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev) ...@@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
b43_radio_mask(dev, 0xc0, ~0x0080); b43_radio_mask(dev, 0xc0, ~0x0080);
if (1) { /* FIXME */ if (1) { /* FIXME */
b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1); b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
udelay(10); udelay(10);
b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1); b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2); b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2); b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
udelay(100); udelay(100);
b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2); b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
for (i = 0; i < 10000; i++) { for (i = 0; i < 10000; i++) {
if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) { if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
i = 0; i = 0;
break; break;
} }
...@@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev) ...@@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
if (i) if (i)
b43err(dev->wl, "radio 0x945 timeout\n"); b43err(dev->wl, "radio 0x945 timeout\n");
b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1); b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
b43_radio_set(dev, 0xa, 0x60); b43_radio_set(dev, 0xa, 0x60);
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
...@@ -390,14 +394,14 @@ static void b43_phy_ht_tx_tone(struct b43_wldev *dev) ...@@ -390,14 +394,14 @@ static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
**************************************************/ **************************************************/
static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel, static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
u8 rssi_type) enum ht_rssi_type rssi_type)
{ {
static const u16 ctl_regs[3][2] = { static const u16 ctl_regs[3][2] = {
{ B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, }, { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
{ B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, }, { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
{ B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, }, { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
}; };
static const u16 radio_r[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1, }; static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
int core; int core;
if (core_sel == 0) { if (core_sel == 0) {
...@@ -411,13 +415,13 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel, ...@@ -411,13 +415,13 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
continue; continue;
switch (rssi_type) { switch (rssi_type) {
case 4: case HT_RSSI_TSSI_2G:
b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8); b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10); b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9); b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10); b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
b43_radio_set(dev, R2059_RXRX1 | 0xbf, 0x1); b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
b43_radio_write(dev, radio_r[core] | 0x159, b43_radio_write(dev, radio_r[core] | 0x159,
0x11); 0x11);
break; break;
...@@ -429,8 +433,8 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel, ...@@ -429,8 +433,8 @@ static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
} }
} }
static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
u8 nsamp) s32 *buf, u8 nsamp)
{ {
u16 phy_regs_values[12]; u16 phy_regs_values[12];
static const u16 phy_regs_to_save[] = { static const u16 phy_regs_to_save[] = {
...@@ -504,15 +508,17 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable) ...@@ -504,15 +508,17 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1, static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
B43_PHY_HT_TXPCTL_CMD_C2, B43_PHY_HT_TXPCTL_CMD_C2,
B43_PHY_HT_TXPCTL_CMD_C3 }; B43_PHY_HT_TXPCTL_CMD_C3 };
static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
B43_PHY_HT_TX_PCTL_STATUS_C2,
B43_PHY_HT_TX_PCTL_STATUS_C3 };
int i; int i;
if (!enable) { if (!enable) {
if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) { if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
/* We disable enabled TX pwr ctl, save it's state */ /* We disable enabled TX pwr ctl, save it's state */
/* for (i = 0; i < 3; i++)
* TODO: find the registers. On N-PHY they were 0x1ed phy_ht->tx_pwr_idx[i] =
* and 0x1ee, we need 3 such a registers for HT-PHY b43_phy_read(dev, status_regs[i]);
*/
} }
b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits); b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
} else { } else {
...@@ -536,13 +542,25 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable) ...@@ -536,13 +542,25 @@ static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev) static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
{ {
struct b43_phy_ht *phy_ht = dev->phy.ht; struct b43_phy_ht *phy_ht = dev->phy.ht;
static const u16 base[] = { 0x840, 0x860, 0x880 };
u16 save_regs[3][3];
s32 rssi_buf[6]; s32 rssi_buf[6];
int core;
/* TODO */ for (core = 0; core < 3; core++) {
save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
b43_phy_write(dev, base[core] + 6, 0);
b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
b43_phy_set(dev, base[core] + 0, 0x0400);
b43_phy_set(dev, base[core] + 0, 0x1000);
}
b43_phy_ht_tx_tone(dev); b43_phy_ht_tx_tone(dev);
udelay(20); udelay(20);
b43_phy_ht_poll_rssi(dev, 4, rssi_buf, 1); b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
b43_phy_ht_stop_playback(dev); b43_phy_ht_stop_playback(dev);
b43_phy_ht_reset_cca(dev); b43_phy_ht_reset_cca(dev);
...@@ -550,7 +568,23 @@ static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev) ...@@ -550,7 +568,23 @@ static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff; phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff; phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
/* TODO */ for (core = 0; core < 3; core++) {
b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
}
}
static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
{
static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
int core;
/* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
for (core = 0; core < 3; core++) {
b43_radio_set(dev, 0x8bf, 0x1);
b43_radio_write(dev, routing[core] | 0x0159, 0x0011);
}
} }
static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev) static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
...@@ -946,6 +980,7 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev) ...@@ -946,6 +980,7 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
b43_phy_ht_tx_power_ctl(dev, false); b43_phy_ht_tx_power_ctl(dev, false);
b43_phy_ht_tx_power_ctl_idle_tssi(dev); b43_phy_ht_tx_power_ctl_idle_tssi(dev);
b43_phy_ht_tx_power_ctl_setup(dev); b43_phy_ht_tx_power_ctl_setup(dev);
b43_phy_ht_tssi_setup(dev);
b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl); b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
return 0; return 0;
......
drivers/net/wireless/b43/phy_ht.h
View file @ 27eee235
...@@ -23,6 +23,9 @@ ...@@ -23,6 +23,9 @@
#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ #define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ #define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ #define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
#define B43_PHY_HT_EST_PWR_C1 0x118
#define B43_PHY_HT_EST_PWR_C2 0x119
#define B43_PHY_HT_EST_PWR_C3 0x11A
#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ #define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
...@@ -53,6 +56,8 @@ ...@@ -53,6 +56,8 @@
#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 #define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ #define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 #define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
#define B43_PHY_HT_TXPCTL_CMD_C2 0x222 #define B43_PHY_HT_TXPCTL_CMD_C2 0x222
#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
#define B43_PHY_HT_RSSI_C1 0x219 #define B43_PHY_HT_RSSI_C1 0x219
...@@ -97,6 +102,7 @@ ...@@ -97,6 +102,7 @@
#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
......
drivers/net/wireless/b43/phy_lp.c
View file @ 27eee235
...@@ -281,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev) ...@@ -281,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
} else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
(dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) && (dev->dev->board_type == SSB_BOARD_BU4312) ||
(sprom->boardflags_lo & B43_BFL_FEM))) { (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
......
drivers/net/wireless/b43/phy_n.c
View file @ 27eee235
...@@ -69,14 +69,27 @@ enum b43_nphy_rf_sequence { ...@@ -69,14 +69,27 @@ enum b43_nphy_rf_sequence {
B43_RFSEQ_UPDATE_GAINU, B43_RFSEQ_UPDATE_GAINU,
}; };
enum b43_nphy_rssi_type { enum n_intc_override {
B43_NPHY_RSSI_X = 0, N_INTC_OVERRIDE_OFF = 0,
B43_NPHY_RSSI_Y, N_INTC_OVERRIDE_TRSW = 1,
B43_NPHY_RSSI_Z, N_INTC_OVERRIDE_PA = 2,
B43_NPHY_RSSI_PWRDET, N_INTC_OVERRIDE_EXT_LNA_PU = 3,
B43_NPHY_RSSI_TSSI_I, N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
B43_NPHY_RSSI_TSSI_Q, };
B43_NPHY_RSSI_TBD,
enum n_rssi_type {
N_RSSI_W1 = 0,
N_RSSI_W2,
N_RSSI_NB,
N_RSSI_IQ,
N_RSSI_TSSI_2G,
N_RSSI_TSSI_5G,
N_RSSI_TBD,
};
enum n_rail_type {
N_RAIL_I = 0,
N_RAIL_Q = 1,
}; };
static inline bool b43_nphy_ipa(struct b43_wldev *dev) static inline bool b43_nphy_ipa(struct b43_wldev *dev)
...@@ -94,7 +107,7 @@ static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) ...@@ -94,7 +107,7 @@ static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
} }
/************************************************** /**************************************************
* RF (just without b43_nphy_rf_control_intc_override) * RF (just without b43_nphy_rf_ctl_intc_override)
**************************************************/ **************************************************/
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
...@@ -128,7 +141,7 @@ static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, ...@@ -128,7 +141,7 @@ static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field, static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
u16 value, u8 core, bool off, u16 value, u8 core, bool off,
u8 override) u8 override)
{ {
...@@ -168,7 +181,7 @@ static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field, ...@@ -168,7 +181,7 @@ static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
u16 value, u8 core, bool off) u16 value, u8 core, bool off)
{ {
int i; int i;
...@@ -244,14 +257,14 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, ...@@ -244,14 +257,14 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
enum n_intc_override intc_override,
u16 value, u8 core) u16 value, u8 core)
{ {
u8 i, j; u8 i, j;
u16 reg, tmp, val; u16 reg, tmp, val;
B43_WARN_ON(dev->phy.rev < 3); B43_WARN_ON(dev->phy.rev < 3);
B43_WARN_ON(field > 4);
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
if ((core == 1 && i == 1) || (core == 2 && !i)) if ((core == 1 && i == 1) || (core == 2 && !i))
...@@ -261,12 +274,12 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, ...@@ -261,12 +274,12 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
b43_phy_set(dev, reg, 0x400); b43_phy_set(dev, reg, 0x400);
switch (field) { switch (intc_override) {
case 0: case N_INTC_OVERRIDE_OFF:
b43_phy_write(dev, reg, 0); b43_phy_write(dev, reg, 0);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
break; break;
case 1: case N_INTC_OVERRIDE_TRSW:
if (!i) { if (!i) {
b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
0xFC3F, (value << 6)); 0xFC3F, (value << 6));
...@@ -307,7 +320,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, ...@@ -307,7 +320,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
0xFFFE); 0xFFFE);
} }
break; break;
case 2: case N_INTC_OVERRIDE_PA:
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
tmp = 0x0020; tmp = 0x0020;
val = value << 5; val = value << 5;
...@@ -317,7 +330,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, ...@@ -317,7 +330,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
} }
b43_phy_maskset(dev, reg, ~tmp, val); b43_phy_maskset(dev, reg, ~tmp, val);
break; break;
case 3: case N_INTC_OVERRIDE_EXT_LNA_PU:
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
tmp = 0x0001; tmp = 0x0001;
val = value; val = value;
...@@ -327,7 +340,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, ...@@ -327,7 +340,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
} }
b43_phy_maskset(dev, reg, ~tmp, val); b43_phy_maskset(dev, reg, ~tmp, val);
break; break;
case 4: case N_INTC_OVERRIDE_EXT_LNA_GAIN:
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
tmp = 0x0002; tmp = 0x0002;
val = value << 1; val = value << 1;
...@@ -1011,7 +1024,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev) ...@@ -1011,7 +1024,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
if (sprom->revision < 4) if (sprom->revision < 4)
workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
&& dev->dev->board_type == 0x46D && dev->dev->board_type == SSB_BOARD_CB2_4321
&& dev->dev->board_rev >= 0x41); && dev->dev->board_rev >= 0x41);
else else
workaround = workaround =
...@@ -1207,8 +1220,9 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, ...@@ -1207,8 +1220,9 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
s8 offset, u8 core, u8 rail, s8 offset, u8 core,
enum b43_nphy_rssi_type type) enum n_rail_type rail,
enum n_rssi_type rssi_type)
{ {
u16 tmp; u16 tmp;
bool core1or5 = (core == 1) || (core == 5); bool core1or5 = (core == 1) || (core == 5);
...@@ -1217,63 +1231,74 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, ...@@ -1217,63 +1231,74 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
offset = clamp_val(offset, -32, 31); offset = clamp_val(offset, -32, 31);
tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) switch (rssi_type) {
case N_RSSI_NB:
if (core1or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) if (core1or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) if (core2or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) if (core2or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
break;
if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) case N_RSSI_W1:
if (core1or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) if (core1or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) if (core2or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) if (core2or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
break;
if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) case N_RSSI_W2:
if (core1or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) if (core1or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) if (core2or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) if (core2or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
break;
if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) case N_RSSI_TBD:
if (core1or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) if (core1or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) if (core2or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) if (core2or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
break;
if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) case N_RSSI_IQ:
if (core1or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) if (core1or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) if (core2or5 && rail == N_RAIL_I)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) if (core2or5 && rail == N_RAIL_Q)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
break;
if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I)) case N_RSSI_TSSI_2G:
if (core1or5)
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I)) if (core2or5)
b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
break;
if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q)) case N_RSSI_TSSI_5G:
if (core1or5)
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q)) if (core2or5)
b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
break;
}
} }
static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
enum n_rssi_type rssi_type)
{ {
u8 i; u8 i;
u16 reg, val; u16 reg, val;
...@@ -1296,7 +1321,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1296,7 +1321,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
if (type < 3) { if (rssi_type == N_RSSI_W1 ||
rssi_type == N_RSSI_W2 ||
rssi_type == N_RSSI_NB) {
reg = (i == 0) ? reg = (i == 0) ?
B43_NPHY_AFECTL_C1 : B43_NPHY_AFECTL_C1 :
B43_NPHY_AFECTL_C2; B43_NPHY_AFECTL_C2;
...@@ -1307,9 +1334,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1307,9 +1334,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
B43_NPHY_RFCTL_LUT_TRSW_UP2; B43_NPHY_RFCTL_LUT_TRSW_UP2;
b43_phy_maskset(dev, reg, 0xFFC3, 0); b43_phy_maskset(dev, reg, 0xFFC3, 0);
if (type == 0) if (rssi_type == N_RSSI_W1)
val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
else if (type == 1) else if (rssi_type == N_RSSI_W2)
val = 16; val = 16;
else else
val = 32; val = 32;
...@@ -1320,9 +1347,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1320,9 +1347,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
B43_NPHY_TXF_40CO_B32S1; B43_NPHY_TXF_40CO_B32S1;
b43_phy_set(dev, reg, 0x0020); b43_phy_set(dev, reg, 0x0020);
} else { } else {
if (type == 6) if (rssi_type == N_RSSI_TBD)
val = 0x0100; val = 0x0100;
else if (type == 3) else if (rssi_type == N_RSSI_IQ)
val = 0x0200; val = 0x0200;
else else
val = 0x0300; val = 0x0300;
...@@ -1334,7 +1361,8 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1334,7 +1361,8 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
b43_phy_maskset(dev, reg, 0xFCFF, val); b43_phy_maskset(dev, reg, 0xFCFF, val);
b43_phy_maskset(dev, reg, 0xF3FF, val << 2); b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
if (type != 3 && type != 6) { if (rssi_type != N_RSSI_IQ &&
rssi_type != N_RSSI_TBD) {
enum ieee80211_band band = enum ieee80211_band band =
b43_current_band(dev->wl); b43_current_band(dev->wl);
...@@ -1344,7 +1372,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1344,7 +1372,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
val = 0x11; val = 0x11;
reg = (i == 0) ? 0x2000 : 0x3000; reg = (i == 0) ? 0x2000 : 0x3000;
reg |= B2055_PADDRV; reg |= B2055_PADDRV;
b43_radio_write16(dev, reg, val); b43_radio_write(dev, reg, val);
reg = (i == 0) ? reg = (i == 0) ?
B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER1 :
...@@ -1356,33 +1384,43 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1356,33 +1384,43 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
} }
} }
static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
enum n_rssi_type rssi_type)
{ {
u16 val; u16 val;
bool rssi_w1_w2_nb = false;
if (type < 3) switch (rssi_type) {
case N_RSSI_W1:
case N_RSSI_W2:
case N_RSSI_NB:
val = 0; val = 0;
else if (type == 6) rssi_w1_w2_nb = true;
break;
case N_RSSI_TBD:
val = 1; val = 1;
else if (type == 3) break;
case N_RSSI_IQ:
val = 2; val = 2;
else break;
default:
val = 3; val = 3;
}
val = (val << 12) | (val << 14); val = (val << 12) | (val << 14);
b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
if (type < 3) { if (rssi_w1_w2_nb) {
b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
(type + 1) << 4); (rssi_type + 1) << 4);
b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
(type + 1) << 4); (rssi_type + 1) << 4);
} }
if (code == 0) { if (code == 0) {
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
if (type < 3) { if (rssi_w1_w2_nb) {
b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
~(B43_NPHY_RFCTL_CMD_RXEN | ~(B43_NPHY_RFCTL_CMD_RXEN |
B43_NPHY_RFCTL_CMD_CORESEL)); B43_NPHY_RFCTL_CMD_CORESEL));
...@@ -1398,7 +1436,7 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1398,7 +1436,7 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
} }
} else { } else {
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
if (type < 3) { if (rssi_w1_w2_nb) {
b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
~(B43_NPHY_RFCTL_CMD_RXEN | ~(B43_NPHY_RFCTL_CMD_RXEN |
B43_NPHY_RFCTL_CMD_CORESEL), B43_NPHY_RFCTL_CMD_CORESEL),
...@@ -1418,7 +1456,8 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1418,7 +1456,8 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
enum n_rssi_type type)
{ {
if (dev->phy.rev >= 3) if (dev->phy.rev >= 3)
b43_nphy_rev3_rssi_select(dev, code, type); b43_nphy_rev3_rssi_select(dev, code, type);
...@@ -1427,11 +1466,12 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1427,11 +1466,12 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
enum n_rssi_type rssi_type, u8 *buf)
{ {
int i; int i;
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
if (type == 2) { if (rssi_type == N_RSSI_NB) {
if (i == 0) { if (i == 0) {
b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
0xFC, buf[0]); 0xFC, buf[0]);
...@@ -1455,8 +1495,8 @@ static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) ...@@ -1455,8 +1495,8 @@ static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
u8 nsamp) s32 *buf, u8 nsamp)
{ {
int i; int i;
int out; int out;
...@@ -1487,7 +1527,7 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, ...@@ -1487,7 +1527,7 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
save_regs_phy[8] = 0; save_regs_phy[8] = 0;
} }
b43_nphy_rssi_select(dev, 5, type); b43_nphy_rssi_select(dev, 5, rssi_type);
if (dev->phy.rev < 2) { if (dev->phy.rev < 2) {
save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
...@@ -1574,7 +1614,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1574,7 +1614,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
u16 r; /* routing */ u16 r; /* routing */
u8 rx_core_state; u8 rx_core_state;
u8 core, i, j; int core, i, j, vcm;
class = b43_nphy_classifier(dev, 0, 0); class = b43_nphy_classifier(dev, 0, 0);
b43_nphy_classifier(dev, 7, 4); b43_nphy_classifier(dev, 7, 4);
...@@ -1586,19 +1626,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1586,19 +1626,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
for (i = 0; i < ARRAY_SIZE(regs_to_store); i++) for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
b43_nphy_rf_control_intc_override(dev, 0, 0, 7); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
b43_nphy_rf_control_intc_override(dev, 1, 1, 7); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
b43_nphy_rf_control_override(dev, 0x1, 0, 0, false); b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x2, 1, 0, false); b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
b43_nphy_rf_control_override(dev, 0x80, 1, 0, false); b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
b43_nphy_rf_control_override(dev, 0x40, 1, 0, false); b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
b43_nphy_rf_control_override(dev, 0x20, 0, 0, false); b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x10, 1, 0, false); b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
} else { } else {
b43_nphy_rf_control_override(dev, 0x10, 0, 0, false); b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
b43_nphy_rf_control_override(dev, 0x20, 1, 0, false); b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
} }
rx_core_state = b43_nphy_get_rx_core_state(dev); rx_core_state = b43_nphy_get_rx_core_state(dev);
...@@ -1606,35 +1646,44 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1606,35 +1646,44 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
if (!(rx_core_state & (1 << core))) if (!(rx_core_state & (1 << core)))
continue; continue;
r = core ? B2056_RX1 : B2056_RX0; r = core ? B2056_RX1 : B2056_RX0;
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2); b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2); N_RSSI_NB);
for (i = 0; i < 8; i++) { b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
N_RSSI_NB);
/* Grab RSSI results for every possible VCM */
for (vcm = 0; vcm < 8; vcm++) {
b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
i << 2); vcm << 2);
b43_nphy_poll_rssi(dev, 2, results[i], 8); b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
} }
/* Find out which VCM got the best results */
for (i = 0; i < 4; i += 2) { for (i = 0; i < 4; i += 2) {
s32 curr; s32 currd;
s32 mind = 0x100000; s32 mind = 0x100000;
s32 minpoll = 249; s32 minpoll = 249;
u8 minvcm = 0; u8 minvcm = 0;
if (2 * core != i) if (2 * core != i)
continue; continue;
for (j = 0; j < 8; j++) { for (vcm = 0; vcm < 8; vcm++) {
curr = results[j][i] * results[j][i] + currd = results[vcm][i] * results[vcm][i] +
results[j][i + 1] * results[j][i]; results[vcm][i + 1] * results[vcm][i];
if (curr < mind) { if (currd < mind) {
mind = curr; mind = currd;
minvcm = j; minvcm = vcm;
} }
if (results[j][i] < minpoll) if (results[vcm][i] < minpoll)
minpoll = results[j][i]; minpoll = results[vcm][i];
} }
vcm_final = minvcm; vcm_final = minvcm;
results_min[i] = minpoll; results_min[i] = minpoll;
} }
/* Select the best VCM */
b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
vcm_final << 2); vcm_final << 2);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
if (core != i / 2) if (core != i / 2)
continue; continue;
...@@ -1647,16 +1696,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1647,16 +1696,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
offset[i] = -32; offset[i] = -32;
b43_nphy_scale_offset_rssi(dev, 0, offset[i], b43_nphy_scale_offset_rssi(dev, 0, offset[i],
(i / 2 == 0) ? 1 : 2, (i / 2 == 0) ? 1 : 2,
(i % 2 == 0) ? 0 : 1, (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
2); N_RSSI_NB);
} }
} }
for (core = 0; core < 2; core++) { for (core = 0; core < 2; core++) {
if (!(rx_core_state & (1 << core))) if (!(rx_core_state & (1 << core)))
continue; continue;
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i); b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i); N_RAIL_I, i);
b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
N_RAIL_Q, i);
b43_nphy_poll_rssi(dev, i, poll_results, 8); b43_nphy_poll_rssi(dev, i, poll_results, 8);
for (j = 0; j < 4; j++) { for (j = 0; j < 4; j++) {
if (j / 2 == core) { if (j / 2 == core) {
...@@ -1696,8 +1748,13 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1696,8 +1748,13 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
} }
rssical_radio_regs[0] = b43_radio_read(dev, 0x602B); if (dev->phy.rev >= 7) {
rssical_radio_regs[0] = b43_radio_read(dev, 0x702B); } else {
rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
B2056_RX_RSSI_MISC);
rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
B2056_RX_RSSI_MISC);
}
rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
...@@ -1723,9 +1780,9 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) ...@@ -1723,9 +1780,9 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
{ {
int i, j; int i, j, vcm;
u8 state[4]; u8 state[4];
u8 code, val; u8 code, val;
u16 class, override; u16 class, override;
...@@ -1743,10 +1800,10 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) ...@@ -1743,10 +1800,10 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
s32 results[4][4] = { }; s32 results[4][4] = { };
s32 miniq[4][2] = { }; s32 miniq[4][2] = { };
if (type == 2) { if (type == N_RSSI_NB) {
code = 0; code = 0;
val = 6; val = 6;
} else if (type < 2) { } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
code = 25; code = 25;
val = 4; val = 4;
} else { } else {
...@@ -1765,63 +1822,63 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) ...@@ -1765,63 +1822,63 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
override = 0x110; override = 0x110;
regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
b43_radio_write16(dev, B2055_C1_PD_RXTX, val); b43_radio_write(dev, B2055_C1_PD_RXTX, val);
regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
b43_radio_write16(dev, B2055_C2_PD_RXTX, val); b43_radio_write(dev, B2055_C2_PD_RXTX, val);
state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
b43_nphy_rssi_select(dev, 5, type); b43_nphy_rssi_select(dev, 5, type);
b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
for (i = 0; i < 4; i++) { for (vcm = 0; vcm < 4; vcm++) {
u8 tmp[4]; u8 tmp[4];
for (j = 0; j < 4; j++) for (j = 0; j < 4; j++)
tmp[j] = i; tmp[j] = vcm;
if (type != 1) if (type != N_RSSI_W2)
b43_nphy_set_rssi_2055_vcm(dev, type, tmp); b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
b43_nphy_poll_rssi(dev, type, results[i], 8); b43_nphy_poll_rssi(dev, type, results[vcm], 8);
if (type < 2) if (type == N_RSSI_W1 || type == N_RSSI_W2)
for (j = 0; j < 2; j++) for (j = 0; j < 2; j++)
miniq[i][j] = min(results[i][2 * j], miniq[vcm][j] = min(results[vcm][2 * j],
results[i][2 * j + 1]); results[vcm][2 * j + 1]);
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
s32 mind = 0x100000; s32 mind = 0x100000;
u8 minvcm = 0; u8 minvcm = 0;
s32 minpoll = 249; s32 minpoll = 249;
s32 curr; s32 currd;
for (j = 0; j < 4; j++) { for (vcm = 0; vcm < 4; vcm++) {
if (type == 2) if (type == N_RSSI_NB)
curr = abs(results[j][i]); currd = abs(results[vcm][i] - code * 8);
else else
curr = abs(miniq[j][i / 2] - code * 8); currd = abs(miniq[vcm][i / 2] - code * 8);
if (curr < mind) { if (currd < mind) {
mind = curr; mind = currd;
minvcm = j; minvcm = vcm;
} }
if (results[j][i] < minpoll) if (results[vcm][i] < minpoll)
minpoll = results[j][i]; minpoll = results[vcm][i];
} }
results_min[i] = minpoll; results_min[i] = minpoll;
vcm_final[i] = minvcm; vcm_final[i] = minvcm;
} }
if (type != 1) if (type != N_RSSI_W2)
b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
...@@ -1836,7 +1893,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) ...@@ -1836,7 +1893,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
offset[i] = code - 32; offset[i] = code - 32;
core = (i / 2) ? 2 : 1; core = (i / 2) ? 2 : 1;
rail = (i % 2) ? 1 : 0; rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
type); type);
...@@ -1847,37 +1904,37 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) ...@@ -1847,37 +1904,37 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
switch (state[2]) { switch (state[2]) {
case 1: case 1:
b43_nphy_rssi_select(dev, 1, 2); b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
break; break;
case 4: case 4:
b43_nphy_rssi_select(dev, 1, 0); b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
break; break;
case 2: case 2:
b43_nphy_rssi_select(dev, 1, 1); b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
break; break;
default: default:
b43_nphy_rssi_select(dev, 1, 1); b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
break; break;
} }
switch (state[3]) { switch (state[3]) {
case 1: case 1:
b43_nphy_rssi_select(dev, 2, 2); b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
break; break;
case 4: case 4:
b43_nphy_rssi_select(dev, 2, 0); b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
break; break;
default: default:
b43_nphy_rssi_select(dev, 2, 1); b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
break; break;
} }
b43_nphy_rssi_select(dev, 0, type); b43_nphy_rssi_select(dev, 0, type);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
b43_nphy_classifier(dev, 7, class); b43_nphy_classifier(dev, 7, class);
b43_nphy_write_clip_detection(dev, clip_state); b43_nphy_write_clip_detection(dev, clip_state);
...@@ -1895,9 +1952,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev) ...@@ -1895,9 +1952,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev)
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
b43_nphy_rev3_rssi_cal(dev); b43_nphy_rev3_rssi_cal(dev);
} else { } else {
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z); b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X); b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y); b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
} }
} }
...@@ -1930,10 +1987,8 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -1930,10 +1987,8 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
/* Set Clip 2 detect */ /* Set Clip 2 detect */
b43_phy_set(dev, B43_NPHY_C1_CGAINI, b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
B43_NPHY_C1_CGAINI_CL2DETECT); b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
b43_phy_set(dev, B43_NPHY_C2_CGAINI,
B43_NPHY_C2_CGAINI_CL2DETECT);
b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
0x17); 0x17);
...@@ -1967,22 +2022,22 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -1967,22 +2022,22 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain); b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
b43_phy_write(dev, 0x2A7, e->init_gain); b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
e->rfseq_init); e->rfseq_init);
/* TODO: check defines. Do not match variables names */ b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain); b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
b43_phy_write(dev, 0x2A9, e->cliphi_gain); b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain); b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
b43_phy_write(dev, 0x2AB, e->clipmd_gain); b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain); b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
b43_phy_write(dev, 0x2AD, e->cliplo_gain);
b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin); b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl); b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
...@@ -2164,8 +2219,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) ...@@ -2164,8 +2219,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
} }
if (phy->rev <= 8) { if (phy->rev <= 8) {
b43_phy_write(dev, 0x23F, 0x1B0); b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
b43_phy_write(dev, 0x240, 0x1B0); b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
} }
if (phy->rev >= 8) if (phy->rev >= 8)
b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
...@@ -2182,8 +2237,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) ...@@ -2182,8 +2237,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000); b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000); b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154); lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
...@@ -2260,11 +2315,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) ...@@ -2260,11 +2315,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
rx2tx_lut_40_11n); rx2tx_lut_40_11n);
} }
b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2); b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
} }
b43_phy_write(dev, 0x32F, 0x3); b43_phy_write(dev, 0x32F, 0x3);
if (phy->radio_rev == 4 || phy->radio_rev == 6) if (phy->radio_rev == 4 || phy->radio_rev == 6)
b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0); b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
if (sprom->revision && if (sprom->revision &&
...@@ -2450,8 +2505,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -2450,8 +2505,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
u16 tmp16; u16 tmp16;
u32 tmp32; u32 tmp32;
b43_phy_write(dev, 0x23f, 0x1f8); b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
b43_phy_write(dev, 0x240, 0x1f8); b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
tmp32 &= 0xffffff; tmp32 &= 0xffffff;
...@@ -2464,8 +2519,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -2464,8 +2519,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
b43_phy_write(dev, 0x2AE, 0x000C); b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
/* TX to RX */ /* TX to RX */
b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
...@@ -2490,7 +2545,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -2490,7 +2545,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
0x2 : 0x9C40; 0x2 : 0x9C40;
b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
if (!dev->phy.is_40mhz) { if (!dev->phy.is_40mhz) {
b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
...@@ -2542,18 +2597,18 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) ...@@ -2542,18 +2597,18 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
} }
/* Dropped probably-always-true condition */ /* Dropped probably-always-true condition */
b43_phy_write(dev, 0x224, 0x03eb); b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
b43_phy_write(dev, 0x225, 0x03eb); b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
b43_phy_write(dev, 0x226, 0x0341); b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
b43_phy_write(dev, 0x227, 0x0341); b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
b43_phy_write(dev, 0x228, 0x042b); b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
b43_phy_write(dev, 0x229, 0x042b); b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
b43_phy_write(dev, 0x22a, 0x0381); b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
b43_phy_write(dev, 0x22b, 0x0381); b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
b43_phy_write(dev, 0x22c, 0x042b); b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
b43_phy_write(dev, 0x22d, 0x042b); b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
b43_phy_write(dev, 0x22e, 0x0381); b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
b43_phy_write(dev, 0x22f, 0x0381); b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
; /* TODO: 0x0080000000000000 HF */ ; /* TODO: 0x0080000000000000 HF */
...@@ -2572,7 +2627,7 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) ...@@ -2572,7 +2627,7 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
dev->dev->board_type == 0x8B) { dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
delays1[0] = 0x1; delays1[0] = 0x1;
delays1[5] = 0x14; delays1[5] = 0x14;
} }
...@@ -3120,21 +3175,21 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) ...@@ -3120,21 +3175,21 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
b43_nphy_ipa_internal_tssi_setup(dev); b43_nphy_ipa_internal_tssi_setup(dev);
if (phy->rev >= 7) if (phy->rev >= 7)
b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0); b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
else if (phy->rev >= 3) else if (phy->rev >= 3)
b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false); b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
b43_nphy_stop_playback(dev); b43_nphy_stop_playback(dev);
b43_nphy_tx_tone(dev, 0xFA0, 0, false, false); b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
udelay(20); udelay(20);
tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1); tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
b43_nphy_stop_playback(dev); b43_nphy_stop_playback(dev);
b43_nphy_rssi_select(dev, 0, 0); b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
if (phy->rev >= 7) if (phy->rev >= 7)
b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0); b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
else if (phy->rev >= 3) else if (phy->rev >= 3)
b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true); b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
if (phy->rev >= 3) { if (phy->rev >= 3) {
nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
...@@ -3573,8 +3628,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) ...@@ -3573,8 +3628,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
} }
b43_nphy_rf_control_intc_override(dev, 2, 0, 3); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
b43_nphy_rf_control_override(dev, 8, 0, 3, false); b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
if (core == 0) { if (core == 0) {
...@@ -3584,8 +3639,10 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) ...@@ -3584,8 +3639,10 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
rxval = 4; rxval = 4;
txval = 2; txval = 2;
} }
b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); core + 1);
b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
2 - core);
} }
#endif #endif
...@@ -3847,9 +3904,13 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) ...@@ -3847,9 +3904,13 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
} }
/* TODO use some definitions */ if (dev->phy.rev >= 7) {
b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); } else {
b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
rssical_radio_regs[0]);
b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
rssical_radio_regs[1]);
}
b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
...@@ -3880,75 +3941,75 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) ...@@ -3880,75 +3941,75 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
tmp = (i == 0) ? 0x2000 : 0x3000; tmp = (i == 0) ? 0x2000 : 0x3000;
offset = i * 11; offset = i * 11;
save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
if (nphy->ipa5g_on) { if (nphy->ipa5g_on) {
b43_radio_write16(dev, tmp | B2055_PADDRV, 4); b43_radio_write(dev, tmp | B2055_PADDRV, 4);
b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
} else { } else {
b43_radio_write16(dev, tmp | B2055_PADDRV, 0); b43_radio_write(dev, tmp | B2055_PADDRV, 0);
b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
} }
b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
} else { } else {
b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
if (nphy->ipa2g_on) { if (nphy->ipa2g_on) {
b43_radio_write16(dev, tmp | B2055_PADDRV, 6); b43_radio_write(dev, tmp | B2055_PADDRV, 6);
b43_radio_write16(dev, tmp | B2055_XOCTL2, b43_radio_write(dev, tmp | B2055_XOCTL2,
(dev->phy.rev < 5) ? 0x11 : 0x01); (dev->phy.rev < 5) ? 0x11 : 0x01);
} else { } else {
b43_radio_write16(dev, tmp | B2055_PADDRV, 0); b43_radio_write(dev, tmp | B2055_PADDRV, 0);
b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
} }
} }
b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
b43_radio_write16(dev, tmp | B2055_XOMISC, 0); b43_radio_write(dev, tmp | B2055_XOMISC, 0);
b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
} }
} else { } else {
save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
B43_NPHY_BANDCTL_5GHZ)) { B43_NPHY_BANDCTL_5GHZ)) {
b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
} else { } else {
b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
} }
if (dev->phy.rev < 2) { if (dev->phy.rev < 2) {
...@@ -4144,9 +4205,9 @@ static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) ...@@ -4144,9 +4205,9 @@ static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
b43_nphy_rf_control_intc_override(dev, 2, 1, 3); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
b43_nphy_rf_control_intc_override(dev, 1, 2, 1); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
b43_nphy_rf_control_intc_override(dev, 1, 8, 2); b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
...@@ -4679,7 +4740,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, ...@@ -4679,7 +4740,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
(cur_lna << 2)); (cur_lna << 2));
b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
false); false);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
b43_nphy_stop_playback(dev); b43_nphy_stop_playback(dev);
...@@ -4728,7 +4789,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, ...@@ -4728,7 +4789,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
break; break;
} }
b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
...@@ -4797,18 +4858,6 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) ...@@ -4797,18 +4858,6 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
* N-PHY init * N-PHY init
**************************************************/ **************************************************/
/*
* Upload the N-PHY tables.
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
*/
static void b43_nphy_tables_init(struct b43_wldev *dev)
{
if (dev->phy.rev < 3)
b43_nphy_rev0_1_2_tables_init(dev);
else
b43_nphy_rev3plus_tables_init(dev);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
{ {
...@@ -4958,7 +5007,7 @@ static int b43_phy_initn(struct b43_wldev *dev) ...@@ -4958,7 +5007,7 @@ static int b43_phy_initn(struct b43_wldev *dev)
if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
(dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
dev->dev->board_type == 0x8B)) dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
else else
b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
......
drivers/net/wireless/b43/phy_n.h
View file @ 27eee235
...@@ -54,10 +54,15 @@ ...@@ -54,10 +54,15 @@
#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 #define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ #define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ #define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ #define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ #define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ #define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ #define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ #define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ #define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ #define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
...@@ -107,10 +112,15 @@ ...@@ -107,10 +112,15 @@
#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 #define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ #define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ #define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ #define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ #define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ #define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ #define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ #define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ #define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ #define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
...@@ -706,10 +716,146 @@ ...@@ -706,10 +716,146 @@
#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ #define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ #define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 #define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
/* REV3+ */
#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
#define B43_NPHY_MLUA B43_PHY_N(0x259)
#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ #define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ #define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ #define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ #define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) #define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
......
drivers/net/wireless/b43/radio_2059.c
View file @ 27eee235
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ #define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
r20, r21, r22, r23, r24, r25, r26, r27, r28) \ r20) \
.radio_syn16 = r00, \ .radio_syn16 = r00, \
.radio_syn17 = r01, \ .radio_syn17 = r01, \
.radio_syn22 = r02, \ .radio_syn22 = r02, \
...@@ -41,22 +41,14 @@ ...@@ -41,22 +41,14 @@
.radio_syn41 = r10, \ .radio_syn41 = r10, \
.radio_syn43 = r11, \ .radio_syn43 = r11, \
.radio_syn47 = r12, \ .radio_syn47 = r12, \
.radio_syn4a = r13, \ .radio_rxtx4a = r13, \
.radio_syn58 = r14, \ .radio_rxtx58 = r14, \
.radio_syn5a = r15, \ .radio_rxtx5a = r15, \
.radio_syn6a = r16, \ .radio_rxtx6a = r16, \
.radio_syn6d = r17, \ .radio_rxtx6d = r17, \
.radio_syn6e = r18, \ .radio_rxtx6e = r18, \
.radio_syn92 = r19, \ .radio_rxtx92 = r19, \
.radio_syn98 = r20, \ .radio_rxtx98 = r20
.radio_rxtx4a = r21, \
.radio_rxtx58 = r22, \
.radio_rxtx5a = r23, \
.radio_rxtx6a = r24, \
.radio_rxtx6d = r25, \
.radio_rxtx6e = r26, \
.radio_rxtx92 = r27, \
.radio_rxtx98 = r28
#define PHYREGS(r0, r1, r2, r3, r4, r5) \ #define PHYREGS(r0, r1, r2, r3, r4, r5) \
.phy_regs.bw1 = r0, \ .phy_regs.bw1 = r0, \
...@@ -70,91 +62,78 @@ static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radi ...@@ -70,91 +62,78 @@ static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radi
{ .freq = 2412, { .freq = 2412,
RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
}, },
{ .freq = 2417, { .freq = 2417,
RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
}, },
{ .freq = 2422, { .freq = 2422,
RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
}, },
{ .freq = 2427, { .freq = 2427,
RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
}, },
{ .freq = 2432, { .freq = 2432,
RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
}, },
{ .freq = 2437, { .freq = 2437,
RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
}, },
{ .freq = 2442, { .freq = 2442,
RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
}, },
{ .freq = 2447, { .freq = 2447,
RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
}, },
{ .freq = 2452, { .freq = 2452,
RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
}, },
{ .freq = 2457, { .freq = 2457,
RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
}, },
{ .freq = 2462, { .freq = 2462,
RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
}, },
{ .freq = 2467, { .freq = 2467,
RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
}, },
{ .freq = 2472, { .freq = 2472,
RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
0x00, 0x00, 0x00, 0xf0, 0x00), 0x00, 0x00, 0x00, 0xf0, 0x00),
PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
}, },
......
drivers/net/wireless/b43/radio_2059.h
View file @ 27eee235
...@@ -5,9 +5,9 @@ ...@@ -5,9 +5,9 @@
#include "phy_ht.h" #include "phy_ht.h"
#define R2059_SYN 0x000 #define R2059_C1 0x000
#define R2059_TXRX0 0x400 #define R2059_C2 0x400
#define R2059_RXRX1 0x800 #define R2059_C3 0x800
#define R2059_ALL 0xC00 #define R2059_ALL 0xC00
/* Values for various registers uploaded on channel switching */ /* Values for various registers uploaded on channel switching */
...@@ -28,14 +28,6 @@ struct b43_phy_ht_channeltab_e_radio2059 { ...@@ -28,14 +28,6 @@ struct b43_phy_ht_channeltab_e_radio2059 {
u8 radio_syn41; u8 radio_syn41;
u8 radio_syn43; u8 radio_syn43;
u8 radio_syn47; u8 radio_syn47;
u8 radio_syn4a;
u8 radio_syn58;
u8 radio_syn5a;
u8 radio_syn6a;
u8 radio_syn6d;
u8 radio_syn6e;
u8 radio_syn92;
u8 radio_syn98;
u8 radio_rxtx4a; u8 radio_rxtx4a;
u8 radio_rxtx58; u8 radio_rxtx58;
u8 radio_rxtx5a; u8 radio_rxtx5a;
......
drivers/net/wireless/b43/tables_nphy.c
View file @ 27eee235
...@@ -2174,7 +2174,7 @@ static const u16 b43_ntab_loftlt1_r3[] = { ...@@ -2174,7 +2174,7 @@ static const u16 b43_ntab_loftlt1_r3[] = {
/* volatile tables, PHY revision >= 3 */ /* volatile tables, PHY revision >= 3 */
/* indexed by antswctl2g */ /* indexed by antswctl2g */
static const u16 b43_ntab_antswctl2g_r3[4][32] = { static const u16 b43_ntab_antswctl_r3[4][32] = {
{ {
0x0082, 0x0082, 0x0211, 0x0222, 0x0328, 0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
0x0000, 0x0000, 0x0000, 0x0144, 0x0000, 0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
...@@ -3095,9 +3095,55 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, ...@@ -3095,9 +3095,55 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
} }
#define ntab_upload(dev, offset, data) do { \ #define ntab_upload(dev, offset, data) do { \
b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \ b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
} while (0) } while (0)
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
static void b43_nphy_tables_init_rev3(struct b43_wldev *dev)
{
struct ssb_sprom *sprom = dev->dev->bus_sprom;
u8 antswlut;
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
antswlut = sprom->fem.ghz5.antswlut;
else
antswlut = sprom->fem.ghz2.antswlut;
/* Static tables */
ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
ntab_upload(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
ntab_upload(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
ntab_upload(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
ntab_upload(dev, B43_NTAB_C0_ESTPLT_R3, b43_ntab_estimatepowerlt0_r3);
ntab_upload(dev, B43_NTAB_C1_ESTPLT_R3, b43_ntab_estimatepowerlt1_r3);
ntab_upload(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
ntab_upload(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
ntab_upload(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
ntab_upload(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
ntab_upload(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
ntab_upload(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
ntab_upload(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
/* Volatile tables */
if (antswlut < ARRAY_SIZE(b43_ntab_antswctl_r3))
ntab_upload(dev, B43_NTAB_ANT_SW_CTL_R3,
b43_ntab_antswctl_r3[antswlut]);
else
B43_WARN_ON(1);
}
static void b43_nphy_tables_init_rev0(struct b43_wldev *dev)
{ {
/* Static tables */ /* Static tables */
ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct); ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
...@@ -3130,48 +3176,13 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev) ...@@ -3130,48 +3176,13 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1); ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
} }
#define ntab_upload_r3(dev, offset, data) do { \ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */
b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ void b43_nphy_tables_init(struct b43_wldev *dev)
} while (0)
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
{ {
struct ssb_sprom *sprom = dev->dev->bus_sprom; if (dev->phy.rev >= 3)
b43_nphy_tables_init_rev3(dev);
/* Static tables */
ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
b43_ntab_estimatepowerlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
b43_ntab_estimatepowerlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
/* Volatile tables */
if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
else else
B43_WARN_ON(1); b43_nphy_tables_init_rev0(dev);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
......
drivers/net/wireless/b43/tables_nphy.h
View file @ 27eee235
...@@ -115,22 +115,22 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent( ...@@ -115,22 +115,22 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
#define B43_NTAB_NOISEVAR11_SIZE 256 #define B43_NTAB_NOISEVAR11_SIZE 256
#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */ #define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
#define B43_NTAB_C0_ESTPLT_SIZE 64 #define B43_NTAB_C0_ESTPLT_SIZE 64
#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
#define B43_NTAB_C1_ESTPLT_SIZE 64
#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */ #define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
#define B43_NTAB_C0_ADJPLT_SIZE 128 #define B43_NTAB_C0_ADJPLT_SIZE 128
#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
#define B43_NTAB_C1_ADJPLT_SIZE 128
#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */ #define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
#define B43_NTAB_C0_GAINCTL_SIZE 128 #define B43_NTAB_C0_GAINCTL_SIZE 128
#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
#define B43_NTAB_C1_GAINCTL_SIZE 128
#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */ #define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
#define B43_NTAB_C0_IQLT_SIZE 128 #define B43_NTAB_C0_IQLT_SIZE 128
#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
#define B43_NTAB_C1_IQLT_SIZE 128
#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */ #define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
#define B43_NTAB_C0_LOFEEDTH_SIZE 128 #define B43_NTAB_C0_LOFEEDTH_SIZE 128
#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
#define B43_NTAB_C1_ESTPLT_SIZE 64
#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
#define B43_NTAB_C1_ADJPLT_SIZE 128
#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
#define B43_NTAB_C1_GAINCTL_SIZE 128
#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
#define B43_NTAB_C1_IQLT_SIZE 128
#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */ #define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
#define B43_NTAB_C1_LOFEEDTH_SIZE 128 #define B43_NTAB_C1_LOFEEDTH_SIZE 128
...@@ -154,15 +154,17 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent( ...@@ -154,15 +154,17 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */ #define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */
#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */ #define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */
#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */ #define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */ #define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */
#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */ #define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */
#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */ #define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */
#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */ #define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
#define B43_NTAB_C0_PAPD_COMP_R3 B43_NTAB16(26, 576)
#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */ #define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
#define B43_NTAB_C1_PAPD_COMP_R3 B43_NTAB16(27, 576)
#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
...@@ -182,8 +184,7 @@ void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value); ...@@ -182,8 +184,7 @@ void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
unsigned int nr_elements, const void *_data); unsigned int nr_elements, const void *_data);
void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev); void b43_nphy_tables_init(struct b43_wldev *dev);
void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev); const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
......
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