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Commit 28fafca7 authored by Olivier Grenie's avatar Olivier Grenie Committed by Mauro Carvalho Chehab
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[media] DiB0090: misc improvements 

This patch adds several performance improvements and prepares the
usage of firmware-based devices.
Signed-off-by: default avatarOlivier Grenie <olivier.grenie@dibcom.fr>
Signed-off-by: default avatarPatrick Boettcher <patrick.boettcher@dibcom.fr>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent b994d192
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Showing with 1346 additions and 335 deletions
drivers/media/dvb/frontends/dib0090.c
View file @ 28fafca7
...@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); ...@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
} \ } \
} while (0) } while (0)
#define CONFIG_SYS_DVBT
#define CONFIG_SYS_ISDBT #define CONFIG_SYS_ISDBT
#define CONFIG_BAND_CBAND #define CONFIG_BAND_CBAND
#define CONFIG_BAND_VHF #define CONFIG_BAND_VHF
...@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); ...@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
#define EN_SBD 0x44E9 #define EN_SBD 0x44E9
#define EN_CAB 0x88E9 #define EN_CAB 0x88E9
/* Calibration defines */
#define DC_CAL 0x1
#define WBD_CAL 0x2
#define TEMP_CAL 0x4
#define CAPTRIM_CAL 0x8
#define KROSUS_PLL_LOCKED 0x800
#define KROSUS 0x2
/* Use those defines to identify SOC version */
#define SOC 0x02
#define SOC_7090_P1G_11R1 0x82
#define SOC_7090_P1G_21R1 0x8a
#define SOC_8090_P1G_11R1 0x86
#define SOC_8090_P1G_21R1 0x8e
/* else use thos ones to check */
#define P1A_B 0x0
#define P1C 0x1
#define P1D_E_F 0x3
#define P1G 0x7
#define P1G_21R2 0xf
#define MP001 0x1 /* Single 9090/8096 */
#define MP005 0x4 /* Single Sband */
#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
#define pgm_read_word(w) (*w) #define pgm_read_word(w) (*w)
struct dc_calibration; struct dc_calibration;
...@@ -84,7 +113,7 @@ struct dib0090_tuning { ...@@ -84,7 +113,7 @@ struct dib0090_tuning {
u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u8 switch_trim; u8 switch_trim;
u8 lna_tune; u8 lna_tune;
u8 lna_bias; u16 lna_bias;
u16 v2i; u16 v2i;
u16 mix; u16 mix;
u16 load; u16 load;
...@@ -99,13 +128,19 @@ struct dib0090_pll { ...@@ -99,13 +128,19 @@ struct dib0090_pll {
u8 topresc; u8 topresc;
}; };
struct dib0090_identity {
u8 version;
u8 product;
u8 p1g;
u8 in_soc;
};
struct dib0090_state { struct dib0090_state {
struct i2c_adapter *i2c; struct i2c_adapter *i2c;
struct dvb_frontend *fe; struct dvb_frontend *fe;
const struct dib0090_config *config; const struct dib0090_config *config;
u8 current_band; u8 current_band;
u16 revision;
enum frontend_tune_state tune_state; enum frontend_tune_state tune_state;
u32 current_rf; u32 current_rf;
...@@ -143,15 +178,34 @@ struct dib0090_state { ...@@ -143,15 +178,34 @@ struct dib0090_state {
u8 tuner_is_tuned; u8 tuner_is_tuned;
u8 agc_freeze; u8 agc_freeze;
u8 reset; struct dib0090_identity identity;
u32 rf_request;
u8 current_standard;
u8 calibrate;
u32 rest;
u16 bias;
s16 temperature;
u8 wbd_calibration_gain;
const struct dib0090_wbd_slope *current_wbd_table;
u16 wbdmux;
};
struct dib0090_fw_state {
struct i2c_adapter *i2c;
struct dvb_frontend *fe;
struct dib0090_identity identity;
const struct dib0090_config *config;
}; };
static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
{ {
u8 b[2]; u8 b[2];
struct i2c_msg msg[2] = { struct i2c_msg msg[2] = {
{.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1}, {.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1},
{.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2}, {.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
}; };
if (i2c_transfer(state->i2c, msg, 2) != 2) { if (i2c_transfer(state->i2c, msg, 2) != 2) {
printk(KERN_WARNING "DiB0090 I2C read failed\n"); printk(KERN_WARNING "DiB0090 I2C read failed\n");
...@@ -163,7 +217,29 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) ...@@ -163,7 +217,29 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
{ {
u8 b[3] = { reg & 0xff, val >> 8, val & 0xff }; u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 }; struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 };
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C write failed\n");
return -EREMOTEIO;
}
return 0;
}
static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
{
u8 b[2];
struct i2c_msg msg = {.addr = reg,.flags = I2C_M_RD,.buf = b,.len = 2 };
if (i2c_transfer(state->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C read failed\n");
return 0;
}
return (b[0] << 8) | b[1];
}
static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
{
u8 b[2] = { val >> 8, val & 0xff };
struct i2c_msg msg = {.addr = reg,.flags = 0,.buf = b,.len = 2 };
if (i2c_transfer(state->i2c, &msg, 1) != 1) { if (i2c_transfer(state->i2c, &msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C write failed\n"); printk(KERN_WARNING "DiB0090 I2C write failed\n");
return -EREMOTEIO; return -EREMOTEIO;
...@@ -183,89 +259,329 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b, ...@@ -183,89 +259,329 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b,
} while (--c); } while (--c);
} }
static u16 dib0090_identify(struct dvb_frontend *fe) static int dib0090_identify(struct dvb_frontend *fe)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
u16 v; u16 v;
struct dib0090_identity *identity = &state->identity;
v = dib0090_read_reg(state, 0x1a); v = dib0090_read_reg(state, 0x1a);
#ifdef FIRMWARE_FIREFLY identity->p1g = 0;
/* pll is not locked locked */ identity->in_soc = 0;
if (!(v & 0x800))
dprintk("FE%d : Identification : pll is not yet locked", fe->id); dprintk("Tuner identification (Version = 0x%04x)", v);
#endif
/* without PLL lock info */ /* without PLL lock info */
v &= 0x3ff; v &= ~KROSUS_PLL_LOCKED;
dprintk("P/V: %04x:", v);
if ((v >> 8) & 0xf) identity->version = v & 0xff;
dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf); identity->product = (v >> 8) & 0xf;
else
return 0xff; if (identity->product != KROSUS)
goto identification_error;
v &= 0xff;
if (((v >> 5) & 0x7) == 0x1) if ((identity->version & 0x3) == SOC) {
dprintk("FE%d : MP001 : 9090/8096", fe->id); identity->in_soc = 1;
else if (((v >> 5) & 0x7) == 0x4) switch (identity->version) {
dprintk("FE%d : MP005 : Single Sband", fe->id); case SOC_8090_P1G_11R1:
else if (((v >> 5) & 0x7) == 0x6) dprintk("SOC 8090 P1-G11R1 Has been detected");
dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id); identity->p1g = 1;
else if (((v >> 5) & 0x7) == 0x7) break;
dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id); case SOC_8090_P1G_21R1:
else dprintk("SOC 8090 P1-G21R1 Has been detected");
return 0xff; identity->p1g = 1;
break;
/* revision only */ case SOC_7090_P1G_11R1:
if ((v & 0x1f) == 0x3) dprintk("SOC 7090 P1-G11R1 Has been detected");
dprintk("FE%d : P1-D/E/F detected", fe->id); identity->p1g = 1;
else if ((v & 0x1f) == 0x1) break;
dprintk("FE%d : P1C detected", fe->id); case SOC_7090_P1G_21R1:
else if ((v & 0x1f) == 0x0) { dprintk("SOC 7090 P1-G21R1 Has been detected");
#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT identity->p1g = 1;
dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id); break;
dib0090_p1b_register(fe); default:
#else goto identification_error;
dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id); }
return 0xff; } else {
#endif switch ((identity->version >> 5) & 0x7) {
case MP001:
dprintk("MP001 : 9090/8096");
break;
case MP005:
dprintk("MP005 : Single Sband");
break;
case MP008:
dprintk("MP008 : diversity VHF-UHF-LBAND");
break;
case MP009:
dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
break;
default:
goto identification_error;
}
switch (identity->version & 0x1f) {
case P1G_21R2:
dprintk("P1G_21R2 detected");
identity->p1g = 1;
break;
case P1G:
dprintk("P1G detected");
identity->p1g = 1;
break;
case P1D_E_F:
dprintk("P1D/E/F detected");
break;
case P1C:
dprintk("P1C detected");
break;
case P1A_B:
dprintk("P1-A/B detected: driver is deactivated - not available");
goto identification_error;
break;
default:
goto identification_error;
}
} }
return v; return 0;
identification_error:
return -EIO;
}
static int dib0090_fw_identify(struct dvb_frontend *fe)
{
struct dib0090_fw_state *state = fe->tuner_priv;
struct dib0090_identity *identity = &state->identity;
u16 v = dib0090_fw_read_reg(state, 0x1a);
identity->p1g = 0;
identity->in_soc = 0;
dprintk("FE: Tuner identification (Version = 0x%04x)", v);
/* without PLL lock info */
v &= ~KROSUS_PLL_LOCKED;
identity->version = v & 0xff;
identity->product = (v >> 8) & 0xf;
if (identity->product != KROSUS)
goto identification_error;
//From the SOC the version definition has changed
if ((identity->version & 0x3) == SOC) {
identity->in_soc = 1;
switch (identity->version) {
case SOC_8090_P1G_11R1:
dprintk("SOC 8090 P1-G11R1 Has been detected");
identity->p1g = 1;
break;
case SOC_8090_P1G_21R1:
dprintk("SOC 8090 P1-G21R1 Has been detected");
identity->p1g = 1;
break;
case SOC_7090_P1G_11R1:
dprintk("SOC 7090 P1-G11R1 Has been detected");
identity->p1g = 1;
break;
case SOC_7090_P1G_21R1:
dprintk("SOC 7090 P1-G21R1 Has been detected");
identity->p1g = 1;
break;
default:
goto identification_error;
}
} else {
switch ((identity->version >> 5) & 0x7) {
case MP001:
dprintk("MP001 : 9090/8096");
break;
case MP005:
dprintk("MP005 : Single Sband");
break;
case MP008:
dprintk("MP008 : diversity VHF-UHF-LBAND");
break;
case MP009:
dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
break;
default:
goto identification_error;
}
switch (identity->version & 0x1f) {
case P1G_21R2:
dprintk("P1G_21R2 detected");
identity->p1g = 1;
break;
case P1G:
dprintk("P1G detected");
identity->p1g = 1;
break;
case P1D_E_F:
dprintk("P1D/E/F detected");
break;
case P1C:
dprintk("P1C detected");
break;
case P1A_B:
dprintk("P1-A/B detected: driver is deactivated - not available");
goto identification_error;
break;
default:
goto identification_error;
}
}
return 0;
identification_error:
return -EIO;;
} }
static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg) static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
u16 PllCfg, i, v;
HARD_RESET(state); HARD_RESET(state);
dib0090_write_reg(state, 0x24, EN_PLL); dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
/* adcClkOutRatio=8->7, release reset */ if (!cfg->in_soc) {
dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); /* adcClkOutRatio=8->7, release reset */
dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
if (cfg->clkoutdrive != 0)
dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
| (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
else
dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
| (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
}
/* Read Pll current config * */
PllCfg = dib0090_read_reg(state, 0x21);
/** Reconfigure PLL if current setting is different from default setting **/
if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
&& !cfg->io.pll_bypass) {
/* Set Bypass mode */
PllCfg |= (1 << 15);
dib0090_write_reg(state, 0x21, PllCfg);
/* Set Reset Pll */
PllCfg &= ~(1 << 13);
dib0090_write_reg(state, 0x21, PllCfg);
/*** Set new Pll configuration in bypass and reset state ***/
PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
dib0090_write_reg(state, 0x21, PllCfg);
/* Remove Reset Pll */
PllCfg |= (1 << 13);
dib0090_write_reg(state, 0x21, PllCfg);
/*** Wait for PLL lock ***/
i = 100;
do {
v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
if (v)
break;
} while (--i);
if (i == 0) {
dprintk("Pll: Unable to lock Pll");
return;
}
/* Finally Remove Bypass mode */
PllCfg &= ~(1 << 15);
dib0090_write_reg(state, 0x21, PllCfg);
}
if (cfg->io.pll_bypass) {
PllCfg |= (cfg->io.pll_bypass << 15);
dib0090_write_reg(state, 0x21, PllCfg);
}
}
static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
{
struct dib0090_fw_state *state = fe->tuner_priv;
u16 PllCfg;
u16 v;
int i;
dprintk("fw reset digital");
HARD_RESET(state);
dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
dib0090_fw_write_reg(state, 0x20,
((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
if (cfg->clkoutdrive != 0) if (cfg->clkoutdrive != 0)
dib0090_write_reg(state, 0x23, v |= cfg->clkoutdrive << 5;
(0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
clkouttobamse
<< 4) | (0
<<
2)
| (0));
else else
dib0090_write_reg(state, 0x23, v |= 7 << 5;
(0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg->
clkouttobamse << 4) | (0 v |= 2 << 10;
<< dib0090_fw_write_reg(state, 0x23, v);
2)
| (0)); /* Read Pll current config * */
PllCfg = dib0090_fw_read_reg(state, 0x21);
/** Reconfigure PLL if current setting is different from default setting **/
if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
/* enable pll, de-activate reset, ratio: 2/1 = 60MHz */ /* Set Bypass mode */
dib0090_write_reg(state, 0x21, PllCfg |= (1 << 15);
(cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)); dib0090_fw_write_reg(state, 0x21, PllCfg);
/* Set Reset Pll */
PllCfg &= ~(1 << 13);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/*** Set new Pll configuration in bypass and reset state ***/
PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/* Remove Reset Pll */
PllCfg |= (1 << 13);
dib0090_fw_write_reg(state, 0x21, PllCfg);
/*** Wait for PLL lock ***/
i = 100;
do {
v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
if (v)
break;
} while (--i);
if (i == 0) {
dprintk("Pll: Unable to lock Pll");
return -EIO;
}
/* Finally Remove Bypass mode */
PllCfg &= ~(1 << 15);
dib0090_fw_write_reg(state, 0x21, PllCfg);
}
if (cfg->io.pll_bypass) {
PllCfg |= (cfg->io.pll_bypass << 15);
dib0090_fw_write_reg(state, 0x21, PllCfg);
}
return dib0090_fw_identify(fe);
} }
static int dib0090_wakeup(struct dvb_frontend *fe) static int dib0090_wakeup(struct dvb_frontend *fe)
...@@ -273,6 +589,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe) ...@@ -273,6 +589,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe)
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
if (state->config->sleep) if (state->config->sleep)
state->config->sleep(fe, 0); state->config->sleep(fe, 0);
/* enable dataTX in case we have been restarted in the wrong moment */
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
return 0; return 0;
} }
...@@ -292,8 +611,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast) ...@@ -292,8 +611,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
else else
dib0090_write_reg(state, 0x04, 1); dib0090_write_reg(state, 0x04, 1);
} }
EXPORT_SYMBOL(dib0090_dcc_freq); EXPORT_SYMBOL(dib0090_dcc_freq);
static const u16 bb_ramp_pwm_normal_socs[] = {
550, /* max BB gain in 10th of dB */
(1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
440,
(4 << 9) | 0, /* BB_RAMP3 = 26dB */
(0 << 9) | 208, /* BB_RAMP4 */
(4 << 9) | 208, /* BB_RAMP5 = 29dB */
(0 << 9) | 440, /* BB_RAMP6 */
};
static const u16 rf_ramp_pwm_cband_7090[] = {
280, /* max RF gain in 10th of dB */
18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
504, /* ramp_max = maximum X used on the ramp */
(29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
(0 << 10) | 504, /* RF_RAMP6, LNA 1 */
(60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
(0 << 10) | 364, /* RF_RAMP8, LNA 2 */
(34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
(0 << 10) | 228, /* GAIN_4_2, LNA 3 */
(37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
(0 << 10) | 109, /* RF_RAMP4, LNA 4 */
};
static const u16 rf_ramp_pwm_cband_8090[] = {
345, /* max RF gain in 10th of dB */
29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
1000, /* ramp_max = maximum X used on the ramp */
(35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
(0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
(58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
(0 << 10) | 772, /* RF_RAMP6, LNA 2 */
(27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
(0 << 10) | 496, /* RF_RAMP8, LNA 3 */
(40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
(0 << 10) | 200, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_uhf_7090[] = {
407, /* max RF gain in 10th of dB */
13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
529, /* ramp_max = maximum X used on the ramp */
(23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
(0 << 10) | 176, /* RF_RAMP4, LNA 1 */
(63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
(0 << 10) | 529, /* RF_RAMP6, LNA 2 */
(48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
(0 << 10) | 400, /* RF_RAMP8, LNA 3 */
(29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
(0 << 10) | 316, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_uhf_8090[] = {
388, /* max RF gain in 10th of dB */
26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
1008, /* ramp_max = maximum X used on the ramp */
(11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
(0 << 10) | 369, /* RF_RAMP4, LNA 1 */
(41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
(0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
(27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
(0 << 10) | 809, /* RF_RAMP8, LNA 3 */
(14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
(0 << 10) | 659, /* GAIN_4_2, LNA 4 */
};
static const u16 rf_ramp_pwm_cband[] = { static const u16 rf_ramp_pwm_cband[] = {
0, /* max RF gain in 10th of dB */ 0, /* max RF gain in 10th of dB */
0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
...@@ -326,6 +712,16 @@ static const u16 rf_ramp_uhf[] = { ...@@ -326,6 +712,16 @@ static const u16 rf_ramp_uhf[] = {
0, 0, 127, /* CBAND : 0.0 dB */ 0, 0, 127, /* CBAND : 0.0 dB */
}; };
static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
{
314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
84, 314, 127, /* LNA1 */
80, 230, 255, /* LNA2 */
80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
70, 70, 127, /* LNA4 */
0, 0, 127, /* CBAND */
};
static const u16 rf_ramp_cband[] = { static const u16 rf_ramp_cband[] = {
332, /* max RF gain in 10th of dB */ 332, /* max RF gain in 10th of dB */
132, 252, 127, /* LNA1, dB */ 132, 252, 127, /* LNA1, dB */
...@@ -380,8 +776,8 @@ static const u16 bb_ramp_pwm_normal[] = { ...@@ -380,8 +776,8 @@ static const u16 bb_ramp_pwm_normal[] = {
}; };
struct slope { struct slope {
int16_t range; s16 range;
int16_t slope; s16 slope;
}; };
static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val) static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
{ {
...@@ -597,19 +993,40 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe) ...@@ -597,19 +993,40 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
#endif #endif
#ifdef CONFIG_BAND_CBAND #ifdef CONFIG_BAND_CBAND
if (state->current_band == BAND_CBAND) { if (state->current_band == BAND_CBAND) {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); if (state->identity.in_soc) {
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
} else {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
}
} else } else
#endif #endif
#ifdef CONFIG_BAND_VHF #ifdef CONFIG_BAND_VHF
if (state->current_band == BAND_VHF) { if (state->current_band == BAND_VHF) {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf); if (state->identity.in_soc) {
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
//dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf_socs); /* TODO */
} else {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
}
} else } else
#endif #endif
{ {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf); if (state->identity.in_soc) {
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
} else {
dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
}
} }
if (state->rf_ramp[0] != 0) if (state->rf_ramp[0] != 0)
...@@ -617,11 +1034,22 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe) ...@@ -617,11 +1034,22 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
else else
dib0090_write_reg(state, 0x32, (0 << 11)); dib0090_write_reg(state, 0x32, (0 << 11));
dib0090_write_reg(state, 0x04, 0x01);
dib0090_write_reg(state, 0x39, (1 << 10)); dib0090_write_reg(state, 0x39, (1 << 10));
} }
} }
EXPORT_SYMBOL(dib0090_pwm_gain_reset); EXPORT_SYMBOL(dib0090_pwm_gain_reset);
static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
{
u16 adc_val = dib0090_read_reg(state, 0x1d);
if (state->identity.in_soc) {
adc_val >>= 2;
}
return adc_val;
}
int dib0090_gain_control(struct dvb_frontend *fe) int dib0090_gain_control(struct dvb_frontend *fe)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
...@@ -643,18 +1071,21 @@ int dib0090_gain_control(struct dvb_frontend *fe) ...@@ -643,18 +1071,21 @@ int dib0090_gain_control(struct dvb_frontend *fe)
} else } else
#endif #endif
#ifdef CONFIG_BAND_VHF #ifdef CONFIG_BAND_VHF
if (state->current_band == BAND_VHF) { if (state->current_band == BAND_VHF && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_vhf); dib0090_set_rframp(state, rf_ramp_vhf);
dib0090_set_bbramp(state, bb_ramp_boost); dib0090_set_bbramp(state, bb_ramp_boost);
} else } else
#endif #endif
#ifdef CONFIG_BAND_CBAND #ifdef CONFIG_BAND_CBAND
if (state->current_band == BAND_CBAND) { if (state->current_band == BAND_CBAND && !state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_cband); dib0090_set_rframp(state, rf_ramp_cband);
dib0090_set_bbramp(state, bb_ramp_boost); dib0090_set_bbramp(state, bb_ramp_boost);
} else } else
#endif #endif
{ if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
dib0090_set_bbramp(state, bb_ramp_boost);
} else {
dib0090_set_rframp(state, rf_ramp_uhf); dib0090_set_rframp(state, rf_ramp_uhf);
dib0090_set_bbramp(state, bb_ramp_boost); dib0090_set_bbramp(state, bb_ramp_boost);
} }
...@@ -669,17 +1100,25 @@ int dib0090_gain_control(struct dvb_frontend *fe) ...@@ -669,17 +1100,25 @@ int dib0090_gain_control(struct dvb_frontend *fe)
*tune_state = CT_AGC_STEP_0; *tune_state = CT_AGC_STEP_0;
} else if (!state->agc_freeze) { } else if (!state->agc_freeze) {
s16 wbd; s16 wbd = 0, i, cnt;
int adc; int adc;
wbd_val = dib0090_read_reg(state, 0x1d); wbd_val = dib0090_get_slow_adc_val(state);
/* read and calc the wbd power */ if (*tune_state == CT_AGC_STEP_0)
wbd = dib0090_wbd_to_db(state, wbd_val); cnt = 5;
else
cnt = 1;
for (i = 0; i < cnt; i++) {
wbd_val = dib0090_get_slow_adc_val(state);
wbd += dib0090_wbd_to_db(state, wbd_val);
}
wbd /= cnt;
wbd_error = state->wbd_target - wbd; wbd_error = state->wbd_target - wbd;
if (*tune_state == CT_AGC_STEP_0) { if (*tune_state == CT_AGC_STEP_0) {
if (wbd_error < 0 && state->rf_gain_limit > 0) { if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
#ifdef CONFIG_BAND_CBAND #ifdef CONFIG_BAND_CBAND
/* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */ /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
...@@ -700,39 +1139,39 @@ int dib0090_gain_control(struct dvb_frontend *fe) ...@@ -700,39 +1139,39 @@ int dib0090_gain_control(struct dvb_frontend *fe)
adc_error = (s16) (((s32) ADC_TARGET) - adc); adc_error = (s16) (((s32) ADC_TARGET) - adc);
#ifdef CONFIG_STANDARD_DAB #ifdef CONFIG_STANDARD_DAB
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
adc_error += 130; adc_error -= 10;
#endif #endif
#ifdef CONFIG_STANDARD_DVBT #ifdef CONFIG_STANDARD_DVBT
if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
(state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16)) (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
adc_error += 60; adc_error += 60;
#endif #endif
#ifdef CONFIG_SYS_ISDBT #ifdef CONFIG_SYS_ISDBT
if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
0) 0)
&& &&
((state->fe->dtv_property_cache.layer[0].modulation == ((state->fe->dtv_property_cache.layer[0].modulation ==
QAM_64) QAM_64)
|| (state->fe->dtv_property_cache.layer[0]. || (state->fe->dtv_property_cache.
modulation == QAM_16))) layer[0].modulation == QAM_16)))
|| ||
((state->fe->dtv_property_cache.layer[1].segment_count > ((state->fe->dtv_property_cache.layer[1].segment_count >
0) 0)
&& &&
((state->fe->dtv_property_cache.layer[1].modulation == ((state->fe->dtv_property_cache.layer[1].modulation ==
QAM_64) QAM_64)
|| (state->fe->dtv_property_cache.layer[1]. || (state->fe->dtv_property_cache.
modulation == QAM_16))) layer[1].modulation == QAM_16)))
|| ||
((state->fe->dtv_property_cache.layer[2].segment_count > ((state->fe->dtv_property_cache.layer[2].segment_count >
0) 0)
&& &&
((state->fe->dtv_property_cache.layer[2].modulation == ((state->fe->dtv_property_cache.layer[2].modulation ==
QAM_64) QAM_64)
|| (state->fe->dtv_property_cache.layer[2]. || (state->fe->dtv_property_cache.
modulation == QAM_16))) layer[2].modulation == QAM_16)))
) )
) )
adc_error += 60; adc_error += 60;
#endif #endif
...@@ -760,9 +1199,9 @@ int dib0090_gain_control(struct dvb_frontend *fe) ...@@ -760,9 +1199,9 @@ int dib0090_gain_control(struct dvb_frontend *fe)
} }
#ifdef DEBUG_AGC #ifdef DEBUG_AGC
dprintk dprintk
("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
(u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
(u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
#endif #endif
} }
...@@ -771,6 +1210,7 @@ int dib0090_gain_control(struct dvb_frontend *fe) ...@@ -771,6 +1210,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
return ret; return ret;
} }
EXPORT_SYMBOL(dib0090_gain_control); EXPORT_SYMBOL(dib0090_gain_control);
void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
...@@ -785,13 +1225,53 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * ...@@ -785,13 +1225,53 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
if (rflt) if (rflt)
*rflt = (state->rf_lt_def >> 10) & 0x7; *rflt = (state->rf_lt_def >> 10) & 0x7;
} }
EXPORT_SYMBOL(dib0090_get_current_gain); EXPORT_SYMBOL(dib0090_get_current_gain);
u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
{ {
struct dib0090_state *st = tuner->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
return st->wbd_offset; u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
s32 current_temp = state->temperature;
s32 wbd_thot, wbd_tcold;
const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
while (f_MHz > wbd->max_freq)
wbd++;
dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
if (current_temp < 0)
current_temp = 0;
if (current_temp > 128)
current_temp = 128;
//What Wbd gain to apply for this range of frequency
state->wbdmux &= ~(7 << 13);
if (wbd->wbd_gain != 0)
state->wbdmux |= (wbd->wbd_gain << 13);
else
state->wbdmux |= (4 << 13); // 4 is the default WBD gain
dib0090_write_reg(state, 0x10, state->wbdmux);
//All the curves are linear with slope*f/64+offset
wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
// Iet assumes that thot-tcold = 130 equiv 128, current temperature ref is -30deg
wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
//for (offset = 0; offset < 1000; offset += 4)
// dbgp("offset = %d -> %d\n", offset, dib0090_wbd_to_db(state, offset));
state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold); // get the value in dBm from the offset
dprintk("wbd-target: %d dB", (u32) state->wbd_target);
dprintk("wbd offset applied is %d", wbd_tcold);
return state->wbd_offset + wbd_tcold;
} }
EXPORT_SYMBOL(dib0090_get_wbd_offset); EXPORT_SYMBOL(dib0090_get_wbd_offset);
static const u16 dib0090_defaults[] = { static const u16 dib0090_defaults[] = {
...@@ -801,7 +1281,7 @@ static const u16 dib0090_defaults[] = { ...@@ -801,7 +1281,7 @@ static const u16 dib0090_defaults[] = {
0x99a0, 0x99a0,
0x6008, 0x6008,
0x0000, 0x0000,
0x8acb, 0x8bcb,
0x0000, 0x0000,
0x0405, 0x0405,
0x0000, 0x0000,
...@@ -829,8 +1309,6 @@ static const u16 dib0090_defaults[] = { ...@@ -829,8 +1309,6 @@ static const u16 dib0090_defaults[] = {
1, 0x39, 1, 0x39,
0x0000, 0x0000,
1, 0x1b,
EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
2, 0x1e, 2, 0x1e,
0x07FF, 0x07FF,
0x0007, 0x0007,
...@@ -844,50 +1322,126 @@ static const u16 dib0090_defaults[] = { ...@@ -844,50 +1322,126 @@ static const u16 dib0090_defaults[] = {
0 0
}; };
static int dib0090_reset(struct dvb_frontend *fe) static const u16 dib0090_p1g_additionnal_defaults[] = {
{ // additionnal INITIALISATION for p1g to be written after dib0090_defaults
struct dib0090_state *state = fe->tuner_priv; 1, 0x05,
u16 l, r, *n; 0xabcd,
dib0090_reset_digital(fe, state->config); 1, 0x11,
state->revision = dib0090_identify(fe); 0x00b4,
/* Revision definition */
if (state->revision == 0xff)
return -EINVAL;
#ifdef EFUSE
else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
dib0090_set_EFUSE(state);
#endif
#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 1, 0x1c,
if (!(state->revision & 0x1)) /* it is P1B - reset is already done */ 0xfffd,
return 0;
#endif 1, 0x40,
0x108,
0
};
static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
{
u16 l, r;
/* Upload the default values */
n = (u16 *) dib0090_defaults;
l = pgm_read_word(n++); l = pgm_read_word(n++);
while (l) { while (l) {
r = pgm_read_word(n++); r = pgm_read_word(n++);
do { do {
/* DEBUG_TUNER */
/* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
dib0090_write_reg(state, r, pgm_read_word(n++)); dib0090_write_reg(state, r, pgm_read_word(n++));
r++; r++;
} while (--l); } while (--l);
l = pgm_read_word(n++); l = pgm_read_word(n++);
} }
}
#define CAP_VALUE_MIN (u8) 9
#define CAP_VALUE_MAX (u8) 40
#define HR_MIN (u8) 25
#define HR_MAX (u8) 40
#define POLY_MIN (u8) 0
#define POLY_MAX (u8) 8
void dib0090_set_EFUSE(struct dib0090_state *state)
{
u8 c,h,n;
u16 e2,e4;
u16 cal;
e2=dib0090_read_reg(state,0x26);
e4=dib0090_read_reg(state,0x28);
if ((state->identity.version == P1D_E_F) || // All P1F uses the internal calibration
(state->identity.version == P1G) || (e2 == 0xffff)) { //W0090G11R1 and W0090G11R1-D : We will find the calibration Value of the Baseband
dib0090_write_reg(state,0x22,0x10); //Start the Calib
cal = (dib0090_read_reg(state,0x22)>>6) & 0x3ff;
if ((cal<670) || (cal==1023)) //Cal at 800 would give too high value for the n
cal=850; //Recenter the n to 32
n = 165 - ((cal * 10)>>6) ;
e2 = e4 = (3<<12) | (34<<6) | (n);
}
if (e2!=e4) {
e2 &= e4; /* Remove the redundancy */
}
if (e2 != 0xffff) {
c = e2 & 0x3f;
n = (e2 >> 12) & 0xf;
h= (e2 >> 6) & 0x3f;
if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
c=32;
if ((h >= HR_MAX) || (h <= HR_MIN))
h=34;
if ((n >= POLY_MAX) || (n <= POLY_MIN))
n=3;
dib0090_write_reg(state,0x13, (h << 10)) ;
e2 = (n<<11) | ((h>>2)<<6) | (c);
dib0090_write_reg(state,0x2, e2) ; /* Load the BB_2 */
}
}
static int dib0090_reset(struct dvb_frontend *fe)
{
struct dib0090_state *state = fe->tuner_priv;
dib0090_reset_digital(fe, state->config);
if (dib0090_identify(fe) < 0)
return -EIO;
#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
return 0;
#endif
if (!state->identity.in_soc) {
if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
else
dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
}
dib0090_set_default_config(state, dib0090_defaults);
if (state->identity.in_soc)
dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
if (state->identity.p1g)
dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
dib0090_set_EFUSE(state);
/* Congigure in function of the crystal */ /* Congigure in function of the crystal */
if (state->config->io.clock_khz >= 24000) if (state->config->io.clock_khz >= 24000)
l = 1; dib0090_write_reg(state, 0x14, 1);
else else
l = 2; dib0090_write_reg(state, 0x14, 2);
dib0090_write_reg(state, 0x14, l);
dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
state->reset = 3; /* enable iq-offset-calibration and wbd-calibration when tuning next time */ state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
return 0; return 0;
} }
...@@ -927,11 +1481,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st ...@@ -927,11 +1481,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st
} }
struct dc_calibration { struct dc_calibration {
uint8_t addr; u8 addr;
uint8_t offset; u8 offset;
uint8_t pga:1; u8 pga:1;
uint16_t bb1; u16 bb1;
uint8_t i:1; u8 i:1;
}; };
static const struct dc_calibration dc_table[] = { static const struct dc_calibration dc_table[] = {
...@@ -944,6 +1498,17 @@ static const struct dc_calibration dc_table[] = { ...@@ -944,6 +1498,17 @@ static const struct dc_calibration dc_table[] = {
{0}, {0},
}; };
static const struct dc_calibration dc_p1g_table[] = {
/* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
/* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
{0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1}, // offset_trim2_i_chann 0 0 5 0 0 1 6 9 5
{0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0}, // offset_trim2_q_chann 0 0 5 0 0 1 7 15 11
/* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
{0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1}, // offset_trim1_i_chann 0 0 5 0 0 1 6 4 0
{0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0}, // offset_trim1_q_chann 0 0 5 0 0 1 6 14 10
{0},
};
static void dib0090_set_trim(struct dib0090_state *state) static void dib0090_set_trim(struct dib0090_state *state)
{ {
u16 *val; u16 *val;
...@@ -962,41 +1527,45 @@ static void dib0090_set_trim(struct dib0090_state *state) ...@@ -962,41 +1527,45 @@ static void dib0090_set_trim(struct dib0090_state *state)
static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{ {
int ret = 0; int ret = 0;
u16 reg;
switch (*tune_state) { switch (*tune_state) {
case CT_TUNER_START: case CT_TUNER_START:
/* init */ dprintk("Start DC offset calibration");
dprintk("Internal DC calibration");
/* the LNA is off */
dib0090_write_reg(state, 0x24, 0x02ed);
/* force vcm2 = 0.8V */ /* force vcm2 = 0.8V */
state->bb6 = 0; state->bb6 = 0;
state->bb7 = 0x040d; state->bb7 = 0x040d;
/* the LNA AND LO are off */
reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
dib0090_write_reg(state, 0x24, reg);
state->wbdmux = dib0090_read_reg(state, 0x10);
dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); // connect BB, disable WDB enable*
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); //Discard the DataTX
state->dc = dc_table; state->dc = dc_table;
if (state->identity.p1g)
state->dc = dc_p1g_table;
*tune_state = CT_TUNER_STEP_0; *tune_state = CT_TUNER_STEP_0;
/* fall through */ /* fall through */
case CT_TUNER_STEP_0: case CT_TUNER_STEP_0:
dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
dib0090_write_reg(state, 0x01, state->dc->bb1); dib0090_write_reg(state, 0x01, state->dc->bb1);
dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
state->step = 0; state->step = 0;
state->min_adc_diff = 1023; state->min_adc_diff = 1023;
*tune_state = CT_TUNER_STEP_1; *tune_state = CT_TUNER_STEP_1;
ret = 50; ret = 50;
break; break;
case CT_TUNER_STEP_1: case CT_TUNER_STEP_1:
dib0090_set_trim(state); dib0090_set_trim(state);
*tune_state = CT_TUNER_STEP_2; *tune_state = CT_TUNER_STEP_2;
break; break;
...@@ -1007,7 +1576,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front ...@@ -1007,7 +1576,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
break; break;
case CT_TUNER_STEP_5: /* found an offset */ case CT_TUNER_STEP_5: /* found an offset */
dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step); dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
if (state->step == 0 && state->adc_diff < 0) {
state->min_adc_diff = -1023;
dprintk("Change of sign of the minimum adc diff");
}
dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
/* first turn for this frequency */ /* first turn for this frequency */
if (state->step == 0) { if (state->step == 0) {
...@@ -1017,20 +1592,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front ...@@ -1017,20 +1592,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
state->step = 0x10; state->step = 0x10;
} }
state->adc_diff = ABS(state->adc_diff); /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */ /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
state->step++; state->step++;
state->min_adc_diff = state->adc_diff; state->min_adc_diff = state->adc_diff; //min is used as N-1
*tune_state = CT_TUNER_STEP_1; *tune_state = CT_TUNER_STEP_1;
} else { } else {
/* the minimum was what we have seen in the step before */ /* the minimum was what we have seen in the step before */
state->step--; if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) { //Come back to the previous state since the delta was better
dib0090_set_trim(state); dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
state->step--;
}
dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff, dib0090_set_trim(state);
state->step); dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
state->dc++; state->dc++;
if (state->dc->addr == 0) /* done */ if (state->dc->addr == 0) /* done */
...@@ -1042,10 +1618,10 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front ...@@ -1042,10 +1618,10 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
break; break;
case CT_TUNER_STEP_6: case CT_TUNER_STEP_6:
dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); //Force the test bus to be off
dib0090_write_reg(state, 0x1f, 0x7); dib0090_write_reg(state, 0x1f, 0x7);
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
state->reset &= ~0x1; state->calibrate &= ~DC_CAL;
default: default:
break; break;
} }
...@@ -1054,21 +1630,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front ...@@ -1054,21 +1630,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{ {
u8 wbd_gain;
const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
switch (*tune_state) { switch (*tune_state) {
case CT_TUNER_START: case CT_TUNER_START:
/* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */ while (state->current_rf / 1000 > wbd->max_freq)
dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10)); wbd++;
dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff); if (wbd->wbd_gain != 0)
wbd_gain = wbd->wbd_gain;
else {
wbd_gain = 4;
#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
wbd_gain = 2;
#endif
}
if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
*tune_state = CT_TUNER_START;
state->calibrate &= ~WBD_CAL;
return 0;
}
dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); // Force: WBD enable,gain to 4, mux to WBD
dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); //Discard all LNA but crystal !!!
*tune_state = CT_TUNER_STEP_0; *tune_state = CT_TUNER_STEP_0;
state->wbd_calibration_gain = wbd_gain;
return 90; /* wait for the WBDMUX to switch and for the ADC to sample */ return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
case CT_TUNER_STEP_0: case CT_TUNER_STEP_0:
state->wbd_offset = dib0090_read_reg(state, 0x1d); state->wbd_offset = dib0090_get_slow_adc_val(state);
dprintk("WBD calibration offset = %d", state->wbd_offset); dprintk("WBD calibration offset = %d", state->wbd_offset);
*tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
state->reset &= ~0x2; state->calibrate &= ~WBD_CAL;
break; break;
default: default:
break; break;
} }
...@@ -1092,6 +1690,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state) ...@@ -1092,6 +1690,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state)
state->bb_1_def |= tmp; state->bb_1_def |= tmp;
dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
if (state->identity.in_soc) {
dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
} else {
dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
}
} }
static const struct dib0090_pll dib0090_pll_table[] = { static const struct dib0090_pll dib0090_pll_table[] = {
...@@ -1180,6 +1787,266 @@ static const struct dib0090_tuning dib0090_tuning_table[] = { ...@@ -1180,6 +1787,266 @@ static const struct dib0090_tuning dib0090_tuning_table[] = {
#endif #endif
}; };
static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
#ifdef CONFIG_BAND_CBAND
{170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB}, // FM EN_CAB
#endif
#ifdef CONFIG_BAND_VHF
{184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
{227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
{380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
#endif
#ifdef CONFIG_BAND_UHF
{510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD}, // SBD EN_SBD
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD}, // SBD EN_SBD
#endif
};
static const struct dib0090_pll dib0090_p1g_pll_table[] = {
#ifdef CONFIG_BAND_CBAND
{57000, 0, 11, 48, 6}, // CAB
{70000, 1, 11, 48, 6}, // CAB
{86000, 0, 10, 32, 4}, // CAB
{105000, 1, 10, 32, 4}, // FM
{115000, 0, 9, 24, 6}, // FM
{140000, 1, 9, 24, 6}, // MID FM VHF
{170000, 0, 8, 16, 4}, // MID FM VHF
#endif
#ifdef CONFIG_BAND_VHF
{200000, 1, 8, 16, 4}, // VHF
{230000, 0, 7, 12, 6}, // VHF
{280000, 1, 7, 12, 6}, // MID VHF UHF
{340000, 0, 6, 8, 4}, // MID VHF UHF
{380000, 1, 6, 8, 4}, // MID VHF UHF
{455000, 0, 5, 6, 6}, // MID VHF UHF
#endif
#ifdef CONFIG_BAND_UHF
{580000, 1, 5, 6, 6}, // UHF
{680000, 0, 4, 4, 4}, // UHF
{860000, 1, 4, 4, 4}, // UHF
#endif
#ifdef CONFIG_BAND_LBAND
{1800000, 1, 2, 2, 4}, // LBD
#endif
#ifdef CONFIG_BAND_SBAND
{2900000, 0, 1, 1, 6}, // SBD
#endif
};
static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
#ifdef CONFIG_BAND_CBAND
{184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB // 0x8190 Good perf but higher current //0x4187 Low current
{227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB
{380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB
#endif
#ifdef CONFIG_BAND_UHF
{520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
{900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
#endif
#ifdef CONFIG_BAND_LBAND
{1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
{1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
{1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
#endif
#ifdef CONFIG_BAND_SBAND
{2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD}, // SBD EN_SBD
{2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD}, // SBD EN_SBD
#endif
};
static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
//max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
#ifdef CONFIG_BAND_CBAND
//{ 184000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB }, // 0x81ce 0x8190 Good perf but higher current //0x4187 Low current
{300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
{380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB}, //0x4187
{570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
{858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
#endif
};
static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 0;
u16 lo4 = 0xe900;
s16 adc_target;
u16 adc;
s8 step_sign;
u8 force_soft_search = 0;
if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
force_soft_search = 1;
if (*tune_state == CT_TUNER_START) {
dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
dib0090_write_reg(state, 0x10, 0x2B1);
dib0090_write_reg(state, 0x1e, 0x0032);
if (!state->tuner_is_tuned) {
/* prepare a complete captrim */
if (!state->identity.p1g || force_soft_search)
state->step = state->captrim = state->fcaptrim = 64;
state->current_rf = state->rf_request;
} else { /* we are already tuned to this frequency - the configuration is correct */
if (!state->identity.p1g || force_soft_search) {
/* do a minimal captrim even if the frequency has not changed */
state->step = 4;
state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
}
}
state->adc_diff = 3000; // start with a unreachable high number : only set for KROSUS < P1G */
*tune_state = CT_TUNER_STEP_0;
} else if (*tune_state == CT_TUNER_STEP_0) {
if (state->identity.p1g && !force_soft_search) {
// 30MHz => Code 15 for the ration => 128us to lock. Giving approximately
u8 ratio = 31; // (state->config->io.clock_khz / 1024 + 1) & 0x1f;
dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
dib0090_read_reg(state, 0x40);
//dib0090_write_reg(state, 0x40, (3<<7) | ((((state->config->io.clock_khz >> 11)+1) & 0x1f)<<2) | (1<<1) | 1);
ret = 50;
} else {
state->step /= 2;
dib0090_write_reg(state, 0x18, lo4 | state->captrim);
if (state->identity.in_soc)
ret = 25;
}
*tune_state = CT_TUNER_STEP_1;
} else if (*tune_state == CT_TUNER_STEP_1) {
if (state->identity.p1g && !force_soft_search) {
dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
dib0090_read_reg(state, 0x40);
state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
dprintk("***Final Captrim= 0x%x", state->fcaptrim);
*tune_state = CT_TUNER_STEP_3;
} else {
/* MERGE for all krosus before P1G */
adc = dib0090_get_slow_adc_val(state);
dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
adc_target = 200;
} else
adc_target = 400;
if (adc >= adc_target) {
adc -= adc_target;
step_sign = -1;
} else {
adc = adc_target - adc;
step_sign = 1;
}
if (adc < state->adc_diff) {
dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
state->adc_diff = adc;
state->fcaptrim = state->captrim;
//we could break here, to save time, if we reached a close-enough value
//e.g.: if (state->adc_diff < 20)
//break;
}
state->captrim += step_sign * state->step;
if (state->step >= 1)
*tune_state = CT_TUNER_STEP_0;
else
*tune_state = CT_TUNER_STEP_2;
ret = 25; //LOLO changed from 15
}
} else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
/*write the final cptrim config */
dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
*tune_state = CT_TUNER_STEP_3;
} else if (*tune_state == CT_TUNER_STEP_3) {
state->calibrate &= ~CAPTRIM_CAL;
*tune_state = CT_TUNER_STEP_0;
}
return ret;
}
static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
{
int ret = 15;
s16 val;
//The assumption is that the AGC is not active
switch (*tune_state) {
case CT_TUNER_START:
state->wbdmux = dib0090_read_reg(state, 0x10);
dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); //Move to the bias and clear the wbd enable
state->bias = dib0090_read_reg(state, 0x13);
dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); //Move to the Ref
*tune_state = CT_TUNER_STEP_0;
/* wait for the WBDMUX to switch and for the ADC to sample */
break;
case CT_TUNER_STEP_0:
state->adc_diff = dib0090_get_slow_adc_val(state); // Get the value for the Ref
dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); //Move to the Ptat
*tune_state = CT_TUNER_STEP_1;
break;
case CT_TUNER_STEP_1:
val = dib0090_get_slow_adc_val(state); // Get the value for the Ptat
state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; // +55 is defined as = -30deg
dprintk("temperature: %d C", state->temperature - 30);
*tune_state = CT_TUNER_STEP_2;
break;
case CT_TUNER_STEP_2:
//Reload the start values.
dib0090_write_reg(state, 0x13, state->bias);
dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
*tune_state = CT_TUNER_START;
state->calibrate &= ~TEMP_CAL;
if (state->config->analog_output == 0)
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); //Set the DataTX
break;
default:
ret = 0;
break;
}
return ret;
}
#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
static int dib0090_tune(struct dvb_frontend *fe) static int dib0090_tune(struct dvb_frontend *fe)
{ {
...@@ -1188,91 +2055,139 @@ static int dib0090_tune(struct dvb_frontend *fe) ...@@ -1188,91 +2055,139 @@ static int dib0090_tune(struct dvb_frontend *fe)
const struct dib0090_pll *pll = state->current_pll_table_index; const struct dib0090_pll *pll = state->current_pll_table_index;
enum frontend_tune_state *tune_state = &state->tune_state; enum frontend_tune_state *tune_state = &state->tune_state;
u32 rf; u16 lo5, lo6, Den, tmp;
u16 lo4 = 0xe900, lo5, lo6, Den;
u32 FBDiv, Rest, FREF, VCOF_kHz = 0; u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
u16 tmp, adc;
int8_t step_sign;
int ret = 10; /* 1ms is the default delay most of the time */ int ret = 10; /* 1ms is the default delay most of the time */
u8 c, i; u8 c, i;
state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); /************************* VCO ***************************/
rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
/* in any case we first need to do a reset if needed */
if (state->reset & 0x1)
return dib0090_dc_offset_calibration(state, tune_state);
else if (state->reset & 0x2)
return dib0090_wbd_calibration(state, tune_state);
/************************* VCO ***************************/
/* Default values for FG */ /* Default values for FG */
/* from these are needed : */ /* from these are needed : */
/* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */ /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
#ifdef CONFIG_SYS_ISDBT /* in any case we first need to do a calibration if needed */
if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) if (*tune_state == CT_TUNER_START) {
rf += 850; /* deactivate DataTX before some calibrations */
#endif if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
else /* Activate DataTX in case a calibration has been done before */ if (state->config->analog_output == 0)
dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
}
if (state->current_rf != rf) { if (state->calibrate & DC_CAL)
state->tuner_is_tuned = 0; return dib0090_dc_offset_calibration(state, tune_state);
else if (state->calibrate & WBD_CAL) {
if (state->current_rf == 0) {
state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
}
return dib0090_wbd_calibration(state, tune_state);
} else if (state->calibrate & TEMP_CAL)
return dib0090_get_temperature(state, tune_state);
else if (state->calibrate & CAPTRIM_CAL)
return dib0090_captrim_search(state, tune_state);
tune = dib0090_tuning_table; if (*tune_state == CT_TUNER_START) {
/* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
if (state->config->use_pwm_agc && state->identity.in_soc) {
tmp = dib0090_read_reg(state, 0x39);
if ((tmp >> 10) & 0x1)
dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); // disengage mux : en_mux_bb1 = 0
}
tmp = (state->revision >> 5) & 0x7; state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
if (tmp == 0x4 || tmp == 0x7) { state->rf_request =
/* CBAND tuner version for VHF */ state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
if (state->current_band == BAND_FM || state->current_band == BAND_VHF) { BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
/* Force CBAND */ freq_offset_khz_vhf);
state->current_band = BAND_CBAND;
tune = dib0090_tuning_table_fm_vhf_on_cband; /* in ISDB-T 1seg we shift tuning frequency */
if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
&& state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
u8 found_offset = 0;
u32 margin_khz = 100;
if (LUT_offset != NULL) {
while (LUT_offset->RF_freq != 0xffff) {
if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
&& (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
&& LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
state->rf_request += LUT_offset->offset_khz;
found_offset = 1;
break;
}
LUT_offset++;
}
} }
if (found_offset == 0)
state->rf_request += 400;
} }
if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
state->tuner_is_tuned = 0;
state->current_rf = 0;
state->current_standard = 0;
pll = dib0090_pll_table; tune = dib0090_tuning_table;
/* Look for the interval */ if (state->identity.p1g)
while (rf > tune->max_freq) tune = dib0090_p1g_tuning_table;
tune++;
while (rf > pll->max_freq)
pll++;
state->current_tune_table_index = tune;
state->current_pll_table_index = pll;
}
if (*tune_state == CT_TUNER_START) { tmp = (state->identity.version >> 5) & 0x7;
if (state->tuner_is_tuned == 0) if (state->identity.in_soc) {
state->current_rf = 0; if (state->config->force_cband_input) { /* Use the CBAND input for all band */
if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
|| state->current_band & BAND_UHF) {
state->current_band = BAND_CBAND;
tune = dib0090_tuning_table_cband_7090;
}
} else { /* Use the CBAND input for all band under UHF */
if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
state->current_band = BAND_CBAND;
tune = dib0090_tuning_table_cband_7090;
}
}
} else
if (tmp == 0x4 || tmp == 0x7) {
/* CBAND tuner version for VHF */
if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
state->current_band = BAND_CBAND; /* Force CBAND */
tune = dib0090_tuning_table_fm_vhf_on_cband;
if (state->identity.p1g)
tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
}
}
if (state->current_rf != rf) { pll = dib0090_pll_table;
if (state->identity.p1g)
pll = dib0090_p1g_pll_table;
dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); /* Look for the interval */
while (state->rf_request > tune->max_freq)
tune++;
while (state->rf_request > pll->max_freq)
pll++;
/* external loop filter, otherwise: state->current_tune_table_index = tune;
* lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; state->current_pll_table_index = pll;
* lo6 = 0x0e34 */
if (pll->vco_band)
lo5 = 0x049e;
else if (state->config->analog_output)
lo5 = 0x041d;
else
lo5 = 0x041c;
lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */ // select internal switch
dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
if (!state->config->io.pll_int_loop_filt)
lo6 = 0xff28;
else
lo6 = (state->config->io.pll_int_loop_filt << 3);
VCOF_kHz = (pll->hfdiv * rf) * 2; // Find the VCO frequency in MHz
VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
FREF = state->config->io.clock_khz; FREF = state->config->io.clock_khz; // REFDIV is 1FREF Has to be as Close as possible to 10MHz
if (state->config->fref_clock_ratio != 0)
FREF /= state->config->fref_clock_ratio;
// Determine the FB divider
// The reference is 10MHz, Therefore the FBdivider is on the first digits
FBDiv = (VCOF_kHz / pll->topresc / FREF); FBDiv = (VCOF_kHz / pll->topresc / FREF);
Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; //in kHz
// Avoid Spurs in the loopfilter bandwidth
if (Rest < LPF) if (Rest < LPF)
Rest = 0; Rest = 0;
else if (Rest < 2 * LPF) else if (Rest < 2 * LPF)
...@@ -1280,147 +2195,155 @@ static int dib0090_tune(struct dvb_frontend *fe) ...@@ -1280,147 +2195,155 @@ static int dib0090_tune(struct dvb_frontend *fe)
else if (Rest > (FREF - LPF)) { else if (Rest > (FREF - LPF)) {
Rest = 0; Rest = 0;
FBDiv += 1; FBDiv += 1;
} else if (Rest > (FREF - 2 * LPF)) } //Go to the next FB
else if (Rest > (FREF - 2 * LPF))
Rest = FREF - 2 * LPF; Rest = FREF - 2 * LPF;
Rest = (Rest * 6528) / (FREF / 10); Rest = (Rest * 6528) / (FREF / 10);
state->rest = Rest;
Den = 1; /* external loop filter, otherwise:
* lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
* lo6 = 0x0e34 */
if (Rest == 0) {
if (pll->vco_band)
lo5 = 0x049f;
//else if (state->config->analog_output)
// lo5 = 0x041f;
else
lo5 = 0x041f;
} else {
if (pll->vco_band)
lo5 = 0x049e;
else if (state->config->analog_output)
lo5 = 0x041d;
else
lo5 = 0x041c;
}
if (state->identity.p1g) { /* Bias is done automatically in P1G */
if (state->identity.in_soc) {
if (state->identity.version == SOC_8090_P1G_11R1)
lo5 = 0x46f;
else
lo5 = 0x42f;
} else
lo5 = 0x42c; //BIAS Lo set to 4 by default in case of the Captrim search does not take care of the VCO Bias
}
lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
//Internal loop filter set...
if (!state->config->io.pll_int_loop_filt) {
if (state->identity.in_soc)
lo6 = 0xff98;
else if (state->identity.p1g || (Rest == 0))
lo6 = 0xfff8;
else
lo6 = 0xff28;
} else
lo6 = (state->config->io.pll_int_loop_filt << 3); // take the loop filter value given by the layout
//dprintk("lo6 = 0x%04x", (u32)lo6);
dprintk(" ***** ******* Rest value = %d", Rest); Den = 1;
if (Rest > 0) { if (Rest > 0) {
if (state->config->analog_output) if (state->config->analog_output)
lo6 |= (1 << 2) | 2; lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
else else {
lo6 |= (1 << 2) | 1; if (state->identity.in_soc)
lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
else
lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
}
Den = 255; Den = 255;
} }
#ifdef CONFIG_BAND_SBAND // Now we have to define the Num and Denum
if (state->current_band == BAND_SBAND) // LO1 gets the FBdiv
lo6 &= 0xfffb;
#endif
dib0090_write_reg(state, 0x15, (u16) FBDiv); dib0090_write_reg(state, 0x15, (u16) FBDiv);
// LO2 gets the REFDiv
dib0090_write_reg(state, 0x16, (Den << 8) | 1); if (state->config->fref_clock_ratio != 0)
dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
else
dib0090_write_reg(state, 0x16, (Den << 8) | 1);
// LO3 for the Numerator
dib0090_write_reg(state, 0x17, (u16) Rest); dib0090_write_reg(state, 0x17, (u16) Rest);
// VCO and HF DIV
dib0090_write_reg(state, 0x19, lo5); dib0090_write_reg(state, 0x19, lo5);
// SIGMA Delta
dib0090_write_reg(state, 0x1c, lo6); dib0090_write_reg(state, 0x1c, lo6);
// Check if the 0090 is analogged configured
//Disable ADC and DigPLL =0xFF9F, 0xffbf for test purposes.
//Enable The Outputs of the BB on DATA_Tx
lo6 = tune->tuner_enable; lo6 = tune->tuner_enable;
if (state->config->analog_output) if (state->config->analog_output)
lo6 = (lo6 & 0xff9f) | 0x2; lo6 = (lo6 & 0xff9f) | 0x2;
dib0090_write_reg(state, 0x24, lo6 | EN_LO dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
#ifdef CONFIG_DIB0090_USE_PWM_AGC
| state->config->use_pwm_agc * EN_CRYSTAL
#endif
);
state->current_rf = rf;
/* prepare a complete captrim */
state->step = state->captrim = state->fcaptrim = 64;
} else { /* we are already tuned to this frequency - the configuration is correct */
/* do a minimal captrim even if the frequency has not changed */
state->step = 4;
state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
} }
state->adc_diff = 3000;
dib0090_write_reg(state, 0x10, 0x2B1); state->current_rf = state->rf_request;
state->current_standard = state->fe->dtv_property_cache.delivery_system;
dib0090_write_reg(state, 0x1e, 0x0032);
ret = 20; ret = 20;
*tune_state = CT_TUNER_STEP_1; state->calibrate = CAPTRIM_CAL; /* captrim serach now */
} else if (*tune_state == CT_TUNER_STEP_0) { }
/* nothing */
} else if (*tune_state == CT_TUNER_STEP_1) {
state->step /= 2;
dib0090_write_reg(state, 0x18, lo4 | state->captrim);
*tune_state = CT_TUNER_STEP_2;
} else if (*tune_state == CT_TUNER_STEP_2) {
adc = dib0090_read_reg(state, 0x1d);
dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc,
(u32) (adc) * (u32) 1800 / (u32) 1024);
if (adc >= 400) {
adc -= 400;
step_sign = -1;
} else {
adc = 400 - adc;
step_sign = 1;
}
if (adc < state->adc_diff) { else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff); const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
state->adc_diff = adc;
state->fcaptrim = state->captrim;
} // if(!state->identity.p1g) {
while (state->current_rf / 1000 > wbd->max_freq)
wbd++;
// }
state->captrim += step_sign * state->step; dib0090_write_reg(state, 0x1e, 0x07ff);
if (state->step >= 1) dprintk("Final Captrim: %d", (u32) state->fcaptrim);
*tune_state = CT_TUNER_STEP_1; dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
else dprintk("VCO = %d", (u32) pll->vco_band);
*tune_state = CT_TUNER_STEP_3; dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
(u32) dib0090_read_reg(state, 0x1c) & 0x3);
ret = 15; #define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
} else if (*tune_state == CT_TUNER_STEP_3) { c = 4;
/*write the final cptrim config */ i = 3; //wbdmux_bias
dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY if (wbd->wbd_gain != 0) //&& !state->identity.p1g)
state->memory[state->memory_index].cap = state->fcaptrim; c = wbd->wbd_gain;
#endif
*tune_state = CT_TUNER_STEP_4; //Store wideband mux register.
} else if (*tune_state == CT_TUNER_STEP_4) { state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
dib0090_write_reg(state, 0x1e, 0x07ff); dib0090_write_reg(state, 0x10, state->wbdmux);
dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim); if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code); dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band); dib0090_write_reg(state, 0x09, tune->lna_bias);
dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf); dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz); } else
dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17)); dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
(u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
c = 4;
i = 3;
#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
c = 2;
i = 2;
}
#endif
dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
#ifdef CONFIG_DIB0090_USE_PWM_AGC
| (state->config->use_pwm_agc << 1)
#endif
));
dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
dib0090_write_reg(state, 0x0c, tune->v2i); dib0090_write_reg(state, 0x0c, tune->v2i);
dib0090_write_reg(state, 0x0d, tune->mix); dib0090_write_reg(state, 0x0d, tune->mix);
dib0090_write_reg(state, 0x0e, tune->load); dib0090_write_reg(state, 0x0e, tune->load);
*tune_state = CT_TUNER_STEP_1;
*tune_state = CT_TUNER_STEP_5; } else if (*tune_state == CT_TUNER_STEP_1) {
} else if (*tune_state == CT_TUNER_STEP_5) {
/* initialize the lt gain register */ /* initialize the lt gain register */
state->rf_lt_def = 0x7c00; state->rf_lt_def = 0x7c00;
dib0090_write_reg(state, 0x0f, state->rf_lt_def); // dib0090_write_reg(state, 0x0f, state->rf_lt_def);
dib0090_set_bandwidth(state); dib0090_set_bandwidth(state);
state->tuner_is_tuned = 1; state->tuner_is_tuned = 1;
// if(!state->identity.p1g)
state->calibrate |= WBD_CAL; // TODO: only do the WBD calibration for new tune
//
state->calibrate |= TEMP_CAL; // Force the Temperature to be remesured at next TUNE.
*tune_state = CT_TUNER_STOP; *tune_state = CT_TUNER_STOP;
} else } else
ret = FE_CALLBACK_TIME_NEVER; ret = FE_CALLBACK_TIME_NEVER;
...@@ -1440,6 +2363,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe) ...@@ -1440,6 +2363,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
return state->tune_state; return state->tune_state;
} }
EXPORT_SYMBOL(dib0090_get_tune_state); EXPORT_SYMBOL(dib0090_get_tune_state);
int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
...@@ -1449,6 +2373,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun ...@@ -1449,6 +2373,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
state->tune_state = tune_state; state->tune_state = tune_state;
return 0; return 0;
} }
EXPORT_SYMBOL(dib0090_set_tune_state); EXPORT_SYMBOL(dib0090_set_tune_state);
static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
...@@ -1462,7 +2387,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) ...@@ -1462,7 +2387,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
{ {
struct dib0090_state *state = fe->tuner_priv; struct dib0090_state *state = fe->tuner_priv;
uint32_t ret; u32 ret;
state->tune_state = CT_TUNER_START; state->tune_state = CT_TUNER_START;
...@@ -1492,6 +2417,29 @@ static const struct dvb_tuner_ops dib0090_ops = { ...@@ -1492,6 +2417,29 @@ static const struct dvb_tuner_ops dib0090_ops = {
.get_frequency = dib0090_get_frequency, .get_frequency = dib0090_get_frequency,
}; };
static const struct dvb_tuner_ops dib0090_fw_ops = {
.info = {
.name = "DiBcom DiB0090",
.frequency_min = 45000000,
.frequency_max = 860000000,
.frequency_step = 1000,
},
.release = dib0090_release,
.init = NULL,
.sleep = NULL,
.set_params = NULL,
.get_frequency = NULL,
};
static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
{470, 0, 250, 0, 100, 4},
{860, 51, 866, 21, 375, 4},
{1700, 0, 800, 0, 850, 4}, //LBAND Predefinition , to calibrate
{2900, 0, 250, 0, 100, 6}, //SBAND Predefinition , NOT tested Yet
{0xFFFF, 0, 0, 0, 0, 0},
};
struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
{ {
struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL); struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
...@@ -1503,6 +2451,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte ...@@ -1503,6 +2451,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
st->fe = fe; st->fe = fe;
fe->tuner_priv = st; fe->tuner_priv = st;
if (config->wbd == NULL)
st->current_wbd_table = dib0090_wbd_table_default;
else
st->current_wbd_table = config->wbd;
if (dib0090_reset(fe) != 0) if (dib0090_reset(fe) != 0)
goto free_mem; goto free_mem;
...@@ -1515,8 +2468,35 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte ...@@ -1515,8 +2468,35 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
fe->tuner_priv = NULL; fe->tuner_priv = NULL;
return NULL; return NULL;
} }
EXPORT_SYMBOL(dib0090_register); EXPORT_SYMBOL(dib0090_register);
struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
{
struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
if (st == NULL)
return NULL;
st->config = config;
st->i2c = i2c;
st->fe = fe;
fe->tuner_priv = st;
if (dib0090_fw_reset_digital(fe, st->config) != 0)
goto free_mem;
dprintk("DiB0090 FW: successfully identified");
memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
return fe;
free_mem:
kfree(st);
fe->tuner_priv = NULL;
return NULL;
}
EXPORT_SYMBOL(dib0090_fw_register);
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>"); MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner"); MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
......
drivers/media/dvb/frontends/dib0090.h
View file @ 28fafca7
...@@ -27,6 +27,21 @@ struct dib0090_io_config { ...@@ -27,6 +27,21 @@ struct dib0090_io_config {
u16 pll_int_loop_filt; u16 pll_int_loop_filt;
}; };
struct dib0090_wbd_slope {
u16 max_freq; /* for every frequency less than or equal to that field: this information is correct */
u16 slope_cold;
u16 offset_cold;
u16 slope_hot;
u16 offset_hot;
u8 wbd_gain;
};
struct dib0090_low_if_offset_table {
int std;
u32 RF_freq;
s32 offset_khz;
};
struct dib0090_config { struct dib0090_config {
struct dib0090_io_config io; struct dib0090_io_config io;
int (*reset) (struct dvb_frontend *, int); int (*reset) (struct dvb_frontend *, int);
...@@ -47,10 +62,20 @@ struct dib0090_config { ...@@ -47,10 +62,20 @@ struct dib0090_config {
u16 wbd_cband_offset; u16 wbd_cband_offset;
u8 use_pwm_agc; u8 use_pwm_agc;
u8 clkoutdrive; u8 clkoutdrive;
u8 ls_cfg_pad_drv;
u8 data_tx_drv;
u8 in_soc;
const struct dib0090_low_if_offset_table *low_if;
u8 fref_clock_ratio;
u16 force_cband_input;
struct dib0090_wbd_slope *wbd;
}; };
#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE)) #if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config); extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast); extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe); extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner); extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
...@@ -65,6 +90,12 @@ static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, str ...@@ -65,6 +90,12 @@ static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, str
return NULL; return NULL;
} }
static inline struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast) static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
{ {
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
......
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