Commit 29ed1973 authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Just a few bug fixes for 4.9.  The big one is Mario's prime fencing fix.

* 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu:fix vpost_needed routine
  drm/amdgpu/powerplay: drop a redundant NULL check
  drm/amdgpu: Attach exclusive fence to prime exported bo's. (v5)
parents 51a4c38a 1da2c326
...@@ -459,6 +459,7 @@ struct amdgpu_bo { ...@@ -459,6 +459,7 @@ struct amdgpu_bo {
u64 metadata_flags; u64 metadata_flags;
void *metadata; void *metadata;
u32 metadata_size; u32 metadata_size;
unsigned prime_shared_count;
/* list of all virtual address to which this bo /* list of all virtual address to which this bo
* is associated to * is associated to
*/ */
......
...@@ -132,7 +132,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, ...@@ -132,7 +132,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev,
entry->priority = min(info[i].bo_priority, entry->priority = min(info[i].bo_priority,
AMDGPU_BO_LIST_MAX_PRIORITY); AMDGPU_BO_LIST_MAX_PRIORITY);
entry->tv.bo = &entry->robj->tbo; entry->tv.bo = &entry->robj->tbo;
entry->tv.shared = true; entry->tv.shared = !entry->robj->prime_shared_count;
if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS) if (entry->robj->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
gds_obj = entry->robj; gds_obj = entry->robj;
......
...@@ -658,12 +658,10 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) ...@@ -658,12 +658,10 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
return false; return false;
if (amdgpu_passthrough(adev)) { if (amdgpu_passthrough(adev)) {
/* for FIJI: In whole GPU pass-through virtualization case /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
* old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH) * some old smc fw still need driver do vPost otherwise gpu hang, while
* so amdgpu_card_posted return false and driver will incorrectly skip vPost. * those smc fw version above 22.15 doesn't have this flaw, so we force
* but if we force vPost do in pass-through case, the driver reload will hang. * vpost executed for smc version below 22.15
* whether doing vPost depends on amdgpu_card_posted if smc version is above
* 00160e00 for FIJI.
*/ */
if (adev->asic_type == CHIP_FIJI) { if (adev->asic_type == CHIP_FIJI) {
int err; int err;
...@@ -674,22 +672,11 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev) ...@@ -674,22 +672,11 @@ static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
return true; return true;
fw_ver = *((uint32_t *)adev->pm.fw->data + 69); fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
if (fw_ver >= 0x00160e00) if (fw_ver < 0x00160e00)
return !amdgpu_card_posted(adev); return true;
} }
} else {
/* in bare-metal case, amdgpu_card_posted return false
* after system reboot/boot, and return true if driver
* reloaded.
* we shouldn't do vPost after driver reload otherwise GPU
* could hang.
*/
if (amdgpu_card_posted(adev))
return false;
} }
return !amdgpu_card_posted(adev);
/* we assume vPost is neede for all other cases */
return true;
} }
/** /**
......
...@@ -74,20 +74,36 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, ...@@ -74,20 +74,36 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
if (ret) if (ret)
return ERR_PTR(ret); return ERR_PTR(ret);
bo->prime_shared_count = 1;
return &bo->gem_base; return &bo->gem_base;
} }
int amdgpu_gem_prime_pin(struct drm_gem_object *obj) int amdgpu_gem_prime_pin(struct drm_gem_object *obj)
{ {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
int ret = 0; long ret = 0;
ret = amdgpu_bo_reserve(bo, false); ret = amdgpu_bo_reserve(bo, false);
if (unlikely(ret != 0)) if (unlikely(ret != 0))
return ret; return ret;
/*
* Wait for all shared fences to complete before we switch to future
* use of exclusive fence on this prime shared bo.
*/
ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
MAX_SCHEDULE_TIMEOUT);
if (unlikely(ret < 0)) {
DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret);
amdgpu_bo_unreserve(bo);
return ret;
}
/* pin buffer into GTT */ /* pin buffer into GTT */
ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
if (likely(ret == 0))
bo->prime_shared_count++;
amdgpu_bo_unreserve(bo); amdgpu_bo_unreserve(bo);
return ret; return ret;
} }
...@@ -102,6 +118,8 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) ...@@ -102,6 +118,8 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
return; return;
amdgpu_bo_unpin(bo); amdgpu_bo_unpin(bo);
if (bo->prime_shared_count)
bo->prime_shared_count--;
amdgpu_bo_unreserve(bo); amdgpu_bo_unreserve(bo);
} }
......
...@@ -1469,8 +1469,6 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) ...@@ -1469,8 +1469,6 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
table_info->vddgfx_lookup_table, vv_id, &sclk)) { table_info->vddgfx_lookup_table, vv_id, &sclk)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ClockStretcher)) { PHM_PlatformCaps_ClockStretcher)) {
if (table_info == NULL)
return -EINVAL;
sclk_table = table_info->vdd_dep_on_sclk; sclk_table = table_info->vdd_dep_on_sclk;
for (j = 1; j < sclk_table->count; j++) { for (j = 1; j < sclk_table->count; j++) {
......
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