Commit 2a114cc1 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter

drm/i915/bdw: Use The GT mailbox for IPS enable/disable

v2: Squash in fixup from Ben to synchronize the GT mailbox commands.

CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: default avatarArt Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 416f4727
...@@ -1805,7 +1805,7 @@ struct drm_i915_file_private { ...@@ -1805,7 +1805,7 @@ struct drm_i915_file_private {
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
#define HAS_IPS(dev) (IS_ULT(dev)) #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
......
...@@ -4953,6 +4953,7 @@ ...@@ -4953,6 +4953,7 @@
#define GEN6_PCODE_WRITE_D_COMP 0x11 #define GEN6_PCODE_WRITE_D_COMP 0x11
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19
#define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_DATA 0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
......
...@@ -3393,15 +3393,26 @@ void hsw_enable_ips(struct intel_crtc *crtc) ...@@ -3393,15 +3393,26 @@ void hsw_enable_ips(struct intel_crtc *crtc)
* only after intel_enable_plane. And intel_enable_plane already waits * only after intel_enable_plane. And intel_enable_plane already waits
* for a vblank, so all we need to do here is to enable the IPS bit. */ * for a vblank, so all we need to do here is to enable the IPS bit. */
assert_plane_enabled(dev_priv, crtc->plane); assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(crtc->base.dev)) {
mutex_lock(&dev_priv->rps.hw_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
mutex_unlock(&dev_priv->rps.hw_lock);
/* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
* mailbox." Therefore we need to defer waiting on the state
* change.
* TODO: need to fix this for state checker
*/
} else {
I915_WRITE(IPS_CTL, IPS_ENABLE); I915_WRITE(IPS_CTL, IPS_ENABLE);
/* The bit only becomes 1 in the next vblank, so this wait here
/* The bit only becomes 1 in the next vblank, so this wait here is * is essentially intel_wait_for_vblank. If we don't have this
* essentially intel_wait_for_vblank. If we don't have this and don't * and don't wait for vblanks until the end of crtc_enable, then
* wait for vblanks until the end of crtc_enable, then the HW state * the HW state readout code will complain that the expected
* readout code will complain that the expected IPS_CTL value is not the * IPS_CTL value is not the one we read. */
* one we read. */
if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
DRM_ERROR("Timed out waiting for IPS enable\n"); DRM_ERROR("Timed out waiting for IPS enable\n");
}
} }
void hsw_disable_ips(struct intel_crtc *crtc) void hsw_disable_ips(struct intel_crtc *crtc)
...@@ -3413,6 +3424,11 @@ void hsw_disable_ips(struct intel_crtc *crtc) ...@@ -3413,6 +3424,11 @@ void hsw_disable_ips(struct intel_crtc *crtc)
return; return;
assert_plane_enabled(dev_priv, crtc->plane); assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(crtc->base.dev)) {
mutex_lock(&dev_priv->rps.hw_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
mutex_unlock(&dev_priv->rps.hw_lock);
} else
I915_WRITE(IPS_CTL, 0); I915_WRITE(IPS_CTL, 0);
POSTING_READ(IPS_CTL); POSTING_READ(IPS_CTL);
......
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