drm/amd/powerplay: enable power containment features for tonga.

v2: fix build error introduced when fix code style problems.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

@@ -4,7 +4,7 @@
 
 HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
 	       hardwaremanager.o pp_acpi.o cz_hwmgr.o \
-               cz_clockpowergating.o \
+               cz_clockpowergating.o tonga_powertune.o\
 	       tonga_processpptables.o ppatomctrl.o \
                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c

@@ -302,6 +302,8 @@ void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_DisableMemoryTransition);
 
+	tonga_initialize_power_tune_defaults(hwmgr);
+
 	data->mclk_strobe_mode_threshold = 40000;
 	data->mclk_stutter_mode_threshold = 30000;
 	data->mclk_edc_enable_threshold = 40000;
@@ -2479,7 +2481,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t
 	graphic_level->VoltageDownHyst = 0;
 	graphic_level->PowerThrottle = 0;
 
-	threshold = engine_clock * data->fast_watemark_threshold / 100;
+	threshold = engine_clock * data->fast_watermark_threshold / 100;
 /*
 	*get the DAL clock. do it in funture.
 	PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
@@ -2982,6 +2984,10 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE(0 == result,
 		"Failed to initialize Boot Level!", return result;);
 
+	result = tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
+	PP_ASSERT_WITH_CODE(result == 0,
+			"Failed to populate BAPM Parameters!", return result);
+
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_ClockStretcher)) {
 		result = tonga_populate_clock_stretcher_data_table(hwmgr);
@@ -4370,6 +4376,10 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 		"Failed to initialize ARB table index!", result = tmp_result);
 
+	tmp_result = tonga_populate_pm_fuses(hwmgr);
+	PP_ASSERT_WITH_CODE((tmp_result == 0),
+			"Failed to populate PM fuses!", result = tmp_result);
+
 	tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 		"Failed to populate initialize MC Reg table!", result = tmp_result);
@@ -4388,6 +4398,18 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 		"Failed to start DPM!", result = tmp_result);
 
+	tmp_result = tonga_enable_smc_cac(hwmgr);
+	PP_ASSERT_WITH_CODE((tmp_result == 0),
+			"Failed to enable SMC CAC!", result = tmp_result);
+
+	tmp_result = tonga_enable_power_containment(hwmgr);
+	PP_ASSERT_WITH_CODE((tmp_result == 0),
+			"Failed to enable power containment!", result = tmp_result);
+
+	tmp_result = tonga_power_control_set_level(hwmgr);
+	PP_ASSERT_WITH_CODE((tmp_result == 0),
+			"Failed to power control set level!", result = tmp_result);
+
 	return result;
 }
 

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h

@@ -300,6 +300,7 @@ struct tonga_hwmgr {
 	bool                         dll_defaule_on;
 	bool                         performance_request_registered;
 
+
 	/* ----------------- Low Power Features ---------------------*/
 	phw_tonga_bacos					bacos;
 	phw_tonga_ulv_parm              ulv;
@@ -314,10 +315,14 @@ struct tonga_hwmgr {
 	bool                         enable_tdc_limit_feature;
 	bool                         enable_pkg_pwr_tracking_feature;
 	bool                         disable_uvd_power_tune_feature;
-	phw_tonga_pt_defaults           *power_tune_defaults;
+	struct tonga_pt_defaults           *power_tune_defaults;
 	SMU72_Discrete_PmFuses           power_tune_table;
-	uint32_t                           ul_dte_tj_offset;             /* Fudge factor in DPM table to correct HW DTE errors */
-	uint32_t                           fast_watemark_threshold;      /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
+	uint32_t                           dte_tj_offset;             /* Fudge factor in DPM table to correct HW DTE errors */
+	uint32_t                           fast_watermark_threshold;      /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
+
+
+	bool                           enable_dte_feature;
+
 
 	/* ----------------- Phase Shedding ---------------------*/
 	bool                         vddc_phase_shed_control;

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.h

@@ -34,21 +34,24 @@ enum _phw_tonga_ptc_config_reg_type {
 };
 typedef enum _phw_tonga_ptc_config_reg_type phw_tonga_ptc_config_reg_type;
 
+/* PowerContainment Features */
+#define POWERCONTAINMENT_FEATURE_DTE             0x00000001
+
+
 /* PowerContainment Features */
 #define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
 #define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
 
-struct _phw_tonga_pt_config_reg {
+struct tonga_pt_config_reg {
 	uint32_t                           Offset;
 	uint32_t                           Mask;
 	uint32_t                           Shift;
 	uint32_t                           Value;
 	phw_tonga_ptc_config_reg_type     Type;
 };
-typedef struct _phw_tonga_pt_config_reg phw_tonga_pt_config_reg;
 
-struct _phw_tonga_pt_defaults {
+struct tonga_pt_defaults {
 	uint8_t   svi_load_line_en;
 	uint8_t   svi_load_line_vddC;
 	uint8_t   tdc_vddc_throttle_release_limit_perc;
@@ -60,7 +63,18 @@ struct _phw_tonga_pt_defaults {
 	uint16_t  bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
 	uint16_t  bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
 };
-typedef struct _phw_tonga_pt_defaults phw_tonga_pt_defaults;
+
+
+
+void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
+int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
+int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr);
+int tonga_enable_smc_cac(struct pp_hwmgr *hwmgr);
+int tonga_disable_smc_cac(struct pp_hwmgr *hwmgr);
+int tonga_enable_power_containment(struct pp_hwmgr *hwmgr);
+int tonga_disable_power_containment(struct pp_hwmgr *hwmgr);
+int tonga_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
+int tonga_power_control_set_level(struct pp_hwmgr *hwmgr);
 
 #endif