Commit 2acdaf59 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver fixes from Stephen Boyd:

 - Fix qcom mux logic to look at the proper parent table member. Luckily
   this clk type isn't very common.

 - Don't kill clks on qcom systems that use Trion PLLs that are enabled
   out of the bootloader. We will simply skip programming the PLL rate
   if it's already done.

 - Use the proper clk_ops for the qcom sm6125 ICE clks.

 - Use module_platform_driver() in i.MX as it can be a module.

 - Fix a UAF in the versatile clk driver on an error path.

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: versatile: clk-icst: use after free on error path
  clk: qcom: sm6125-gcc: Swap ops of ice and apps on sdcc1
  clk: imx: use module_platform_driver
  clk: qcom: clk-alpha-pll: Don't reconfigure running Trion
  clk: qcom: regmap-mux: fix parent clock lookup
parents a84e0b31 2d4fcc5a
...@@ -370,7 +370,7 @@ static struct platform_driver imx8qxp_lpcg_clk_driver = { ...@@ -370,7 +370,7 @@ static struct platform_driver imx8qxp_lpcg_clk_driver = {
.probe = imx8qxp_lpcg_clk_probe, .probe = imx8qxp_lpcg_clk_probe,
}; };
builtin_platform_driver(imx8qxp_lpcg_clk_driver); module_platform_driver(imx8qxp_lpcg_clk_driver);
MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver"); MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
......
...@@ -308,7 +308,7 @@ static struct platform_driver imx8qxp_clk_driver = { ...@@ -308,7 +308,7 @@ static struct platform_driver imx8qxp_clk_driver = {
}, },
.probe = imx8qxp_clk_probe, .probe = imx8qxp_clk_probe,
}; };
builtin_platform_driver(imx8qxp_clk_driver); module_platform_driver(imx8qxp_clk_driver);
MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>"); MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
MODULE_DESCRIPTION("NXP i.MX8QXP clock driver"); MODULE_DESCRIPTION("NXP i.MX8QXP clock driver");
......
...@@ -1429,6 +1429,15 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); ...@@ -1429,6 +1429,15 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config) const struct alpha_pll_config *config)
{ {
/*
* If the bootloader left the PLL enabled it's likely that there are
* RCGs that will lock up if we disable the PLL below.
*/
if (trion_pll_is_enabled(pll, regmap)) {
pr_debug("Trion PLL is already enabled, skipping configuration\n");
return;
}
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
......
...@@ -28,7 +28,7 @@ static u8 mux_get_parent(struct clk_hw *hw) ...@@ -28,7 +28,7 @@ static u8 mux_get_parent(struct clk_hw *hw)
val &= mask; val &= mask;
if (mux->parent_map) if (mux->parent_map)
return qcom_find_src_index(hw, mux->parent_map, val); return qcom_find_cfg_index(hw, mux->parent_map, val);
return val; return val;
} }
......
...@@ -69,6 +69,18 @@ int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src) ...@@ -69,6 +69,18 @@ int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
} }
EXPORT_SYMBOL_GPL(qcom_find_src_index); EXPORT_SYMBOL_GPL(qcom_find_src_index);
int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map, u8 cfg)
{
int i, num_parents = clk_hw_get_num_parents(hw);
for (i = 0; i < num_parents; i++)
if (cfg == map[i].cfg)
return i;
return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_cfg_index);
struct regmap * struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{ {
......
...@@ -49,6 +49,8 @@ extern void ...@@ -49,6 +49,8 @@ extern void
qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count); qcom_pll_set_fsm_mode(struct regmap *m, u32 reg, u8 bias_count, u8 lock_count);
extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
u8 src); u8 src);
extern int qcom_find_cfg_index(struct clk_hw *hw, const struct parent_map *map,
u8 cfg);
extern int qcom_cc_register_board_clk(struct device *dev, const char *path, extern int qcom_cc_register_board_clk(struct device *dev, const char *path,
const char *name, unsigned long rate); const char *name, unsigned long rate);
......
...@@ -1121,7 +1121,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { ...@@ -1121,7 +1121,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.name = "gcc_sdcc1_apps_clk_src", .name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1, .parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1), .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops,
}, },
}; };
...@@ -1143,7 +1143,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { ...@@ -1143,7 +1143,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.name = "gcc_sdcc1_ice_core_clk_src", .name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0, .parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0), .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_ops,
}, },
}; };
......
...@@ -543,8 +543,8 @@ static void __init of_syscon_icst_setup(struct device_node *np) ...@@ -543,8 +543,8 @@ static void __init of_syscon_icst_setup(struct device_node *np)
regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype); regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype);
if (IS_ERR(regclk)) { if (IS_ERR(regclk)) {
kfree(name);
pr_err("error setting up syscon ICST clock %s\n", name); pr_err("error setting up syscon ICST clock %s\n", name);
kfree(name);
return; return;
} }
of_clk_add_provider(np, of_clk_src_simple_get, regclk); of_clk_add_provider(np, of_clk_src_simple_get, regclk);
......
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