Commit 2b9c875c authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

clk: sunxi-ng: mux: Add support for mux tables

Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.

Add support for specifying a mux table to map clock parents to
mux values.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 89af8525
......@@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
parent = reg >> cm->shift;
parent &= (1 << cm->width) - 1;
if (cm->table) {
int num_parents = clk_hw_get_num_parents(&common->hw);
int i;
for (i = 0; i < num_parents; i++)
if (cm->table[i] == parent)
return i;
}
return parent;
}
......@@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
unsigned long flags;
u32 reg;
if (cm->table)
index = cm->table[index];
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
......
......@@ -8,6 +8,7 @@
struct ccu_mux_internal {
u8 shift;
u8 width;
const u8 *table;
struct {
u8 index;
......@@ -21,12 +22,16 @@ struct ccu_mux_internal {
} variable_prediv;
};
#define _SUNXI_CCU_MUX(_shift, _width) \
#define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \
{ \
.shift = _shift, \
.width = _width, \
.table = _table, \
}
#define _SUNXI_CCU_MUX(_shift, _width) \
_SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
struct ccu_mux {
u16 reg;
u32 enable;
......
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