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Commit 2c4f829b authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
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[Blackfin] arch: Merge BF561 support into ints-priority 

Merge single core ints-priority-sc.c and dual core ints-priority-dc.c
into one common code ints-priority.c
Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 856783b3
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Showing with 117 additions and 520 deletions
arch/blackfin/mach-common/Makefile
View file @ 2c4f829b
...@@ -4,8 +4,6 @@ ...@@ -4,8 +4,6 @@
obj-y := \ obj-y := \
cache.o cacheinit.o entry.o \ cache.o cacheinit.o entry.o \
interrupt.o lock.o irqpanic.o arch_checks.o interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o dpmc.o obj-$(CONFIG_PM) += pm.o dpmc.o
arch/blackfin/mach-common/ints-priority-dc.c deleted 100644 → 0
View file @ 856783b3
This diff is collapsed.
arch/blackfin/mach-common/ints-priority-sc.c → arch/blackfin/mach-common/ints-priority.c
View file @ 2c4f829b
...@@ -98,8 +98,7 @@ static void __init search_IAR(void) ...@@ -98,8 +98,7 @@ static void __init search_IAR(void)
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4; int iar_shift = (irqn & 7) * 4;
if (ivg == if (ivg == (0xf &
(0xf &
#ifndef CONFIG_BF52x #ifndef CONFIG_BF52x
bfin_read32((unsigned long *)SIC_IAR0 + bfin_read32((unsigned long *)SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) { (irqn >> 3)) >> iar_shift)) {
...@@ -206,8 +205,7 @@ static void bfin_generic_error_mask_irq(unsigned int irq) ...@@ -206,8 +205,7 @@ static void bfin_generic_error_mask_irq(unsigned int irq)
if (!error_int_mask) { if (!error_int_mask) {
local_irq_disable(); local_irq_disable();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 << ~(1 << (IRQ_GENERIC_ERROR -
(IRQ_GENERIC_ERROR -
(IRQ_CORETMR + 1)))); (IRQ_CORETMR + 1))));
SSYNC(); SSYNC();
local_irq_enable(); local_irq_enable();
...@@ -232,7 +230,7 @@ static struct irq_chip bfin_generic_error_irqchip = { ...@@ -232,7 +230,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
}; };
static void bfin_demux_error_irq(unsigned int int_err_irq, static void bfin_demux_error_irq(unsigned int int_err_irq,
struct irq_desc *intb_desc) struct irq_desc *inta_desc)
{ {
int irq = 0; int irq = 0;
...@@ -446,17 +444,55 @@ static struct irq_chip bfin_gpio_irqchip = { ...@@ -446,17 +444,55 @@ static struct irq_chip bfin_gpio_irqchip = {
.shutdown = bfin_gpio_irq_shutdown .shutdown = bfin_gpio_irq_shutdown
}; };
static void bfin_demux_gpio_irq(unsigned int intb_irq, static void bfin_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *intb_desc) struct irq_desc *desc)
{ {
u16 i; unsigned int i, gpio, mask, irq, search = 0;
struct irq_desc *desc;
switch (inta_irq) {
#if defined(CONFIG_BF53x)
case IRQ_PROG_INTA:
irq = IRQ_PF0;
search = 1;
break;
# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
case IRQ_MAC_RX:
irq = IRQ_PH0;
break;
# endif
#elif defined(CONFIG_BF52x)
case IRQ_PORTF_INTA:
irq = IRQ_PF0;
break;
case IRQ_PORTG_INTA:
irq = IRQ_PG0;
break;
case IRQ_PORTH_INTA:
irq = IRQ_PH0;
break;
#elif defined(CONFIG_BF561)
case IRQ_PROG0_INTA:
irq = IRQ_PF0;
break;
case IRQ_PROG1_INTA:
irq = IRQ_PF16;
break;
case IRQ_PROG2_INTA:
irq = IRQ_PF32;
break;
#endif
default:
BUG();
return;
}
if (search) {
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
int irq = IRQ_PF0 + i; irq += i;
int flag_d = get_gpiop_data(i);
int mask = mask = get_gpiop_data(i) &
flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i)); (gpio_enabled[gpio_bank(i)] &
get_gpiop_maska(i));
while (mask) { while (mask) {
if (mask & 1) { if (mask & 1) {
...@@ -467,6 +503,22 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq, ...@@ -467,6 +503,22 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
mask >>= 1; mask >>= 1;
} }
} }
} else {
gpio = irq_to_gpio(irq);
mask = get_gpiop_data(gpio) &
(gpio_enabled[gpio_bank(gpio)] &
get_gpiop_maska(gpio));
do {
if (mask & 1) {
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
irq++;
mask >>= 1;
} while (mask);
}
} }
#else /* CONFIG_BF54x */ #else /* CONFIG_BF54x */
...@@ -721,14 +773,13 @@ static struct irq_chip bfin_gpio_irqchip = { ...@@ -721,14 +773,13 @@ static struct irq_chip bfin_gpio_irqchip = {
.shutdown = bfin_gpio_irq_shutdown .shutdown = bfin_gpio_irq_shutdown
}; };
static void bfin_demux_gpio_irq(unsigned int intb_irq, static void bfin_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *intb_desc) struct irq_desc *desc)
{ {
u8 bank, pint_val; u8 bank, pint_val;
u32 request, irq; u32 request, irq;
struct irq_desc *desc;
switch (intb_irq) { switch (inta_irq) {
case IRQ_PINT0: case IRQ_PINT0:
bank = 0; bank = 0;
break; break;
...@@ -795,7 +846,7 @@ int __init init_arch_irq(void) ...@@ -795,7 +846,7 @@ int __init init_arch_irq(void)
int irq; int irq;
unsigned long ilat = 0; unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */ /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL); bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
...@@ -812,6 +863,8 @@ int __init init_arch_irq(void) ...@@ -812,6 +863,8 @@ int __init init_arch_irq(void)
local_irq_disable(); local_irq_disable();
init_exception_buff();
#ifdef CONFIG_BF54x #ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN # ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN; pint[0]->assign = CONFIG_PINT0_ASSIGN;
...@@ -874,6 +927,19 @@ int __init init_arch_irq(void) ...@@ -874,6 +927,19 @@ int __init init_arch_irq(void)
set_irq_chained_handler(irq, set_irq_chained_handler(irq,
bfin_demux_gpio_irq); bfin_demux_gpio_irq);
break; break;
#elif defined(CONFIG_BF561)
case IRQ_PROG0_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PROG1_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PROG2_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
#endif #endif
default: default:
set_irq_handler(irq, handle_simple_irq); set_irq_handler(irq, handle_simple_irq);
...@@ -893,11 +959,8 @@ int __init init_arch_irq(void) ...@@ -893,11 +959,8 @@ int __init init_arch_irq(void)
} }
#endif #endif
#ifndef CONFIG_BF54x for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
#else
for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
#endif
set_irq_chip(irq, &bfin_gpio_irqchip); set_irq_chip(irq, &bfin_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */ /* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq); set_irq_handler(irq, handle_level_irq);
...@@ -936,7 +999,7 @@ void do_irq(int vec, struct pt_regs *fp) ...@@ -936,7 +999,7 @@ void do_irq(int vec, struct pt_regs *fp)
} else { } else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
unsigned long sic_status[3]; unsigned long sic_status[3];
SSYNC(); SSYNC();
......
include/asm-blackfin/mach-bf561/blackfin.h
View file @ 2c4f829b
...@@ -49,4 +49,24 @@ ...@@ -49,4 +49,24 @@
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() #define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) #define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
#define SIC_IAR0 SICA_IAR0
#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
#endif /* _MACH_BLACKFIN_H_ */ #endif /* _MACH_BLACKFIN_H_ */
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