Commit 2c923414 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto fixes from Herbert Xu:
 "This fixes the following issues:

  API:
   - algif_hash needs to wait for init operations to complete.
   - The has_key setting for shash was always true.

  Algorithms:
   - Add missing selections of CRYPTO_HASH.
   - Fix pkcs7 authentication.

  Drivers:
   - Fix stack alignment bug in chacha20-ssse3.
   - Fix performance regression in caam due to incorrect setting.
   - Fix potential compile-only build failure of stm32"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: atmel-aes - remove calls of clk_prepare() from atomic contexts
  crypto: algif_hash - wait for crypto_ahash_init() to complete
  crypto: shash - Fix has_key setting
  hwrng: stm32 - Fix dependencies for !HAS_IOMEM archs
  crypto: ghash,poly1305 - select CRYPTO_HASH where needed
  crypto: chacha20-ssse3 - Align stack pointer to 64 bytes
  PKCS#7: Don't require SpcSpOpusInfo in Authenticode pkcs7 signatures
  crypto: caam - make write transactions bufferable on PPC platforms
parents 29a8ea4f 49a20454
...@@ -157,7 +157,9 @@ ENTRY(chacha20_4block_xor_ssse3) ...@@ -157,7 +157,9 @@ ENTRY(chacha20_4block_xor_ssse3)
# done with the slightly better performing SSSE3 byte shuffling, # done with the slightly better performing SSSE3 byte shuffling,
# 7/12-bit word rotation uses traditional shift+OR. # 7/12-bit word rotation uses traditional shift+OR.
sub $0x40,%rsp mov %rsp,%r11
sub $0x80,%rsp
and $~63,%rsp
# x0..15[0-3] = s0..3[0..3] # x0..15[0-3] = s0..3[0..3]
movq 0x00(%rdi),%xmm1 movq 0x00(%rdi),%xmm1
...@@ -620,6 +622,6 @@ ENTRY(chacha20_4block_xor_ssse3) ...@@ -620,6 +622,6 @@ ENTRY(chacha20_4block_xor_ssse3)
pxor %xmm1,%xmm15 pxor %xmm1,%xmm15
movdqu %xmm15,0xf0(%rsi) movdqu %xmm15,0xf0(%rsi)
add $0x40,%rsp mov %r11,%rsp
ret ret
ENDPROC(chacha20_4block_xor_ssse3) ENDPROC(chacha20_4block_xor_ssse3)
...@@ -472,11 +472,13 @@ config CRYPTO_CRCT10DIF_PCLMUL ...@@ -472,11 +472,13 @@ config CRYPTO_CRCT10DIF_PCLMUL
config CRYPTO_GHASH config CRYPTO_GHASH
tristate "GHASH digest algorithm" tristate "GHASH digest algorithm"
select CRYPTO_GF128MUL select CRYPTO_GF128MUL
select CRYPTO_HASH
help help
GHASH is message digest algorithm for GCM (Galois/Counter Mode). GHASH is message digest algorithm for GCM (Galois/Counter Mode).
config CRYPTO_POLY1305 config CRYPTO_POLY1305
tristate "Poly1305 authenticator algorithm" tristate "Poly1305 authenticator algorithm"
select CRYPTO_HASH
help help
Poly1305 authenticator algorithm, RFC7539. Poly1305 authenticator algorithm, RFC7539.
......
...@@ -54,7 +54,8 @@ static int hash_sendmsg(struct socket *sock, struct msghdr *msg, ...@@ -54,7 +54,8 @@ static int hash_sendmsg(struct socket *sock, struct msghdr *msg,
lock_sock(sk); lock_sock(sk);
if (!ctx->more) { if (!ctx->more) {
err = crypto_ahash_init(&ctx->req); err = af_alg_wait_for_completion(crypto_ahash_init(&ctx->req),
&ctx->completion);
if (err) if (err)
goto unlock; goto unlock;
} }
...@@ -125,6 +126,7 @@ static ssize_t hash_sendpage(struct socket *sock, struct page *page, ...@@ -125,6 +126,7 @@ static ssize_t hash_sendpage(struct socket *sock, struct page *page,
} else { } else {
if (!ctx->more) { if (!ctx->more) {
err = crypto_ahash_init(&ctx->req); err = crypto_ahash_init(&ctx->req);
err = af_alg_wait_for_completion(err, &ctx->completion);
if (err) if (err)
goto unlock; goto unlock;
} }
......
...@@ -547,9 +547,7 @@ int pkcs7_sig_note_set_of_authattrs(void *context, size_t hdrlen, ...@@ -547,9 +547,7 @@ int pkcs7_sig_note_set_of_authattrs(void *context, size_t hdrlen,
struct pkcs7_signed_info *sinfo = ctx->sinfo; struct pkcs7_signed_info *sinfo = ctx->sinfo;
if (!test_bit(sinfo_has_content_type, &sinfo->aa_set) || if (!test_bit(sinfo_has_content_type, &sinfo->aa_set) ||
!test_bit(sinfo_has_message_digest, &sinfo->aa_set) || !test_bit(sinfo_has_message_digest, &sinfo->aa_set)) {
(ctx->msg->data_type == OID_msIndirectData &&
!test_bit(sinfo_has_ms_opus_info, &sinfo->aa_set))) {
pr_warn("Missing required AuthAttr\n"); pr_warn("Missing required AuthAttr\n");
return -EBADMSG; return -EBADMSG;
} }
......
...@@ -354,11 +354,10 @@ int crypto_init_shash_ops_async(struct crypto_tfm *tfm) ...@@ -354,11 +354,10 @@ int crypto_init_shash_ops_async(struct crypto_tfm *tfm)
crt->final = shash_async_final; crt->final = shash_async_final;
crt->finup = shash_async_finup; crt->finup = shash_async_finup;
crt->digest = shash_async_digest; crt->digest = shash_async_digest;
if (alg->setkey) {
crt->setkey = shash_async_setkey; crt->setkey = shash_async_setkey;
crt->has_setkey = true;
} crt->has_setkey = alg->setkey != shash_no_setkey;
if (alg->export) if (alg->export)
crt->export = shash_async_export; crt->export = shash_async_export;
if (alg->import) if (alg->import)
......
...@@ -372,6 +372,7 @@ config HW_RANDOM_XGENE ...@@ -372,6 +372,7 @@ config HW_RANDOM_XGENE
config HW_RANDOM_STM32 config HW_RANDOM_STM32
tristate "STMicroelectronics STM32 random number generator" tristate "STMicroelectronics STM32 random number generator"
depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST) depends on HW_RANDOM && (ARCH_STM32 || COMPILE_TEST)
depends on HAS_IOMEM
help help
This driver provides kernel-side support for the Random Number This driver provides kernel-side support for the Random Number
Generator hardware found on STM32 microcontrollers. Generator hardware found on STM32 microcontrollers.
......
...@@ -400,7 +400,7 @@ static int atmel_aes_hw_init(struct atmel_aes_dev *dd) ...@@ -400,7 +400,7 @@ static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
{ {
int err; int err;
err = clk_prepare_enable(dd->iclk); err = clk_enable(dd->iclk);
if (err) if (err)
return err; return err;
...@@ -430,7 +430,7 @@ static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd) ...@@ -430,7 +430,7 @@ static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
dev_info(dd->dev, "version: 0x%x\n", dd->hw_version); dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
clk_disable_unprepare(dd->iclk); clk_disable(dd->iclk);
return 0; return 0;
} }
...@@ -448,7 +448,7 @@ static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd) ...@@ -448,7 +448,7 @@ static inline bool atmel_aes_is_encrypt(const struct atmel_aes_dev *dd)
static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err) static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
{ {
clk_disable_unprepare(dd->iclk); clk_disable(dd->iclk);
dd->flags &= ~AES_FLAGS_BUSY; dd->flags &= ~AES_FLAGS_BUSY;
if (dd->is_async) if (dd->is_async)
...@@ -2091,10 +2091,14 @@ static int atmel_aes_probe(struct platform_device *pdev) ...@@ -2091,10 +2091,14 @@ static int atmel_aes_probe(struct platform_device *pdev)
goto res_err; goto res_err;
} }
err = atmel_aes_hw_version_init(aes_dd); err = clk_prepare(aes_dd->iclk);
if (err) if (err)
goto res_err; goto res_err;
err = atmel_aes_hw_version_init(aes_dd);
if (err)
goto iclk_unprepare;
atmel_aes_get_cap(aes_dd); atmel_aes_get_cap(aes_dd);
err = atmel_aes_buff_init(aes_dd); err = atmel_aes_buff_init(aes_dd);
...@@ -2127,6 +2131,8 @@ static int atmel_aes_probe(struct platform_device *pdev) ...@@ -2127,6 +2131,8 @@ static int atmel_aes_probe(struct platform_device *pdev)
err_aes_dma: err_aes_dma:
atmel_aes_buff_cleanup(aes_dd); atmel_aes_buff_cleanup(aes_dd);
err_aes_buff: err_aes_buff:
iclk_unprepare:
clk_unprepare(aes_dd->iclk);
res_err: res_err:
tasklet_kill(&aes_dd->done_task); tasklet_kill(&aes_dd->done_task);
tasklet_kill(&aes_dd->queue_task); tasklet_kill(&aes_dd->queue_task);
...@@ -2155,6 +2161,8 @@ static int atmel_aes_remove(struct platform_device *pdev) ...@@ -2155,6 +2161,8 @@ static int atmel_aes_remove(struct platform_device *pdev)
atmel_aes_dma_cleanup(aes_dd); atmel_aes_dma_cleanup(aes_dd);
atmel_aes_buff_cleanup(aes_dd); atmel_aes_buff_cleanup(aes_dd);
clk_unprepare(aes_dd->iclk);
return 0; return 0;
} }
......
...@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev) ...@@ -534,8 +534,8 @@ static int caam_probe(struct platform_device *pdev)
* long pointers in master configuration register * long pointers in master configuration register
*/ */
clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE |
MCFGR_LONG_PTR : 0)); (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
/* /*
* Read the Compile Time paramters and SCFGR to determine * Read the Compile Time paramters and SCFGR to determine
......
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