Commit 2ccf80b7 authored by Valentin Longchamp's avatar Valentin Longchamp Committed by Scott Wood

soc/fsl/qe: round brg_freq to 1kHz granularity

Because of integer computation rounding in u-boot (that sets the QE
brg-frequency DTS prop), the clk value is 99999999 Hz even though it is
100 MHz.

When setting brg clks that are exact divisors of 100 MHz, this small
differnce plays a role and can result in lower clks to be output (for
instance 20 MHz - divide by 5 - results in 16.666 MHz - divide by 6).

This patch fixes that by "forcing" the brg_clk to the nearest kHz when
the difference is below 2 integer rounding errors (i.e. 4).
Signed-off-by: default avatarValentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent b54ea82f
...@@ -161,11 +161,15 @@ EXPORT_SYMBOL(qe_issue_cmd); ...@@ -161,11 +161,15 @@ EXPORT_SYMBOL(qe_issue_cmd);
*/ */
static unsigned int brg_clk = 0; static unsigned int brg_clk = 0;
#define CLK_GRAN (1000)
#define CLK_GRAN_LIMIT (5)
unsigned int qe_get_brg_clk(void) unsigned int qe_get_brg_clk(void)
{ {
struct device_node *qe; struct device_node *qe;
int size; int size;
const u32 *prop; const u32 *prop;
unsigned int mod;
if (brg_clk) if (brg_clk)
return brg_clk; return brg_clk;
...@@ -183,6 +187,15 @@ unsigned int qe_get_brg_clk(void) ...@@ -183,6 +187,15 @@ unsigned int qe_get_brg_clk(void)
of_node_put(qe); of_node_put(qe);
/* round this if near to a multiple of CLK_GRAN */
mod = brg_clk % CLK_GRAN;
if (mod) {
if (mod < CLK_GRAN_LIMIT)
brg_clk -= mod;
else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
brg_clk += CLK_GRAN - mod;
}
return brg_clk; return brg_clk;
} }
EXPORT_SYMBOL(qe_get_brg_clk); EXPORT_SYMBOL(qe_get_brg_clk);
......
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