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Commit 2d2da475 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'm68knommu-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu updates from Greg Ungerer:
 "A collection of changes to add elf-fdpic loader support for m68k.

  Also a collection of various fixes. They include typo corrections,
  undefined symbol compilation fixes, removal of the ISA_DMA_API support
  and removal of unused code.

  Summary:

   - correctly set up ZERO_PAGE pointer

   - drop ISA_DMA_API support

   - fix comment typos

   - fixes for undefined symbols

   - remove unused code and variables

   - elf-fdpic loader support for m68k"

* tag 'm68knommu-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: fix 68000 CPU link with no platform selected
  m68k: removed unused "mach_get_ss"
  m68knommu: fix undefined reference to `mach_get_rtc_pll'
  m68knommu: fix undefined reference to `_init_sp'
  m68knommu: allow elf_fdpic loader to be selected
  m68knommu: add definitions to support elf_fdpic program loader
  m68knommu: implement minimal regset support
  m68knommu: use asm-generic/mmu.h for nommu setups
  m68k: fix typos in comments
  m68k: coldfire: drop ISA_DMA_API support
  m68knommu: set ZERO_PAGE() to the allocated zeroed page
parents b00ed48b 6b8be804
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arch/m68k/Kconfig.bus
View file @ 2d2da475
...@@ -56,16 +56,6 @@ config ATARI_ROM_ISA ...@@ -56,16 +56,6 @@ config ATARI_ROM_ISA
The only driver currently using this adapter is the EtherNEC The only driver currently using this adapter is the EtherNEC
driver for RTL8019AS based NE2000 compatible network cards. driver for RTL8019AS based NE2000 compatible network cards.
config GENERIC_ISA_DMA
def_bool ISA
source "drivers/zorro/Kconfig" source "drivers/zorro/Kconfig"
endif endif
if COLDFIRE
config ISA_DMA_API
def_bool !M5272
endif
arch/m68k/Kconfig.cpu
View file @ 2d2da475
...@@ -37,7 +37,7 @@ endchoice ...@@ -37,7 +37,7 @@ endchoice
if M68KCLASSIC if M68KCLASSIC
config M68000 config M68000
bool def_bool y
depends on !MMU depends on !MMU
select CPU_HAS_NO_BITFIELDS select CPU_HAS_NO_BITFIELDS
select CPU_HAS_NO_CAS select CPU_HAS_NO_CAS
......
arch/m68k/Kconfig.machine
View file @ 2d2da475
...@@ -352,6 +352,7 @@ comment "Machine Options" ...@@ -352,6 +352,7 @@ comment "Machine Options"
config UBOOT config UBOOT
bool "Support for U-Boot command line parameters" bool "Support for U-Boot command line parameters"
depends on COLDFIRE
help help
If you say Y here kernel will try to collect command If you say Y here kernel will try to collect command
line parameters from the initial u-boot stack. line parameters from the initial u-boot stack.
......
arch/m68k/coldfire/Makefile
View file @ 2d2da475
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o dma.o entry.o vectors.o obj-$(CONFIG_COLDFIRE) += cache.o clk.o device.o entry.o vectors.o
obj-$(CONFIG_M5206) += m5206.o intc.o reset.o obj-$(CONFIG_M5206) += m5206.o intc.o reset.o
obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o obj-$(CONFIG_M5206e) += m5206.o intc.o reset.o
obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o obj-$(CONFIG_M520x) += m520x.o intc-simr.o reset.o
......
arch/m68k/coldfire/dma.c deleted 100644 → 0
View file @ b00ed48b
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* dma.c -- Freescale ColdFire DMA support
*
* Copyright (C) 2007, Greg Ungerer (gerg@snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/dma.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
/***************************************************************************/
/*
* DMA channel base address table.
*/
unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
#ifdef MCFDMA_BASE0
MCFDMA_BASE0,
#endif
#ifdef MCFDMA_BASE1
MCFDMA_BASE1,
#endif
#ifdef MCFDMA_BASE2
MCFDMA_BASE2,
#endif
#ifdef MCFDMA_BASE3
MCFDMA_BASE3,
#endif
};
EXPORT_SYMBOL(dma_base_addr);
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
EXPORT_SYMBOL(dma_device_address);
/***************************************************************************/
arch/m68k/coldfire/intc.c
View file @ 2d2da475
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
unsigned char mcf_irq2imr[NR_IRQS]; unsigned char mcf_irq2imr[NR_IRQS];
/* /*
* Define the miniumun and maximum external interrupt numbers. * Define the minimum and maximum external interrupt numbers.
* This is also used as the "level" interrupt numbers. * This is also used as the "level" interrupt numbers.
*/ */
#define EIRQ1 25 #define EIRQ1 25
......
arch/m68k/coldfire/m53xx.c
View file @ 2d2da475
...@@ -532,7 +532,7 @@ int clock_pll(int fsys, int flags) ...@@ -532,7 +532,7 @@ int clock_pll(int fsys, int flags)
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE, writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR); MCF_SDRAMC_SDCR);
/* Errata - workaround for SDRAM opeartion after exiting LIMP mode */ /* Errata - workaround for SDRAM operation after exiting LIMP mode */
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX); writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
/* wait for DQS logic to relock */ /* wait for DQS logic to relock */
......
arch/m68k/coldfire/pci.c
View file @ 2d2da475
...@@ -31,7 +31,7 @@ static struct pci_bus *rootbus; ...@@ -31,7 +31,7 @@ static struct pci_bus *rootbus;
static unsigned long iospace; static unsigned long iospace;
/* /*
* We need to be carefull probing on bus 0 (directly connected to host * We need to be careful probing on bus 0 (directly connected to host
* bridge). We should only access the well defined possible devices in * bridge). We should only access the well defined possible devices in
* use, ignore aliases and the like. * use, ignore aliases and the like.
*/ */
......
arch/m68k/hp300/config.c
View file @ 2d2da475
...@@ -240,12 +240,6 @@ static int hp300_hwclk(int op, struct rtc_time *t) ...@@ -240,12 +240,6 @@ static int hp300_hwclk(int op, struct rtc_time *t)
return 0; return 0;
} }
static unsigned int hp300_get_ss(void)
{
return hp300_rtc_read(RTC_REG_SEC1) * 10 +
hp300_rtc_read(RTC_REG_SEC2);
}
static void __init hp300_init_IRQ(void) static void __init hp300_init_IRQ(void)
{ {
} }
...@@ -256,7 +250,6 @@ void __init config_hp300(void) ...@@ -256,7 +250,6 @@ void __init config_hp300(void)
mach_init_IRQ = hp300_init_IRQ; mach_init_IRQ = hp300_init_IRQ;
mach_get_model = hp300_get_model; mach_get_model = hp300_get_model;
mach_hwclk = hp300_hwclk; mach_hwclk = hp300_hwclk;
mach_get_ss = hp300_get_ss;
mach_reset = hp300_reset; mach_reset = hp300_reset;
#ifdef CONFIG_HEARTBEAT #ifdef CONFIG_HEARTBEAT
mach_heartbeat = hp300_pulse; mach_heartbeat = hp300_pulse;
......
arch/m68k/include/asm/dma.h
View file @ 2d2da475
...@@ -2,493 +2,10 @@ ...@@ -2,493 +2,10 @@
#ifndef _M68K_DMA_H #ifndef _M68K_DMA_H
#define _M68K_DMA_H 1 #define _M68K_DMA_H 1
#ifdef CONFIG_COLDFIRE
/*
* ColdFire DMA Model:
* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
* address mode emits a source address, and expects that the device will either
* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
* the device will place data on the correct byte(s) of the data bus, as the
* memory transactions are always 32 bits. This implies that only 32 bit
* devices will find single mode transfers useful. Dual address DMA mode
* performs two cycles: source read and destination write. ColdFire will
* align the data so that the device will always get the correct bytes, thus
* is useful for 8 and 16 bit devices. This is the mode that is supported
* below.
*
* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
*
* APR/18/2002 : added proper support for MCF5272 DMA controller.
* Arthur Shipkowski (art@videon-central.com)
*/
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
/*
* Set number of channels of DMA on ColdFire for different implementations.
*/
#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
defined(CONFIG_M528x) || defined(CONFIG_M525x)
#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M53xx)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2
#endif
extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
#if !defined(CONFIG_M5272)
#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ 0
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE 1
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD 2
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD 3
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG 4
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG 5
/* I/O to memory, 8 bits, single-address-mode */
#define DMA_MODE_READ_SINGLE 8
/* memory to I/O, 8 bits, single-address-mode */
#define DMA_MODE_WRITE_SINGLE 9
/* I/O to memory, 16 bits, single-address-mode */
#define DMA_MODE_READ_WORD_SINGLE 10
/* memory to I/O, 16 bits, single-address-mode */
#define DMA_MODE_WRITE_WORD_SINGLE 11
/* I/O to memory, 32 bits, single-address-mode */
#define DMA_MODE_READ_LONG_SINGLE 12
/* memory to I/O, 32 bits, single-address-mode */
#define DMA_MODE_WRITE_LONG_SINGLE 13
#else /* CONFIG_M5272 is defined */
/* Source static-address mode */
#define DMA_MODE_SRC_SA_BIT 0x01
/* Two bits to select between all four modes */
#define DMA_MODE_SSIZE_MASK 0x06
/* Offset to shift bits in */
#define DMA_MODE_SSIZE_OFF 0x01
/* Destination static-address mode */
#define DMA_MODE_DES_SA_BIT 0x10
/* Two bits to select between all four modes */
#define DMA_MODE_DSIZE_MASK 0x60
/* Offset to shift bits in */
#define DMA_MODE_DSIZE_OFF 0x05
/* Size modifiers */
#define DMA_MODE_SIZE_LONG 0x00
#define DMA_MODE_SIZE_BYTE 0x01
#define DMA_MODE_SIZE_WORD 0x02
#define DMA_MODE_SIZE_LINE 0x03
/*
* Aliases to help speed quick ports; these may be suboptimal, however. They
* do not include the SINGLE mode modifiers since the MCF5272 does not have a
* mode where the device is in control of its addressing.
*/
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
/* I/O to memory, 32 bits, mode */
#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
/* memory to I/O, 32 bits, mode */
#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
#endif /* !defined(CONFIG_M5272) */
#if !defined(CONFIG_M5272)
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
volatile unsigned char *dmapb;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmapb = (unsigned char *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned char *dmabp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmabp = (unsigned char *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
/* Clear config errors */
dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
/* Set command register */
dmawp[MCFDMA_DCR] =
MCFDMA_DCR_INT | /* Enable completion irq */
MCFDMA_DCR_CS | /* Force one xfer per request */
MCFDMA_DCR_AA | /* Enable auto alignment */
/* single-address-mode */
((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
/* sets s_rw (-> r/w) high if Memory to I/0 */
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
/* Memory to I/O or I/O to Memory */
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
/* 32 bit, 16 bit or 8 bit transfers */
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
MCFDMA_DCR_SSIZE_BYTE)) |
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
MCFDMA_DCR_DSIZE_BYTE));
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
(int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned short *dmawp;
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Determine which address registers are used for memory/device accesses */
if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
/* Source incrementing, must be memory */
dmalp[MCFDMA_SAR] = a;
/* Set dest address, must be device */
dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
} else {
/* Destination incrementing, must be memory */
dmalp[MCFDMA_DAR] = a;
/* Set source address, must be device */
dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
(int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
(int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_BCR] = (unsigned short)count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned short *dmawp;
unsigned short count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmawp = (unsigned short *) dma_base_addr[dmanr];
count = dmawp[MCFDMA_BCR];
return((int) count);
}
#else /* CONFIG_M5272 is defined */
/*
* The MCF5272 DMA controller is very different than the controller defined above
* in terms of register mapping. For instance, with the exception of the 16-bit
* interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
*
* The big difference, however, is the lack of device-requested DMA. All modes
* are dual address transfer, and there is no 'device' setup or direction bit.
* You can DMA between a device and memory, between memory and memory, or even between
* two devices directly, with any combination of incrementing and non-incrementing
* addresses you choose. This puts a crimp in distinguishing between the 'device
* address' set up by set_dma_device_addr.
*
* Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
* which will act exactly as above in -- it will look to see if the source is set to
* autoincrement, and if so it will make the source use the set_dma_addr value and the
* destination the set_dma_device_addr value. Otherwise the source will be set to the
* set_dma_device_addr value and the destination will get the set_dma_addr value.
*
* The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
* and make it explicit. Depending on what you're doing, one of these two should work
* for you, but don't mix them in the same transfer setup.
*/
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("enable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
}
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("disable_dma(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Turn off external requests, and stop any DMA in progress */
dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
}
/*
* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned int *dmalp;
volatile unsigned short *dmawp;
#ifdef DMA_DEBUG
printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
/* Clear config errors */
dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
/* Set command register */
dmalp[MCFDMA_DMR] =
MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
/* source static-address-mode */
((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
/* dest static-address-mode */
((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
/* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
(((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
(int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
/* Determine which address registers are used for memory/device accesses */
if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
/* Source incrementing, must be memory */
dmalp[MCFDMA_DSAR] = a;
/* Set dest address, must be device */
dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
} else {
/* Destination incrementing, must be memory */
dmalp[MCFDMA_DDAR] = a;
/* Set source address, must be device */
dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
}
#ifdef DEBUG_DMA
printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
__FILE__, __LINE__, dmanr, (int) &dmalp[MCFDMA_DMR], dmalp[MCFDMA_DMR],
(int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
(int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
#endif
}
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
{
#ifdef DMA_DEBUG
printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
#endif
dma_device_address[dmanr] = a;
}
/*
* NOTE 2: "count" represents _bytes_.
*
* NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned int *dmalp;
#ifdef DMA_DEBUG
printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
dmalp[MCFDMA_DBCR] = count;
}
/*
* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned int *dmalp;
unsigned int count;
#ifdef DMA_DEBUG
printk("get_dma_residue(dmanr=%d)\n", dmanr);
#endif
dmalp = (unsigned int *) dma_base_addr[dmanr];
count = dmalp[MCFDMA_DBCR];
return(count);
}
#endif /* !defined(CONFIG_M5272) */
#endif /* CONFIG_COLDFIRE */
/* it's useless on the m68k, but unfortunately needed by the new /* it's useless on the m68k, but unfortunately needed by the new
bootmem allocator (but this should do it for this) */ bootmem allocator (but this should do it for this) */
#define MAX_DMA_ADDRESS PAGE_OFFSET #define MAX_DMA_ADDRESS PAGE_OFFSET
#define MAX_DMA_CHANNELS 8
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy; extern int isa_dma_bridge_buggy;
#else #else
......
arch/m68k/include/asm/elf.h
View file @ 2d2da475
...@@ -60,6 +60,13 @@ typedef struct user_m68kfp_struct elf_fpregset_t; ...@@ -60,6 +60,13 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
is actually used on ASV. */ is actually used on ASV. */
#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0
#define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr, dynamic_addr) \
do { \
(_r)->d3 = _exec_map_addr; \
(_r)->d4 = _interp_map_addr; \
(_r)->d5 = dynamic_addr; \
} while(0)
#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) #if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
#define ELF_EXEC_PAGESIZE 8192 #define ELF_EXEC_PAGESIZE 8192
#else #else
...@@ -114,4 +121,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t; ...@@ -114,4 +121,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
#define ELF_PLATFORM (NULL) #define ELF_PLATFORM (NULL)
#define ELF_FDPIC_CORE_EFLAGS 0
#endif #endif
arch/m68k/include/asm/machdep.h
View file @ 2d2da475
...@@ -19,7 +19,6 @@ extern void (*mach_get_model) (char *model); ...@@ -19,7 +19,6 @@ extern void (*mach_get_model) (char *model);
extern void (*mach_get_hardware_list) (struct seq_file *m); extern void (*mach_get_hardware_list) (struct seq_file *m);
/* machine dependent timer functions */ /* machine dependent timer functions */
extern int (*mach_hwclk)(int, struct rtc_time*); extern int (*mach_hwclk)(int, struct rtc_time*);
extern unsigned int (*mach_get_ss)(void);
extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
extern void (*mach_reset)( void ); extern void (*mach_reset)( void );
......
arch/m68k/include/asm/mmu.h
View file @ 2d2da475
...@@ -6,9 +6,7 @@ ...@@ -6,9 +6,7 @@
/* Default "unsigned long" context */ /* Default "unsigned long" context */
typedef unsigned long mm_context_t; typedef unsigned long mm_context_t;
#else #else
typedef struct { #include <asm-generic/mmu.h>
unsigned long end_brk;
} mm_context_t;
#endif #endif
#endif #endif
arch/m68k/include/asm/pgtable_no.h
View file @ 2d2da475
...@@ -42,7 +42,8 @@ extern void paging_init(void); ...@@ -42,7 +42,8 @@ extern void paging_init(void);
* ZERO_PAGE is a global shared page that is always zero: used * ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc.. * for zero-mapped memory areas etc..
*/ */
#define ZERO_PAGE(vaddr) (virt_to_page(0)) extern void *empty_zero_page;
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
/* /*
* All 32bit addresses are effectively valid for vmalloc... * All 32bit addresses are effectively valid for vmalloc...
......
arch/m68k/include/uapi/asm/ptrace.h
View file @ 2d2da475
...@@ -74,7 +74,12 @@ struct switch_stack { ...@@ -74,7 +74,12 @@ struct switch_stack {
#define PTRACE_GET_THREAD_AREA 25 #define PTRACE_GET_THREAD_AREA 25
#define PTRACE_GETFDPIC 31
#define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */ #define PTRACE_SINGLEBLOCK 33 /* resume execution until next branch */
#define PTRACE_GETFDPIC_EXEC 0
#define PTRACE_GETFDPIC_INTERP 1
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* _UAPI_M68K_PTRACE_H */ #endif /* _UAPI_M68K_PTRACE_H */
arch/m68k/kernel/ptrace.c
View file @ 2d2da475
...@@ -19,6 +19,8 @@ ...@@ -19,6 +19,8 @@
#include <linux/ptrace.h> #include <linux/ptrace.h>
#include <linux/user.h> #include <linux/user.h>
#include <linux/signal.h> #include <linux/signal.h>
#include <linux/regset.h>
#include <linux/elf.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <asm/page.h> #include <asm/page.h>
...@@ -284,3 +286,59 @@ asmlinkage void syscall_trace_leave(void) ...@@ -284,3 +286,59 @@ asmlinkage void syscall_trace_leave(void)
if (test_thread_flag(TIF_SYSCALL_TRACE)) if (test_thread_flag(TIF_SYSCALL_TRACE))
ptrace_report_syscall_exit(task_pt_regs(current), 0); ptrace_report_syscall_exit(task_pt_regs(current), 0);
} }
#if defined(CONFIG_BINFMT_ELF_FDPIC) && defined(CONFIG_ELF_CORE)
/*
* Currently the only thing that needs to use regsets for m68k is the
* coredump support of the elf_fdpic loader. Implement the minimum
* definitions required for that.
*/
static int m68k_regset_get(struct task_struct *target,
const struct user_regset *regset,
struct membuf to)
{
struct pt_regs *ptregs = task_pt_regs(target);
u32 uregs[ELF_NGREG];
ELF_CORE_COPY_REGS(uregs, ptregs);
return membuf_write(&to, uregs, sizeof(uregs));
}
enum m68k_regset {
REGSET_GPR,
#ifdef CONFIG_FPU
REGSET_FPU,
#endif
};
static const struct user_regset m68k_user_regsets[] = {
[REGSET_GPR] = {
.core_note_type = NT_PRSTATUS,
.n = ELF_NGREG,
.size = sizeof(u32),
.align = sizeof(u16),
.regset_get = m68k_regset_get,
},
#ifdef CONFIG_FPU
[REGSET_FPU] = {
.core_note_type = NT_PRFPREG,
.n = sizeof(struct user_m68kfp_struct) / sizeof(u32),
.size = sizeof(u32),
.align = sizeof(u32),
}
#endif /* CONFIG_FPU */
};
static const struct user_regset_view user_m68k_view = {
.name = "m68k",
.e_machine = EM_68K,
.ei_osabi = ELF_OSABI,
.regsets = m68k_user_regsets,
.n = ARRAY_SIZE(m68k_user_regsets)
};
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
{
return &user_m68k_view;
}
#endif /* CONFIG_BINFMT_ELF_FDPIC && CONFIG_ELF_CORE */
arch/m68k/kernel/setup_mm.c
View file @ 2d2da475
...@@ -87,15 +87,6 @@ void (*mach_sched_init) (void) __initdata = NULL; ...@@ -87,15 +87,6 @@ void (*mach_sched_init) (void) __initdata = NULL;
void (*mach_init_IRQ) (void) __initdata = NULL; void (*mach_init_IRQ) (void) __initdata = NULL;
void (*mach_get_model) (char *model); void (*mach_get_model) (char *model);
void (*mach_get_hardware_list) (struct seq_file *m); void (*mach_get_hardware_list) (struct seq_file *m);
/* machine dependent timer functions */
int (*mach_hwclk) (int, struct rtc_time*);
EXPORT_SYMBOL(mach_hwclk);
unsigned int (*mach_get_ss)(void);
int (*mach_get_rtc_pll)(struct rtc_pll_info *);
int (*mach_set_rtc_pll)(struct rtc_pll_info *);
EXPORT_SYMBOL(mach_get_ss);
EXPORT_SYMBOL(mach_get_rtc_pll);
EXPORT_SYMBOL(mach_set_rtc_pll);
void (*mach_reset)( void ); void (*mach_reset)( void );
void (*mach_halt)( void ); void (*mach_halt)( void );
void (*mach_power_off)( void ); void (*mach_power_off)( void );
......
arch/m68k/kernel/setup_no.c
View file @ 2d2da475
...@@ -50,7 +50,6 @@ char __initdata command_line[COMMAND_LINE_SIZE]; ...@@ -50,7 +50,6 @@ char __initdata command_line[COMMAND_LINE_SIZE];
/* machine dependent timer functions */ /* machine dependent timer functions */
void (*mach_sched_init)(void) __initdata = NULL; void (*mach_sched_init)(void) __initdata = NULL;
int (*mach_hwclk) (int, struct rtc_time*);
/* machine dependent reboot functions */ /* machine dependent reboot functions */
void (*mach_reset)(void); void (*mach_reset)(void);
......
arch/m68k/kernel/time.c
View file @ 2d2da475
...@@ -63,6 +63,15 @@ void timer_heartbeat(void) ...@@ -63,6 +63,15 @@ void timer_heartbeat(void)
#endif /* CONFIG_HEARTBEAT */ #endif /* CONFIG_HEARTBEAT */
#ifdef CONFIG_M68KCLASSIC #ifdef CONFIG_M68KCLASSIC
/* machine dependent timer functions */
int (*mach_hwclk) (int, struct rtc_time*);
EXPORT_SYMBOL(mach_hwclk);
int (*mach_get_rtc_pll)(struct rtc_pll_info *);
int (*mach_set_rtc_pll)(struct rtc_pll_info *);
EXPORT_SYMBOL(mach_get_rtc_pll);
EXPORT_SYMBOL(mach_set_rtc_pll);
#if !IS_BUILTIN(CONFIG_RTC_DRV_GENERIC) #if !IS_BUILTIN(CONFIG_RTC_DRV_GENERIC)
void read_persistent_clock64(struct timespec64 *ts) void read_persistent_clock64(struct timespec64 *ts)
{ {
......
arch/m68k/mm/motorola.c
View file @ 2d2da475
...@@ -27,7 +27,6 @@ ...@@ -27,7 +27,6 @@
#include <asm/pgalloc.h> #include <asm/pgalloc.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/dma.h>
#ifdef CONFIG_ATARI #ifdef CONFIG_ATARI
#include <asm/atari_stram.h> #include <asm/atari_stram.h>
#endif #endif
......
arch/m68k/q40/config.c
View file @ 2d2da475
...@@ -41,7 +41,6 @@ static void q40_get_model(char *model); ...@@ -41,7 +41,6 @@ static void q40_get_model(char *model);
extern void q40_sched_init(void); extern void q40_sched_init(void);
static int q40_hwclk(int, struct rtc_time *); static int q40_hwclk(int, struct rtc_time *);
static unsigned int q40_get_ss(void);
static int q40_get_rtc_pll(struct rtc_pll_info *pll); static int q40_get_rtc_pll(struct rtc_pll_info *pll);
static int q40_set_rtc_pll(struct rtc_pll_info *pll); static int q40_set_rtc_pll(struct rtc_pll_info *pll);
...@@ -169,7 +168,6 @@ void __init config_q40(void) ...@@ -169,7 +168,6 @@ void __init config_q40(void)
mach_init_IRQ = q40_init_IRQ; mach_init_IRQ = q40_init_IRQ;
mach_hwclk = q40_hwclk; mach_hwclk = q40_hwclk;
mach_get_ss = q40_get_ss;
mach_get_rtc_pll = q40_get_rtc_pll; mach_get_rtc_pll = q40_get_rtc_pll;
mach_set_rtc_pll = q40_set_rtc_pll; mach_set_rtc_pll = q40_set_rtc_pll;
...@@ -246,11 +244,6 @@ static int q40_hwclk(int op, struct rtc_time *t) ...@@ -246,11 +244,6 @@ static int q40_hwclk(int op, struct rtc_time *t)
return 0; return 0;
} }
static unsigned int q40_get_ss(void)
{
return bcd2bin(Q40_RTC_SECS);
}
/* get and set PLL calibration of RTC clock */ /* get and set PLL calibration of RTC clock */
#define Q40_RTC_PLL_MASK ((1<<5)-1) #define Q40_RTC_PLL_MASK ((1<<5)-1)
#define Q40_RTC_PLL_SIGN (1<<5) #define Q40_RTC_PLL_SIGN (1<<5)
......
drivers/mmc/host/Kconfig
View file @ 2d2da475
...@@ -508,7 +508,7 @@ config MMC_OMAP_HS ...@@ -508,7 +508,7 @@ config MMC_OMAP_HS
config MMC_WBSD config MMC_WBSD
tristate "Winbond W83L51xD SD/MMC Card Interface support" tristate "Winbond W83L51xD SD/MMC Card Interface support"
depends on ISA_DMA_API && !M68K depends on ISA_DMA_API
help help
This selects the Winbond(R) W83L51xD Secure digital and This selects the Winbond(R) W83L51xD Secure digital and
Multimedia card Interface. Multimedia card Interface.
......
fs/Kconfig.binfmt
View file @ 2d2da475
...@@ -58,7 +58,7 @@ config ARCH_USE_GNU_PROPERTY ...@@ -58,7 +58,7 @@ config ARCH_USE_GNU_PROPERTY
config BINFMT_ELF_FDPIC config BINFMT_ELF_FDPIC
bool "Kernel support for FDPIC ELF binaries" bool "Kernel support for FDPIC ELF binaries"
default y if !BINFMT_ELF default y if !BINFMT_ELF
depends on (ARM || (SUPERH && !MMU)) depends on ARM || ((M68K || SUPERH) && !MMU)
select ELFCORE select ELFCORE
help help
ELF FDPIC binaries are based on ELF, but allow the individual load ELF FDPIC binaries are based on ELF, but allow the individual load
......
sound/core/Makefile
View file @ 2d2da475
...@@ -9,9 +9,7 @@ ifneq ($(CONFIG_SND_PROC_FS),) ...@@ -9,9 +9,7 @@ ifneq ($(CONFIG_SND_PROC_FS),)
snd-y += info.o snd-y += info.o
snd-$(CONFIG_SND_OSSEMUL) += info_oss.o snd-$(CONFIG_SND_OSSEMUL) += info_oss.o
endif endif
ifneq ($(CONFIG_M68K),y)
snd-$(CONFIG_ISA_DMA_API) += isadma.o snd-$(CONFIG_ISA_DMA_API) += isadma.o
endif
snd-$(CONFIG_SND_OSSEMUL) += sound_oss.o snd-$(CONFIG_SND_OSSEMUL) += sound_oss.o
snd-$(CONFIG_SND_VMASTER) += vmaster.o snd-$(CONFIG_SND_VMASTER) += vmaster.o
snd-$(CONFIG_SND_JACK) += ctljack.o jack.o snd-$(CONFIG_SND_JACK) += ctljack.o jack.o
......
sound/isa/Kconfig
View file @ 2d2da475
...@@ -22,7 +22,7 @@ config SND_SB16_DSP ...@@ -22,7 +22,7 @@ config SND_SB16_DSP
menuconfig SND_ISA menuconfig SND_ISA
bool "ISA sound devices" bool "ISA sound devices"
depends on ISA || COMPILE_TEST depends on ISA || COMPILE_TEST
depends on ISA_DMA_API && !M68K depends on ISA_DMA_API
default y default y
help help
Support for sound devices connected via the ISA bus. Support for sound devices connected via the ISA bus.
......
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