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Commit 2e89db75 authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
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serial: MPSC: Fix coding style and whitespace issues 

Fix up mpsc.c to be aligned with Documentation/CodingStyle.  Also fix up some
whitespace issues.
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 79f85173
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Showing with 283 additions and 401 deletions
drivers/serial/mpsc.c
View file @ 2e89db75
...@@ -93,9 +93,8 @@ ...@@ -93,9 +93,8 @@
#define MPSC_TXBE_SIZE dma_get_cache_alignment() #define MPSC_TXBE_SIZE dma_get_cache_alignment()
#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \ #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
MPSC_TXR_SIZE + MPSC_TXB_SIZE + \ + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
dma_get_cache_alignment() /* for alignment */)
/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
struct mpsc_rx_desc { struct mpsc_rx_desc {
...@@ -266,8 +265,8 @@ struct mpsc_port_info *mpsc_device_remove(int index); ...@@ -266,8 +265,8 @@ struct mpsc_port_info *mpsc_device_remove(int index);
#define SDMA_DESC_CMDSTAT_EI (1<<23) #define SDMA_DESC_CMDSTAT_EI (1<<23)
#define SDMA_DESC_CMDSTAT_O (1<<31) #define SDMA_DESC_CMDSTAT_O (1<<31)
#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
SDMA_DESC_CMDSTAT_EI) | SDMA_DESC_CMDSTAT_EI)
#define SDMA_SDC_RFT (1<<0) #define SDMA_SDC_RFT (1<<0)
#define SDMA_SDC_SFM (1<<1) #define SDMA_SDC_SFM (1<<1)
...@@ -291,10 +290,10 @@ struct mpsc_port_info *mpsc_device_remove(int index); ...@@ -291,10 +290,10 @@ struct mpsc_port_info *mpsc_device_remove(int index);
#define SDMA_1_CAUSE_TXBUF (1<<10) #define SDMA_1_CAUSE_TXBUF (1<<10)
#define SDMA_1_CAUSE_TXEND (1<<11) #define SDMA_1_CAUSE_TXEND (1<<11)
#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
/* SDMA Interrupt registers */ /* SDMA Interrupt registers */
#define SDMA_INTR_CAUSE 0x0000 #define SDMA_INTR_CAUSE 0x0000
...@@ -328,8 +327,7 @@ static void mpsc_release_port(struct uart_port *port); ...@@ -328,8 +327,7 @@ static void mpsc_release_port(struct uart_port *port);
* *
****************************************************************************** ******************************************************************************
*/ */
static void static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
{ {
u32 v; u32 v;
...@@ -345,11 +343,9 @@ mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) ...@@ -345,11 +343,9 @@ mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
pi->brg_base + BRG_BTR); pi->brg_base + BRG_BTR);
return;
} }
static void static void mpsc_brg_enable(struct mpsc_port_info *pi)
mpsc_brg_enable(struct mpsc_port_info *pi)
{ {
u32 v; u32 v;
...@@ -359,11 +355,9 @@ mpsc_brg_enable(struct mpsc_port_info *pi) ...@@ -359,11 +355,9 @@ mpsc_brg_enable(struct mpsc_port_info *pi)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->BRG_BCR_m = v; pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR); writel(v, pi->brg_base + BRG_BCR);
return;
} }
static void static void mpsc_brg_disable(struct mpsc_port_info *pi)
mpsc_brg_disable(struct mpsc_port_info *pi)
{ {
u32 v; u32 v;
...@@ -373,13 +367,9 @@ mpsc_brg_disable(struct mpsc_port_info *pi) ...@@ -373,13 +367,9 @@ mpsc_brg_disable(struct mpsc_port_info *pi)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->BRG_BCR_m = v; pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR); writel(v, pi->brg_base + BRG_BCR);
return;
} }
static inline void /*
mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
{
/*
* To set the baud, we adjust the CDV field in the BRG_BCR reg. * To set the baud, we adjust the CDV field in the BRG_BCR reg.
* From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1. * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
* However, the input clock is divided by 16 in the MPSC b/c of how * However, the input clock is divided by 16 in the MPSC b/c of how
...@@ -388,6 +378,8 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) ...@@ -388,6 +378,8 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
* that accounts for the way the mpsc is set up is: * that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1. * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
*/ */
static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
{
u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
u32 v; u32 v;
...@@ -399,8 +391,6 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) ...@@ -399,8 +391,6 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
pi->BRG_BCR_m = v; pi->BRG_BCR_m = v;
writel(v, pi->brg_base + BRG_BCR); writel(v, pi->brg_base + BRG_BCR);
mpsc_brg_enable(pi); mpsc_brg_enable(pi);
return;
} }
/* /*
...@@ -411,8 +401,7 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) ...@@ -411,8 +401,7 @@ mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
****************************************************************************** ******************************************************************************
*/ */
static void static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
{ {
u32 v; u32 v;
...@@ -432,11 +421,9 @@ mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) ...@@ -432,11 +421,9 @@ mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
pi->sdma_base + SDMA_SDC); pi->sdma_base + SDMA_SDC);
return;
} }
static void static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
{ {
pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
burst_size); burst_size);
...@@ -444,11 +431,9 @@ mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) ...@@ -444,11 +431,9 @@ mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
pi->sdma_base + SDMA_SDC); pi->sdma_base + SDMA_SDC);
mpsc_sdma_burstsize(pi, burst_size); mpsc_sdma_burstsize(pi, burst_size);
return;
} }
static inline u32 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
{ {
u32 old, v; u32 old, v;
...@@ -471,15 +456,14 @@ mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) ...@@ -471,15 +456,14 @@ mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
return old & 0xf; return old & 0xf;
} }
static inline void static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
{ {
u32 v; u32 v;
pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
mask &= 0xf; mask &= 0xf;
if (pi->port.line) if (pi->port.line)
...@@ -489,41 +473,35 @@ mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) ...@@ -489,41 +473,35 @@ mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->shared_regs->SDMA_INTR_MASK_m = v; pi->shared_regs->SDMA_INTR_MASK_m = v;
writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
return;
} }
static inline void static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
if (pi->mirror_regs) if (pi->mirror_regs)
pi->shared_regs->SDMA_INTR_CAUSE_m = 0; pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE + writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
pi->port.line); + pi->port.line);
return;
} }
static inline void static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p) struct mpsc_rx_desc *rxre_p)
{ {
pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
pi->port.line, (u32) rxre_p); pi->port.line, (u32)rxre_p);
writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
return;
} }
static inline void static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p) struct mpsc_tx_desc *txre_p)
{ {
writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
return;
} }
static inline void static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
{ {
u32 v; u32 v;
...@@ -535,25 +513,23 @@ mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) ...@@ -535,25 +513,23 @@ mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
wmb(); wmb();
writel(v, pi->sdma_base + SDMA_SDCM); writel(v, pi->sdma_base + SDMA_SDCM);
wmb(); wmb();
return;
} }
static inline uint static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
mpsc_sdma_tx_active(struct mpsc_port_info *pi)
{ {
return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
} }
static inline void static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
mpsc_sdma_start_tx(struct mpsc_port_info *pi)
{ {
struct mpsc_tx_desc *txre, *txre_p; struct mpsc_tx_desc *txre, *txre_p;
/* If tx isn't running & there's a desc ready to go, start it */ /* If tx isn't running & there's a desc ready to go, start it */
if (!mpsc_sdma_tx_active(pi)) { if (!mpsc_sdma_tx_active(pi)) {
txre = (struct mpsc_tx_desc *)(pi->txr + txre = (struct mpsc_tx_desc *)(pi->txr
(pi->txr_tail * MPSC_TXRE_SIZE)); + (pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)txre, invalidate_dcache_range((ulong)txre,
...@@ -561,20 +537,16 @@ mpsc_sdma_start_tx(struct mpsc_port_info *pi) ...@@ -561,20 +537,16 @@ mpsc_sdma_start_tx(struct mpsc_port_info *pi)
#endif #endif
if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
txre_p = (struct mpsc_tx_desc *)(pi->txr_p + txre_p = (struct mpsc_tx_desc *)
(pi->txr_tail * (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
MPSC_TXRE_SIZE));
mpsc_sdma_set_tx_ring(pi, txre_p); mpsc_sdma_set_tx_ring(pi, txre_p);
mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
} }
} }
return;
} }
static inline void static void mpsc_sdma_stop(struct mpsc_port_info *pi)
mpsc_sdma_stop(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
...@@ -589,8 +561,6 @@ mpsc_sdma_stop(struct mpsc_port_info *pi) ...@@ -589,8 +561,6 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
/* Disable interrupts */ /* Disable interrupts */
mpsc_sdma_intr_mask(pi, 0xf); mpsc_sdma_intr_mask(pi, 0xf);
mpsc_sdma_intr_ack(pi); mpsc_sdma_intr_ack(pi);
return;
} }
/* /*
...@@ -601,8 +571,7 @@ mpsc_sdma_stop(struct mpsc_port_info *pi) ...@@ -601,8 +571,7 @@ mpsc_sdma_stop(struct mpsc_port_info *pi)
****************************************************************************** ******************************************************************************
*/ */
static void static void mpsc_hw_init(struct mpsc_port_info *pi)
mpsc_hw_init(struct mpsc_port_info *pi)
{ {
u32 v; u32 v;
...@@ -624,8 +593,7 @@ mpsc_hw_init(struct mpsc_port_info *pi) ...@@ -624,8 +593,7 @@ mpsc_hw_init(struct mpsc_port_info *pi)
v = (v & ~0xf0f) | 0x100; v = (v & ~0xf0f) | 0x100;
pi->shared_regs->MPSC_TCRR_m = v; pi->shared_regs->MPSC_TCRR_m = v;
writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
} } else {
else {
v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
v &= ~0x1c7; v &= ~0x1c7;
writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
...@@ -659,12 +627,9 @@ mpsc_hw_init(struct mpsc_port_info *pi) ...@@ -659,12 +627,9 @@ mpsc_hw_init(struct mpsc_port_info *pi)
writel(0, pi->mpsc_base + MPSC_CHR_8); writel(0, pi->mpsc_base + MPSC_CHR_8);
writel(0, pi->mpsc_base + MPSC_CHR_9); writel(0, pi->mpsc_base + MPSC_CHR_9);
writel(0, pi->mpsc_base + MPSC_CHR_10); writel(0, pi->mpsc_base + MPSC_CHR_10);
return;
} }
static inline void static void mpsc_enter_hunt(struct mpsc_port_info *pi)
mpsc_enter_hunt(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
...@@ -673,20 +638,16 @@ mpsc_enter_hunt(struct mpsc_port_info *pi) ...@@ -673,20 +638,16 @@ mpsc_enter_hunt(struct mpsc_port_info *pi)
pi->mpsc_base + MPSC_CHR_2); pi->mpsc_base + MPSC_CHR_2);
/* Erratum prevents reading CHR_2 so just delay for a while */ /* Erratum prevents reading CHR_2 so just delay for a while */
udelay(100); udelay(100);
} } else {
else {
writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
pi->mpsc_base + MPSC_CHR_2); pi->mpsc_base + MPSC_CHR_2);
while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
udelay(10); udelay(10);
} }
return;
} }
static inline void static void mpsc_freeze(struct mpsc_port_info *pi)
mpsc_freeze(struct mpsc_port_info *pi)
{ {
u32 v; u32 v;
...@@ -699,11 +660,9 @@ mpsc_freeze(struct mpsc_port_info *pi) ...@@ -699,11 +660,9 @@ mpsc_freeze(struct mpsc_port_info *pi)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->MPSC_MPCR_m = v; pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR); writel(v, pi->mpsc_base + MPSC_MPCR);
return;
} }
static inline void static void mpsc_unfreeze(struct mpsc_port_info *pi)
mpsc_unfreeze(struct mpsc_port_info *pi)
{ {
u32 v; u32 v;
...@@ -716,11 +675,9 @@ mpsc_unfreeze(struct mpsc_port_info *pi) ...@@ -716,11 +675,9 @@ mpsc_unfreeze(struct mpsc_port_info *pi)
writel(v, pi->mpsc_base + MPSC_MPCR); writel(v, pi->mpsc_base + MPSC_MPCR);
pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
return;
} }
static inline void static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
{ {
u32 v; u32 v;
...@@ -733,11 +690,9 @@ mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) ...@@ -733,11 +690,9 @@ mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->MPSC_MPCR_m = v; pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR); writel(v, pi->mpsc_base + MPSC_MPCR);
return;
} }
static inline void static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
{ {
u32 v; u32 v;
...@@ -752,11 +707,9 @@ mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) ...@@ -752,11 +707,9 @@ mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->MPSC_MPCR_m = v; pi->MPSC_MPCR_m = v;
writel(v, pi->mpsc_base + MPSC_MPCR); writel(v, pi->mpsc_base + MPSC_MPCR);
return;
} }
static inline void static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
{ {
u32 v; u32 v;
...@@ -771,7 +724,6 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p) ...@@ -771,7 +724,6 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
if (pi->mirror_regs) if (pi->mirror_regs)
pi->MPSC_CHR_2_m = v; pi->MPSC_CHR_2_m = v;
writel(v, pi->mpsc_base + MPSC_CHR_2); writel(v, pi->mpsc_base + MPSC_CHR_2);
return;
} }
/* /*
...@@ -782,8 +734,7 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p) ...@@ -782,8 +734,7 @@ mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
****************************************************************************** ******************************************************************************
*/ */
static void static void mpsc_init_hw(struct mpsc_port_info *pi)
mpsc_init_hw(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
...@@ -792,12 +743,9 @@ mpsc_init_hw(struct mpsc_port_info *pi) ...@@ -792,12 +743,9 @@ mpsc_init_hw(struct mpsc_port_info *pi)
mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
mpsc_sdma_stop(pi); mpsc_sdma_stop(pi);
mpsc_hw_init(pi); mpsc_hw_init(pi);
return;
} }
static int static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
{ {
int rc = 0; int rc = 0;
...@@ -808,11 +756,10 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi) ...@@ -808,11 +756,10 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
if (!dma_supported(pi->port.dev, 0xffffffff)) { if (!dma_supported(pi->port.dev, 0xffffffff)) {
printk(KERN_ERR "MPSC: Inadequate DMA support\n"); printk(KERN_ERR "MPSC: Inadequate DMA support\n");
rc = -ENXIO; rc = -ENXIO;
} } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL)) &pi->dma_region_p, GFP_KERNEL))
== NULL) { == NULL) {
printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
rc = -ENOMEM; rc = -ENOMEM;
} }
...@@ -821,8 +768,7 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi) ...@@ -821,8 +768,7 @@ mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
return rc; return rc;
} }
static void static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
mpsc_free_ring_mem(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
...@@ -830,14 +776,11 @@ mpsc_free_ring_mem(struct mpsc_port_info *pi) ...@@ -830,14 +776,11 @@ mpsc_free_ring_mem(struct mpsc_port_info *pi)
dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
pi->dma_region, pi->dma_region_p); pi->dma_region, pi->dma_region_p);
pi->dma_region = NULL; pi->dma_region = NULL;
pi->dma_region_p = (dma_addr_t) NULL; pi->dma_region_p = (dma_addr_t)NULL;
} }
return;
} }
static void static void mpsc_init_rings(struct mpsc_port_info *pi)
mpsc_init_rings(struct mpsc_port_info *pi)
{ {
struct mpsc_rx_desc *rxre; struct mpsc_rx_desc *rxre;
struct mpsc_tx_desc *txre; struct mpsc_tx_desc *txre;
...@@ -855,8 +798,8 @@ mpsc_init_rings(struct mpsc_port_info *pi) ...@@ -855,8 +798,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
* Descriptors & buffers are multiples of cacheline size and must be * Descriptors & buffers are multiples of cacheline size and must be
* cacheline aligned. * cacheline aligned.
*/ */
dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment()); dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment()); dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
/* /*
* Partition dma region into rx ring descriptor, rx buffers, * Partition dma region into rx ring descriptor, rx buffers,
...@@ -867,8 +810,8 @@ mpsc_init_rings(struct mpsc_port_info *pi) ...@@ -867,8 +810,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
dp += MPSC_RXR_SIZE; dp += MPSC_RXR_SIZE;
dp_p += MPSC_RXR_SIZE; dp_p += MPSC_RXR_SIZE;
pi->rxb = (u8 *) dp; pi->rxb = (u8 *)dp;
pi->rxb_p = (u8 *) dp_p; pi->rxb_p = (u8 *)dp_p;
dp += MPSC_RXB_SIZE; dp += MPSC_RXB_SIZE;
dp_p += MPSC_RXB_SIZE; dp_p += MPSC_RXB_SIZE;
...@@ -879,8 +822,8 @@ mpsc_init_rings(struct mpsc_port_info *pi) ...@@ -879,8 +822,8 @@ mpsc_init_rings(struct mpsc_port_info *pi)
dp += MPSC_TXR_SIZE; dp += MPSC_TXR_SIZE;
dp_p += MPSC_TXR_SIZE; dp_p += MPSC_TXR_SIZE;
pi->txb = (u8 *) dp; pi->txb = (u8 *)dp;
pi->txb_p = (u8 *) dp_p; pi->txb_p = (u8 *)dp_p;
pi->txr_head = 0; pi->txr_head = 0;
pi->txr_tail = 0; pi->txr_tail = 0;
...@@ -896,10 +839,9 @@ mpsc_init_rings(struct mpsc_port_info *pi) ...@@ -896,10 +839,9 @@ mpsc_init_rings(struct mpsc_port_info *pi)
rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
rxre->bytecnt = cpu_to_be16(0); rxre->bytecnt = cpu_to_be16(0);
rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
SDMA_DESC_CMDSTAT_EI | | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
SDMA_DESC_CMDSTAT_F | | SDMA_DESC_CMDSTAT_L);
SDMA_DESC_CMDSTAT_L);
rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
rxre->buf_ptr = cpu_to_be32(bp_p); rxre->buf_ptr = cpu_to_be32(bp_p);
...@@ -929,19 +871,19 @@ mpsc_init_rings(struct mpsc_port_info *pi) ...@@ -929,19 +871,19 @@ mpsc_init_rings(struct mpsc_port_info *pi)
} }
txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE, dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
DMA_BIDIRECTIONAL); MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)pi->dma_region, flush_dcache_range((ulong)pi->dma_region,
(ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE); (ulong)pi->dma_region
+ MPSC_DMA_ALLOC_SIZE);
#endif #endif
return; return;
} }
static void static void mpsc_uninit_rings(struct mpsc_port_info *pi)
mpsc_uninit_rings(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
...@@ -959,12 +901,9 @@ mpsc_uninit_rings(struct mpsc_port_info *pi) ...@@ -959,12 +901,9 @@ mpsc_uninit_rings(struct mpsc_port_info *pi)
pi->txb_p = NULL; pi->txb_p = NULL;
pi->txr_head = 0; pi->txr_head = 0;
pi->txr_tail = 0; pi->txr_tail = 0;
return;
} }
static int static int mpsc_make_ready(struct mpsc_port_info *pi)
mpsc_make_ready(struct mpsc_port_info *pi)
{ {
int rc; int rc;
...@@ -989,8 +928,7 @@ mpsc_make_ready(struct mpsc_port_info *pi) ...@@ -989,8 +928,7 @@ mpsc_make_ready(struct mpsc_port_info *pi)
****************************************************************************** ******************************************************************************
*/ */
static inline int static int mpsc_rx_intr(struct mpsc_port_info *pi)
mpsc_rx_intr(struct mpsc_port_info *pi)
{ {
struct mpsc_rx_desc *rxre; struct mpsc_rx_desc *rxre;
struct tty_struct *tty = pi->port.info->tty; struct tty_struct *tty = pi->port.info->tty;
...@@ -1003,7 +941,8 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1003,7 +941,8 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)rxre, invalidate_dcache_range((ulong)rxre,
...@@ -1013,11 +952,13 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1013,11 +952,13 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
/* /*
* Loop through Rx descriptors handling ones that have been completed. * Loop through Rx descriptors handling ones that have been completed.
*/ */
while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){ while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
& SDMA_DESC_CMDSTAT_O)) {
bytes_in = be16_to_cpu(rxre->bytecnt); bytes_in = be16_to_cpu(rxre->bytecnt);
/* Following use of tty struct directly is deprecated */ /* Following use of tty struct directly is deprecated */
if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) { if (unlikely(tty_buffer_request_room(tty, bytes_in)
< bytes_in)) {
if (tty->low_latency) if (tty->low_latency)
tty_flip_buffer_push(tty); tty_flip_buffer_push(tty);
/* /*
...@@ -1027,7 +968,8 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1027,7 +968,8 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
} }
bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE); dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)bp, invalidate_dcache_range((ulong)bp,
...@@ -1042,8 +984,9 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1042,8 +984,9 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
* we'll assume there is no data in the buffer. * we'll assume there is no data in the buffer.
* If there is...it gets lost. * If there is...it gets lost.
*/ */
if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) { | SDMA_DESC_CMDSTAT_FR
| SDMA_DESC_CMDSTAT_OR))) {
pi->port.icount.rx++; pi->port.icount.rx++;
...@@ -1052,11 +995,11 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1052,11 +995,11 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
if (uart_handle_break(&pi->port)) if (uart_handle_break(&pi->port))
goto next_frame; goto next_frame;
} } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */
pi->port.icount.frame++; pi->port.icount.frame++;
else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */ } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
pi->port.icount.overrun++; pi->port.icount.overrun++;
}
cmdstat &= pi->port.read_status_mask; cmdstat &= pi->port.read_status_mask;
...@@ -1076,12 +1019,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1076,12 +1019,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
goto next_frame; goto next_frame;
} }
if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && | SDMA_DESC_CMDSTAT_FR
!(cmdstat & pi->port.ignore_status_mask)) | SDMA_DESC_CMDSTAT_OR)))
&& !(cmdstat & pi->port.ignore_status_mask)) {
tty_insert_flip_char(tty, *bp, flag); tty_insert_flip_char(tty, *bp, flag);
else { } else {
for (i=0; i<bytes_in; i++) for (i=0; i<bytes_in; i++)
tty_insert_flip_char(tty, *bp++, TTY_NORMAL); tty_insert_flip_char(tty, *bp++, TTY_NORMAL);
...@@ -1091,12 +1034,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1091,12 +1034,12 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
next_frame: next_frame:
rxre->bytecnt = cpu_to_be16(0); rxre->bytecnt = cpu_to_be16(0);
wmb(); wmb();
rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
SDMA_DESC_CMDSTAT_EI | | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
SDMA_DESC_CMDSTAT_F | | SDMA_DESC_CMDSTAT_L);
SDMA_DESC_CMDSTAT_L);
wmb(); wmb();
dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)rxre, flush_dcache_range((ulong)rxre,
...@@ -1105,15 +1048,15 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1105,15 +1048,15 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
/* Advance to next descriptor */ /* Advance to next descriptor */
pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
rxre = (struct mpsc_rx_desc *)(pi->rxr + rxre = (struct mpsc_rx_desc *)
(pi->rxr_posn * MPSC_RXRE_SIZE)); (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)rxre, invalidate_dcache_range((ulong)rxre,
(ulong)rxre + MPSC_RXRE_SIZE); (ulong)rxre + MPSC_RXRE_SIZE);
#endif #endif
rc = 1; rc = 1;
} }
...@@ -1125,42 +1068,38 @@ mpsc_rx_intr(struct mpsc_port_info *pi) ...@@ -1125,42 +1068,38 @@ mpsc_rx_intr(struct mpsc_port_info *pi)
return rc; return rc;
} }
static inline void static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
{ {
struct mpsc_tx_desc *txre; struct mpsc_tx_desc *txre;
txre = (struct mpsc_tx_desc *)(pi->txr + txre = (struct mpsc_tx_desc *)(pi->txr
(pi->txr_head * MPSC_TXRE_SIZE)); + (pi->txr_head * MPSC_TXRE_SIZE));
txre->bytecnt = cpu_to_be16(count); txre->bytecnt = cpu_to_be16(count);
txre->shadow = txre->bytecnt; txre->shadow = txre->bytecnt;
wmb(); /* ensure cmdstat is last field updated */ wmb(); /* ensure cmdstat is last field updated */
txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F | txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
SDMA_DESC_CMDSTAT_L | ((intr) ? | SDMA_DESC_CMDSTAT_L
SDMA_DESC_CMDSTAT_EI | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
: 0));
wmb(); wmb();
dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL); dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)txre, flush_dcache_range((ulong)txre,
(ulong)txre + MPSC_TXRE_SIZE); (ulong)txre + MPSC_TXRE_SIZE);
#endif #endif
return;
} }
static inline void static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
mpsc_copy_tx_data(struct mpsc_port_info *pi)
{ {
struct circ_buf *xmit = &pi->port.info->xmit; struct circ_buf *xmit = &pi->port.info->xmit;
u8 *bp; u8 *bp;
u32 i; u32 i;
/* Make sure the desc ring isn't full */ /* Make sure the desc ring isn't full */
while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) < while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
(MPSC_TXR_ENTRIES - 1)) { < (MPSC_TXR_ENTRIES - 1)) {
if (pi->port.x_char) { if (pi->port.x_char) {
/* /*
* Ideally, we should use the TCS field in * Ideally, we should use the TCS field in
...@@ -1174,11 +1113,11 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi) ...@@ -1174,11 +1113,11 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi)
*bp = pi->port.x_char; *bp = pi->port.x_char;
pi->port.x_char = 0; pi->port.x_char = 0;
i = 1; i = 1;
} } else if (!uart_circ_empty(xmit)
else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){ && !uart_tx_stopped(&pi->port)) {
i = min((u32) MPSC_TXBE_SIZE, i = min((u32)MPSC_TXBE_SIZE,
(u32) uart_circ_chars_pending(xmit)); (u32)uart_circ_chars_pending(xmit));
i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail, i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
UART_XMIT_SIZE)); UART_XMIT_SIZE));
bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
memcpy(bp, &xmit->buf[xmit->tail], i); memcpy(bp, &xmit->buf[xmit->tail], i);
...@@ -1186,11 +1125,12 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi) ...@@ -1186,11 +1125,12 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi)
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(&pi->port); uart_write_wakeup(&pi->port);
} } else { /* All tx data copied into ring bufs */
else /* All tx data copied into ring bufs */
return; return;
}
dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)bp, flush_dcache_range((ulong)bp,
...@@ -1201,12 +1141,9 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi) ...@@ -1201,12 +1141,9 @@ mpsc_copy_tx_data(struct mpsc_port_info *pi)
/* Advance to next descriptor */ /* Advance to next descriptor */
pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
} }
return;
} }
static inline int static int mpsc_tx_intr(struct mpsc_port_info *pi)
mpsc_tx_intr(struct mpsc_port_info *pi)
{ {
struct mpsc_tx_desc *txre; struct mpsc_tx_desc *txre;
int rc = 0; int rc = 0;
...@@ -1215,10 +1152,11 @@ mpsc_tx_intr(struct mpsc_port_info *pi) ...@@ -1215,10 +1152,11 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
spin_lock_irqsave(&pi->tx_lock, iflags); spin_lock_irqsave(&pi->tx_lock, iflags);
if (!mpsc_sdma_tx_active(pi)) { if (!mpsc_sdma_tx_active(pi)) {
txre = (struct mpsc_tx_desc *)(pi->txr + txre = (struct mpsc_tx_desc *)(pi->txr
(pi->txr_tail * MPSC_TXRE_SIZE)); + (pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)txre, invalidate_dcache_range((ulong)txre,
...@@ -1234,10 +1172,10 @@ mpsc_tx_intr(struct mpsc_port_info *pi) ...@@ -1234,10 +1172,10 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
if (pi->txr_head == pi->txr_tail) if (pi->txr_head == pi->txr_tail)
break; break;
txre = (struct mpsc_tx_desc *)(pi->txr + txre = (struct mpsc_tx_desc *)(pi->txr
(pi->txr_tail * MPSC_TXRE_SIZE)); + (pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, dma_cache_sync(pi->port.dev, (void *)txre,
DMA_FROM_DEVICE); MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
invalidate_dcache_range((ulong)txre, invalidate_dcache_range((ulong)txre,
...@@ -1258,8 +1196,7 @@ mpsc_tx_intr(struct mpsc_port_info *pi) ...@@ -1258,8 +1196,7 @@ mpsc_tx_intr(struct mpsc_port_info *pi)
* the interrupt, then handle any completed Rx/Tx descriptors. When done * the interrupt, then handle any completed Rx/Tx descriptors. When done
* handling those descriptors, we restart the Rx/Tx engines if they're stopped. * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
*/ */
static irqreturn_t static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
mpsc_sdma_intr(int irq, void *dev_id)
{ {
struct mpsc_port_info *pi = dev_id; struct mpsc_port_info *pi = dev_id;
ulong iflags; ulong iflags;
...@@ -1286,8 +1223,7 @@ mpsc_sdma_intr(int irq, void *dev_id) ...@@ -1286,8 +1223,7 @@ mpsc_sdma_intr(int irq, void *dev_id)
* *
****************************************************************************** ******************************************************************************
*/ */
static uint static uint mpsc_tx_empty(struct uart_port *port)
mpsc_tx_empty(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
ulong iflags; ulong iflags;
...@@ -1300,21 +1236,18 @@ mpsc_tx_empty(struct uart_port *port) ...@@ -1300,21 +1236,18 @@ mpsc_tx_empty(struct uart_port *port)
return rc; return rc;
} }
static void static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
mpsc_set_mctrl(struct uart_port *port, uint mctrl)
{ {
/* Have no way to set modem control lines AFAICT */ /* Have no way to set modem control lines AFAICT */
return;
} }
static uint static uint mpsc_get_mctrl(struct uart_port *port)
mpsc_get_mctrl(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
u32 mflags, status; u32 mflags, status;
status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
readl(pi->mpsc_base + MPSC_CHR_10); : readl(pi->mpsc_base + MPSC_CHR_10);
mflags = 0; mflags = 0;
if (status & 0x1) if (status & 0x1)
...@@ -1325,19 +1258,16 @@ mpsc_get_mctrl(struct uart_port *port) ...@@ -1325,19 +1258,16 @@ mpsc_get_mctrl(struct uart_port *port)
return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
} }
static void static void mpsc_stop_tx(struct uart_port *port)
mpsc_stop_tx(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
pr_debug("mpsc_stop_tx[%d]\n", port->line); pr_debug("mpsc_stop_tx[%d]\n", port->line);
mpsc_freeze(pi); mpsc_freeze(pi);
return;
} }
static void static void mpsc_start_tx(struct uart_port *port)
mpsc_start_tx(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
unsigned long iflags; unsigned long iflags;
...@@ -1351,11 +1281,9 @@ mpsc_start_tx(struct uart_port *port) ...@@ -1351,11 +1281,9 @@ mpsc_start_tx(struct uart_port *port)
spin_unlock_irqrestore(&pi->tx_lock, iflags); spin_unlock_irqrestore(&pi->tx_lock, iflags);
pr_debug("mpsc_start_tx[%d]\n", port->line); pr_debug("mpsc_start_tx[%d]\n", port->line);
return;
} }
static void static void mpsc_start_rx(struct mpsc_port_info *pi)
mpsc_start_rx(struct mpsc_port_info *pi)
{ {
pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
...@@ -1363,11 +1291,9 @@ mpsc_start_rx(struct mpsc_port_info *pi) ...@@ -1363,11 +1291,9 @@ mpsc_start_rx(struct mpsc_port_info *pi)
mpsc_enter_hunt(pi); mpsc_enter_hunt(pi);
mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
} }
return;
} }
static void static void mpsc_stop_rx(struct uart_port *port)
mpsc_stop_rx(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
...@@ -1378,8 +1304,7 @@ mpsc_stop_rx(struct uart_port *port) ...@@ -1378,8 +1304,7 @@ mpsc_stop_rx(struct uart_port *port)
pi->mpsc_base + MPSC_CHR_2); pi->mpsc_base + MPSC_CHR_2);
/* Erratum prevents reading CHR_2 so just delay for a while */ /* Erratum prevents reading CHR_2 so just delay for a while */
udelay(100); udelay(100);
} } else {
else {
writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA, writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
pi->mpsc_base + MPSC_CHR_2); pi->mpsc_base + MPSC_CHR_2);
...@@ -1388,17 +1313,13 @@ mpsc_stop_rx(struct uart_port *port) ...@@ -1388,17 +1313,13 @@ mpsc_stop_rx(struct uart_port *port)
} }
mpsc_sdma_cmd(pi, SDMA_SDCM_AR); mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
return;
} }
static void static void mpsc_enable_ms(struct uart_port *port)
mpsc_enable_ms(struct uart_port *port)
{ {
return; /* Not supported */
} }
static void static void mpsc_break_ctl(struct uart_port *port, int ctl)
mpsc_break_ctl(struct uart_port *port, int ctl)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
ulong flags; ulong flags;
...@@ -1411,12 +1332,9 @@ mpsc_break_ctl(struct uart_port *port, int ctl) ...@@ -1411,12 +1332,9 @@ mpsc_break_ctl(struct uart_port *port, int ctl)
pi->MPSC_CHR_1_m = v; pi->MPSC_CHR_1_m = v;
writel(v, pi->mpsc_base + MPSC_CHR_1); writel(v, pi->mpsc_base + MPSC_CHR_1);
spin_unlock_irqrestore(&pi->port.lock, flags); spin_unlock_irqrestore(&pi->port.lock, flags);
return;
} }
static int static int mpsc_startup(struct uart_port *port)
mpsc_startup(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
u32 flag = 0; u32 flag = 0;
...@@ -1439,15 +1357,14 @@ mpsc_startup(struct uart_port *port) ...@@ -1439,15 +1357,14 @@ mpsc_startup(struct uart_port *port)
pi->port.irq); pi->port.irq);
mpsc_sdma_intr_unmask(pi, 0xf); mpsc_sdma_intr_unmask(pi, 0xf);
mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p + mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
(pi->rxr_posn * MPSC_RXRE_SIZE))); + (pi->rxr_posn * MPSC_RXRE_SIZE)));
} }
return rc; return rc;
} }
static void static void mpsc_shutdown(struct uart_port *port)
mpsc_shutdown(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
...@@ -1455,11 +1372,9 @@ mpsc_shutdown(struct uart_port *port) ...@@ -1455,11 +1372,9 @@ mpsc_shutdown(struct uart_port *port)
mpsc_sdma_stop(pi); mpsc_sdma_stop(pi);
free_irq(pi->port.irq, pi); free_irq(pi->port.irq, pi);
return;
} }
static void static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old) struct ktermios *old)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
...@@ -1519,8 +1434,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios, ...@@ -1519,8 +1434,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
if (termios->c_iflag & INPCK) if (termios->c_iflag & INPCK)
pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
SDMA_DESC_CMDSTAT_FR; | SDMA_DESC_CMDSTAT_FR;
if (termios->c_iflag & (BRKINT | PARMRK)) if (termios->c_iflag & (BRKINT | PARMRK))
pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
...@@ -1529,8 +1444,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios, ...@@ -1529,8 +1444,8 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
pi->port.ignore_status_mask = 0; pi->port.ignore_status_mask = 0;
if (termios->c_iflag & IGNPAR) if (termios->c_iflag & IGNPAR)
pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
SDMA_DESC_CMDSTAT_FR; | SDMA_DESC_CMDSTAT_FR;
if (termios->c_iflag & IGNBRK) { if (termios->c_iflag & IGNBRK) {
pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
...@@ -1550,25 +1465,21 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios, ...@@ -1550,25 +1465,21 @@ mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
} }
spin_unlock_irqrestore(&pi->port.lock, flags); spin_unlock_irqrestore(&pi->port.lock, flags);
return;
} }
static const char * static const char *mpsc_type(struct uart_port *port)
mpsc_type(struct uart_port *port)
{ {
pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
return MPSC_DRIVER_NAME; return MPSC_DRIVER_NAME;
} }
static int static int mpsc_request_port(struct uart_port *port)
mpsc_request_port(struct uart_port *port)
{ {
/* Should make chip/platform specific call */ /* Should make chip/platform specific call */
return 0; return 0;
} }
static void static void mpsc_release_port(struct uart_port *port)
mpsc_release_port(struct uart_port *port)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
...@@ -1577,18 +1488,13 @@ mpsc_release_port(struct uart_port *port) ...@@ -1577,18 +1488,13 @@ mpsc_release_port(struct uart_port *port)
mpsc_free_ring_mem(pi); mpsc_free_ring_mem(pi);
pi->ready = 0; pi->ready = 0;
} }
return;
} }
static void static void mpsc_config_port(struct uart_port *port, int flags)
mpsc_config_port(struct uart_port *port, int flags)
{ {
return;
} }
static int static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
{ {
struct mpsc_port_info *pi = (struct mpsc_port_info *)port; struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
int rc = 0; int rc = 0;
...@@ -1641,8 +1547,7 @@ static struct uart_ops mpsc_pops = { ...@@ -1641,8 +1547,7 @@ static struct uart_ops mpsc_pops = {
*/ */
#ifdef CONFIG_SERIAL_MPSC_CONSOLE #ifdef CONFIG_SERIAL_MPSC_CONSOLE
static void static void mpsc_console_write(struct console *co, const char *s, uint count)
mpsc_console_write(struct console *co, const char *s, uint count)
{ {
struct mpsc_port_info *pi = &mpsc_ports[co->index]; struct mpsc_port_info *pi = &mpsc_ports[co->index];
u8 *bp, *dp, add_cr = 0; u8 *bp, *dp, add_cr = 0;
...@@ -1671,8 +1576,7 @@ mpsc_console_write(struct console *co, const char *s, uint count) ...@@ -1671,8 +1576,7 @@ mpsc_console_write(struct console *co, const char *s, uint count)
if (add_cr) { if (add_cr) {
*(dp++) = '\r'; *(dp++) = '\r';
add_cr = 0; add_cr = 0;
} } else {
else {
*(dp++) = *s; *(dp++) = *s;
if (*(s++) == '\n') { /* add '\r' after '\n' */ if (*(s++) == '\n') { /* add '\r' after '\n' */
...@@ -1684,7 +1588,8 @@ mpsc_console_write(struct console *co, const char *s, uint count) ...@@ -1684,7 +1588,8 @@ mpsc_console_write(struct console *co, const char *s, uint count)
count--; count--;
} }
dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
DMA_BIDIRECTIONAL);
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
flush_dcache_range((ulong)bp, flush_dcache_range((ulong)bp,
...@@ -1701,11 +1606,9 @@ mpsc_console_write(struct console *co, const char *s, uint count) ...@@ -1701,11 +1606,9 @@ mpsc_console_write(struct console *co, const char *s, uint count)
} }
spin_unlock_irqrestore(&pi->tx_lock, iflags); spin_unlock_irqrestore(&pi->tx_lock, iflags);
return;
} }
static int __init static int __init mpsc_console_setup(struct console *co, char *options)
mpsc_console_setup(struct console *co, char *options)
{ {
struct mpsc_port_info *pi; struct mpsc_port_info *pi;
int baud, bits, parity, flow; int baud, bits, parity, flow;
...@@ -1743,8 +1646,7 @@ static struct console mpsc_console = { ...@@ -1743,8 +1646,7 @@ static struct console mpsc_console = {
.data = &mpsc_reg, .data = &mpsc_reg,
}; };
static int __init static int __init mpsc_late_console_init(void)
mpsc_late_console_init(void)
{ {
pr_debug("mpsc_late_console_init: Enter\n"); pr_debug("mpsc_late_console_init: Enter\n");
...@@ -1766,40 +1668,37 @@ late_initcall(mpsc_late_console_init); ...@@ -1766,40 +1668,37 @@ late_initcall(mpsc_late_console_init);
* *
****************************************************************************** ******************************************************************************
*/ */
static void static void mpsc_resource_err(char *s)
mpsc_resource_err(char *s)
{ {
printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
return;
} }
static int static int mpsc_shared_map_regs(struct platform_device *pd)
mpsc_shared_map_regs(struct platform_device *pd)
{ {
struct resource *r; struct resource *r;
if ((r = platform_get_resource(pd, IORESOURCE_MEM, if ((r = platform_get_resource(pd, IORESOURCE_MEM,
MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start, MPSC_ROUTING_BASE_ORDER))
MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) { && request_mem_region(r->start,
MPSC_ROUTING_REG_BLOCK_SIZE,
"mpsc_routing_regs")) {
mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
MPSC_ROUTING_REG_BLOCK_SIZE); MPSC_ROUTING_REG_BLOCK_SIZE);
mpsc_shared_regs.mpsc_routing_base_p = r->start; mpsc_shared_regs.mpsc_routing_base_p = r->start;
} } else {
else {
mpsc_resource_err("MPSC routing base"); mpsc_resource_err("MPSC routing base");
return -ENOMEM; return -ENOMEM;
} }
if ((r = platform_get_resource(pd, IORESOURCE_MEM, if ((r = platform_get_resource(pd, IORESOURCE_MEM,
MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start, MPSC_SDMA_INTR_BASE_ORDER))
MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) { && request_mem_region(r->start,
MPSC_SDMA_INTR_REG_BLOCK_SIZE,
"sdma_intr_regs")) {
mpsc_shared_regs.sdma_intr_base = ioremap(r->start, mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
MPSC_SDMA_INTR_REG_BLOCK_SIZE); MPSC_SDMA_INTR_REG_BLOCK_SIZE);
mpsc_shared_regs.sdma_intr_base_p = r->start; mpsc_shared_regs.sdma_intr_base_p = r->start;
} } else {
else {
iounmap(mpsc_shared_regs.mpsc_routing_base); iounmap(mpsc_shared_regs.mpsc_routing_base);
release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
MPSC_ROUTING_REG_BLOCK_SIZE); MPSC_ROUTING_REG_BLOCK_SIZE);
...@@ -1810,8 +1709,7 @@ mpsc_shared_map_regs(struct platform_device *pd) ...@@ -1810,8 +1709,7 @@ mpsc_shared_map_regs(struct platform_device *pd)
return 0; return 0;
} }
static void static void mpsc_shared_unmap_regs(void)
mpsc_shared_unmap_regs(void)
{ {
if (!mpsc_shared_regs.mpsc_routing_base) { if (!mpsc_shared_regs.mpsc_routing_base) {
iounmap(mpsc_shared_regs.mpsc_routing_base); iounmap(mpsc_shared_regs.mpsc_routing_base);
...@@ -1829,19 +1727,17 @@ mpsc_shared_unmap_regs(void) ...@@ -1829,19 +1727,17 @@ mpsc_shared_unmap_regs(void)
mpsc_shared_regs.mpsc_routing_base_p = 0; mpsc_shared_regs.mpsc_routing_base_p = 0;
mpsc_shared_regs.sdma_intr_base_p = 0; mpsc_shared_regs.sdma_intr_base_p = 0;
return;
} }
static int static int mpsc_shared_drv_probe(struct platform_device *dev)
mpsc_shared_drv_probe(struct platform_device *dev)
{ {
struct mpsc_shared_pdata *pdata; struct mpsc_shared_pdata *pdata;
int rc = -ENODEV; int rc = -ENODEV;
if (dev->id == 0) { if (dev->id == 0) {
if (!(rc = mpsc_shared_map_regs(dev))) { if (!(rc = mpsc_shared_map_regs(dev))) {
pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data; pdata = (struct mpsc_shared_pdata *)
dev->dev.platform_data;
mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
...@@ -1858,8 +1754,7 @@ mpsc_shared_drv_probe(struct platform_device *dev) ...@@ -1858,8 +1754,7 @@ mpsc_shared_drv_probe(struct platform_device *dev)
return rc; return rc;
} }
static int static int mpsc_shared_drv_remove(struct platform_device *dev)
mpsc_shared_drv_remove(struct platform_device *dev)
{ {
int rc = -ENODEV; int rc = -ENODEV;
...@@ -1901,46 +1796,42 @@ static struct uart_driver mpsc_reg = { ...@@ -1901,46 +1796,42 @@ static struct uart_driver mpsc_reg = {
.cons = MPSC_CONSOLE, .cons = MPSC_CONSOLE,
}; };
static int static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) struct platform_device *pd)
{ {
struct resource *r; struct resource *r;
if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) && if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){ && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
"mpsc_regs")) {
pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
pi->mpsc_base_p = r->start; pi->mpsc_base_p = r->start;
} } else {
else {
mpsc_resource_err("MPSC base"); mpsc_resource_err("MPSC base");
return -ENOMEM; goto err;
} }
if ((r = platform_get_resource(pd, IORESOURCE_MEM, if ((r = platform_get_resource(pd, IORESOURCE_MEM,
MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start, MPSC_SDMA_BASE_ORDER))
&& request_mem_region(r->start,
MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
pi->sdma_base_p = r->start; pi->sdma_base_p = r->start;
} } else {
else {
mpsc_resource_err("SDMA base"); mpsc_resource_err("SDMA base");
if (pi->mpsc_base) { if (pi->mpsc_base) {
iounmap(pi->mpsc_base); iounmap(pi->mpsc_base);
pi->mpsc_base = NULL; pi->mpsc_base = NULL;
} }
return -ENOMEM; goto err;
} }
if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
&& request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE, && request_mem_region(r->start,
"brg_regs")) { MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
pi->brg_base_p = r->start; pi->brg_base_p = r->start;
} } else {
else {
mpsc_resource_err("BRG base"); mpsc_resource_err("BRG base");
if (pi->mpsc_base) { if (pi->mpsc_base) {
iounmap(pi->mpsc_base); iounmap(pi->mpsc_base);
...@@ -1950,14 +1841,15 @@ mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) ...@@ -1950,14 +1841,15 @@ mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd)
iounmap(pi->sdma_base); iounmap(pi->sdma_base);
pi->sdma_base = NULL; pi->sdma_base = NULL;
} }
return -ENOMEM; goto err;
} }
return 0; return 0;
err:
return -ENOMEM;
} }
static void static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
{ {
if (!pi->mpsc_base) { if (!pi->mpsc_base) {
iounmap(pi->mpsc_base); iounmap(pi->mpsc_base);
...@@ -1979,12 +1871,9 @@ mpsc_drv_unmap_regs(struct mpsc_port_info *pi) ...@@ -1979,12 +1871,9 @@ mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
pi->mpsc_base_p = 0; pi->mpsc_base_p = 0;
pi->sdma_base_p = 0; pi->sdma_base_p = 0;
pi->brg_base_p = 0; pi->brg_base_p = 0;
return;
} }
static void static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
struct platform_device *pd, int num) struct platform_device *pd, int num)
{ {
struct mpsc_pdata *pdata; struct mpsc_pdata *pdata;
...@@ -2020,12 +1909,9 @@ mpsc_drv_get_platform_data(struct mpsc_port_info *pi, ...@@ -2020,12 +1909,9 @@ mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
pi->shared_regs = &mpsc_shared_regs; pi->shared_regs = &mpsc_shared_regs;
pi->port.irq = platform_get_irq(pd, 0); pi->port.irq = platform_get_irq(pd, 0);
return;
} }
static int static int mpsc_drv_probe(struct platform_device *dev)
mpsc_drv_probe(struct platform_device *dev)
{ {
struct mpsc_port_info *pi; struct mpsc_port_info *pi;
int rc = -ENODEV; int rc = -ENODEV;
...@@ -2041,35 +1927,35 @@ mpsc_drv_probe(struct platform_device *dev) ...@@ -2041,35 +1927,35 @@ mpsc_drv_probe(struct platform_device *dev)
if (!(rc = mpsc_make_ready(pi))) { if (!(rc = mpsc_make_ready(pi))) {
spin_lock_init(&pi->tx_lock); spin_lock_init(&pi->tx_lock);
if (!(rc = uart_add_one_port(&mpsc_reg, if (!(rc = uart_add_one_port(&mpsc_reg,
&pi->port))) &pi->port))) {
rc = 0; rc = 0;
else { } else {
mpsc_release_port( mpsc_release_port((struct uart_port *)
(struct uart_port *)pi); pi);
mpsc_drv_unmap_regs(pi); mpsc_drv_unmap_regs(pi);
} }
} } else {
else
mpsc_drv_unmap_regs(pi); mpsc_drv_unmap_regs(pi);
} }
} }
}
return rc; return rc;
} }
static int static int mpsc_drv_remove(struct platform_device *dev)
mpsc_drv_remove(struct platform_device *dev)
{ {
pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id); pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
if (dev->id < MPSC_NUM_CTLRS) { if (dev->id < MPSC_NUM_CTLRS) {
uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port); uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port); mpsc_release_port((struct uart_port *)
&mpsc_ports[dev->id].port);
mpsc_drv_unmap_regs(&mpsc_ports[dev->id]); mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
return 0; return 0;
} } else {
else
return -ENODEV; return -ENODEV;
}
} }
static struct platform_driver mpsc_driver = { static struct platform_driver mpsc_driver = {
...@@ -2080,8 +1966,7 @@ static struct platform_driver mpsc_driver = { ...@@ -2080,8 +1966,7 @@ static struct platform_driver mpsc_driver = {
}, },
}; };
static int __init static int __init mpsc_drv_init(void)
mpsc_drv_init(void)
{ {
int rc; int rc;
...@@ -2096,24 +1981,21 @@ mpsc_drv_init(void) ...@@ -2096,24 +1981,21 @@ mpsc_drv_init(void)
platform_driver_unregister(&mpsc_shared_driver); platform_driver_unregister(&mpsc_shared_driver);
uart_unregister_driver(&mpsc_reg); uart_unregister_driver(&mpsc_reg);
} }
} } else {
else
uart_unregister_driver(&mpsc_reg); uart_unregister_driver(&mpsc_reg);
} }
}
return rc; return rc;
} }
static void __exit static void __exit mpsc_drv_exit(void)
mpsc_drv_exit(void)
{ {
platform_driver_unregister(&mpsc_driver); platform_driver_unregister(&mpsc_driver);
platform_driver_unregister(&mpsc_shared_driver); platform_driver_unregister(&mpsc_shared_driver);
uart_unregister_driver(&mpsc_reg); uart_unregister_driver(&mpsc_reg);
memset(mpsc_ports, 0, sizeof(mpsc_ports)); memset(mpsc_ports, 0, sizeof(mpsc_ports));
memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
return;
} }
module_init(mpsc_drv_init); module_init(mpsc_drv_init);
......
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