Commit 2f4c95dc authored by Neil Armstrong's avatar Neil Armstrong

drm/meson: add support for HDMI clock support

This patchs adds support for the supported HDMI modes clocks frequencies.
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent cb110b66
This diff is collapsed.
......@@ -23,12 +23,14 @@
enum {
MESON_VCLK_TARGET_CVBS = 0,
MESON_VCLK_TARGET_HDMI = 1,
};
/* 27MHz is the CVBS Pixel Clock */
#define MESON_VCLK_CVBS 27000
void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
unsigned int freq);
unsigned int vclk_freq, unsigned int venc_freq,
unsigned int dac_freq, bool hdmi_use_enci);
#endif /* __MESON_VCLK_H */
......@@ -32,6 +32,7 @@
#include "meson_venc_cvbs.h"
#include "meson_venc.h"
#include "meson_vclk.h"
#include "meson_registers.h"
/* HHI VDAC Registers */
......@@ -194,14 +195,20 @@ static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder,
{
struct meson_venc_cvbs *meson_venc_cvbs =
encoder_to_meson_venc_cvbs(encoder);
struct meson_drm *priv = meson_venc_cvbs->priv;
int i;
for (i = 0; i < MESON_CVBS_MODES_COUNT; ++i) {
struct meson_cvbs_mode *meson_mode = &meson_cvbs_modes[i];
if (drm_mode_equal(mode, &meson_mode->mode)) {
meson_venci_cvbs_mode_set(meson_venc_cvbs->priv,
meson_venci_cvbs_mode_set(priv,
meson_mode->enci);
/* Setup 27MHz vclk2 for ENCI and VDAC */
meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
MESON_VCLK_CVBS, MESON_VCLK_CVBS,
MESON_VCLK_CVBS, true);
break;
}
}
......
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