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Commit 2f751a80 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller
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bnx2x: Cosmetic changes 

Fix spelling, alignment, empty lines, relocate the is_4_port_mode function, and split bnx2x_link_status_update function.
Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 32911333
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Showing with 199 additions and 216 deletions
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
View file @ 2f751a80
...@@ -352,7 +352,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ...@@ -352,7 +352,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
DP(NETIF_MSG_LINK, "Unsupported port type\n"); DP(NETIF_MSG_LINK, "Unsupported port type\n");
return -EINVAL; return -EINVAL;
} }
/* Save new config in case command complete successuly */ /* Save new config in case command complete successully */
new_multi_phy_config = bp->link_params.multi_phy_config; new_multi_phy_config = bp->link_params.multi_phy_config;
/* Get the new cfg_idx */ /* Get the new cfg_idx */
cfg_idx = bnx2x_get_link_cfg_idx(bp); cfg_idx = bnx2x_get_link_cfg_idx(bp);
......
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
View file @ 2f751a80
...@@ -27,7 +27,6 @@ ...@@ -27,7 +27,6 @@
#include "bnx2x.h" #include "bnx2x.h"
#include "bnx2x_cmn.h" #include "bnx2x_cmn.h"
/********************************************************/ /********************************************************/
#define ETH_HLEN 14 #define ETH_HLEN 14
/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
...@@ -255,7 +254,6 @@ ...@@ -255,7 +254,6 @@
#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
/* only for E3B0*/ /* only for E3B0*/
#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
...@@ -906,12 +904,12 @@ static int bnx2x_ets_e3b0_get_total_bw( ...@@ -906,12 +904,12 @@ static int bnx2x_ets_e3b0_get_total_bw(
if ((1 == is_bw_cos_exist) && (100 != *total_bw)) { if ((1 == is_bw_cos_exist) && (100 != *total_bw)) {
if (0 == *total_bw) { if (0 == *total_bw) {
DP(NETIF_MSG_LINK, DP(NETIF_MSG_LINK,
"bnx2x_ets_E3B0_config toatl BW shouldn't be 0\n"); "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
return -EINVAL; return -EINVAL;
} }
DP(NETIF_MSG_LINK, DP(NETIF_MSG_LINK,
"bnx2x_ets_E3B0_config toatl BW should be 100\n"); "bnx2x_ets_E3B0_config total BW should be 100\n");
/** /*
* We can handle a case whre the BW isn't 100 this can happen * We can handle a case whre the BW isn't 100 this can happen
* if the TC are joined. * if the TC are joined.
*/ */
...@@ -1152,7 +1150,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params, ...@@ -1152,7 +1150,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
return -EINVAL; return -EINVAL;
} }
/** /*
* Upper bound is set according to current link speed (min_w_val * Upper bound is set according to current link speed (min_w_val
* should be the same for upper bound and COS credit val). * should be the same for upper bound and COS credit val).
*/ */
...@@ -1163,7 +1161,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params, ...@@ -1163,7 +1161,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
cos_bw_bitmap |= (1 << cos_entry); cos_bw_bitmap |= (1 << cos_entry);
/** /*
* The function also sets the BW in HW(not the mappin * The function also sets the BW in HW(not the mappin
* yet) * yet)
*/ */
...@@ -1339,7 +1337,6 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) ...@@ -1339,7 +1337,6 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
/******************************************************************/ /******************************************************************/
/* PFC section */ /* PFC section */
/******************************************************************/ /******************************************************************/
static void bnx2x_update_pfc_xmac(struct link_params *params, static void bnx2x_update_pfc_xmac(struct link_params *params,
struct link_vars *vars, struct link_vars *vars,
u8 is_lb) u8 is_lb)
...@@ -1476,6 +1473,18 @@ static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) ...@@ -1476,6 +1473,18 @@ static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
udelay(40); udelay(40);
} }
static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
{
u32 port4mode_ovwr_val;
/* Check 4-port override enabled */
port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
if (port4mode_ovwr_val & (1<<0)) {
/* Return 4-port mode override value */
return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
}
/* Return 4-port mode from input pin */
return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
}
static void bnx2x_emac_init(struct link_params *params, static void bnx2x_emac_init(struct link_params *params,
struct link_vars *vars) struct link_vars *vars)
...@@ -1642,31 +1651,18 @@ static void bnx2x_umac_enable(struct link_params *params, ...@@ -1642,31 +1651,18 @@ static void bnx2x_umac_enable(struct link_params *params,
} }
static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
{
u32 port4mode_ovwr_val;
/* Check 4-port override enabled */
port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
if (port4mode_ovwr_val & (1<<0)) {
/* Return 4-port mode override value */
return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
}
/* Return 4-port mode from input pin */
return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
}
/* Define the XMAC mode */ /* Define the XMAC mode */
static void bnx2x_xmac_init(struct link_params *params, u32 max_speed) static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
{ {
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
u32 is_port4mode = bnx2x_is_4_port_mode(bp); u32 is_port4mode = bnx2x_is_4_port_mode(bp);
/** /*
* In 4-port mode, need to set the mode only once, so if XMAC is * In 4-port mode, need to set the mode only once, so if XMAC is
* already out of reset, it means the mode has already been set, * already out of reset, it means the mode has already been set,
* and it must not* reset the XMAC again, since it controls both * and it must not* reset the XMAC again, since it controls both
* ports of the path * ports of the path
**/ */
if ((CHIP_NUM(bp) == CHIP_NUM_57840) && if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
(REG_RD(bp, MISC_REG_RESET_REG_2) & (REG_RD(bp, MISC_REG_RESET_REG_2) &
...@@ -1784,6 +1780,7 @@ static int bnx2x_xmac_enable(struct link_params *params, ...@@ -1784,6 +1780,7 @@ static int bnx2x_xmac_enable(struct link_params *params,
return 0; return 0;
} }
static int bnx2x_emac_enable(struct link_params *params, static int bnx2x_emac_enable(struct link_params *params,
struct link_vars *vars, u8 lb) struct link_vars *vars, u8 lb)
{ {
...@@ -2040,7 +2037,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params, ...@@ -2040,7 +2037,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
} }
/* PFC BRB internal port configuration params */ /* PFC BRB internal port configuration params */
struct bnx2x_pfc_brb_threshold_val { struct bnx2x_pfc_brb_threshold_val {
u32 pause_xoff; u32 pause_xoff;
...@@ -2337,10 +2333,11 @@ static int bnx2x_update_pfc_brb(struct link_params *params, ...@@ -2337,10 +2333,11 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
/* /*
* The number of free blocks below which the pause signal to * The number of free blocks below which the pause signal to
* class 1 of MAC #n is asserted. n=0,1 * class 1 of MAC #n is asserted. n=0,1
**/ */
REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 : REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
reg_th_config->pause_xoff); reg_th_config->pause_xoff);
/* /*
* The number of free blocks above which the pause signal to * The number of free blocks above which the pause signal to
* class 1 of MAC #n is de-asserted. n=0,1 * class 1 of MAC #n is de-asserted. n=0,1
...@@ -2370,56 +2367,51 @@ static int bnx2x_update_pfc_brb(struct link_params *params, ...@@ -2370,56 +2367,51 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
pfc_params, pfc_params,
pfc_enabled); pfc_enabled);
/*Should be done by init tool */
/*
* BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
* reset value
* 944
*/
REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE, REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
e3b0_val.per_class_guaranty_mode); e3b0_val.per_class_guaranty_mode);
/** /*
* The hysteresis on the guarantied buffer space for the Lb port * The hysteresis on the guarantied buffer space for the Lb
* before signaling XON. * port before signaling XON.
**/ */
REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
e3b0_val.lb_guarantied_hyst); e3b0_val.lb_guarantied_hyst);
/**
/*
* The number of free blocks below which the full signal to the * The number of free blocks below which the full signal to the
* LB port is asserted. * LB port is asserted.
*/ */
REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
e3b0_val.full_lb_xoff_th); e3b0_val.full_lb_xoff_th);
/** /*
* The number of free blocks above which the full signal to the * The number of free blocks above which the full signal to the
* LB port is de-asserted. * LB port is de-asserted.
*/ */
REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
e3b0_val.full_lb_xon_threshold); e3b0_val.full_lb_xon_threshold);
/** /*
* The number of blocks guarantied for the MAC #n port. n=0,1 * The number of blocks guarantied for the MAC #n port. n=0,1
*/ */
/*The number of blocks guarantied for the LB port.*/ /* The number of blocks guarantied for the LB port.*/
REG_WR(bp, BRB1_REG_LB_GUARANTIED, REG_WR(bp, BRB1_REG_LB_GUARANTIED,
e3b0_val.lb_guarantied); e3b0_val.lb_guarantied);
/** /*
* The number of blocks guarantied for the MAC #n port. * The number of blocks guarantied for the MAC #n port.
*/ */
REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0, REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2 * e3b0_val.mac_0_class_t_guarantied); 2 * e3b0_val.mac_0_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1, REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2 * e3b0_val.mac_1_class_t_guarantied); 2 * e3b0_val.mac_1_class_t_guarantied);
/** /*
* The number of blocks guarantied for class #t in MAC0. t=0,1 * The number of blocks guarantied for class #t in MAC0. t=0,1
*/ */
REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED, REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
e3b0_val.mac_0_class_t_guarantied); e3b0_val.mac_0_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED, REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
e3b0_val.mac_0_class_t_guarantied); e3b0_val.mac_0_class_t_guarantied);
/** /*
* The hysteresis on the guarantied buffer space for class in * The hysteresis on the guarantied buffer space for class in
* MAC0. t=0,1 * MAC0. t=0,1
*/ */
...@@ -2428,14 +2420,14 @@ static int bnx2x_update_pfc_brb(struct link_params *params, ...@@ -2428,14 +2420,14 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST, REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
e3b0_val.mac_0_class_t_guarantied_hyst); e3b0_val.mac_0_class_t_guarantied_hyst);
/** /*
* The number of blocks guarantied for class #t in MAC1.t=0,1 * The number of blocks guarantied for class #t in MAC1.t=0,1
*/ */
REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED, REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
e3b0_val.mac_1_class_t_guarantied); e3b0_val.mac_1_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED, REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
e3b0_val.mac_1_class_t_guarantied); e3b0_val.mac_1_class_t_guarantied);
/** /*
* The hysteresis on the guarantied buffer space for class #t * The hysteresis on the guarantied buffer space for class #t
* in MAC1. t=0,1 * in MAC1. t=0,1
*/ */
...@@ -2443,7 +2435,6 @@ static int bnx2x_update_pfc_brb(struct link_params *params, ...@@ -2443,7 +2435,6 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
e3b0_val.mac_1_class_t_guarantied_hyst); e3b0_val.mac_1_class_t_guarantied_hyst);
REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST, REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
e3b0_val.mac_1_class_t_guarantied_hyst); e3b0_val.mac_1_class_t_guarantied_hyst);
} }
return bnx2x_status; return bnx2x_status;
...@@ -2646,7 +2637,6 @@ int bnx2x_update_pfc(struct link_params *params, ...@@ -2646,7 +2637,6 @@ int bnx2x_update_pfc(struct link_params *params,
bnx2x_emac_enable(params, vars, 0); bnx2x_emac_enable(params, vars, 0);
return bnx2x_status; return bnx2x_status;
} }
if (CHIP_IS_E2(bp)) if (CHIP_IS_E2(bp))
bnx2x_update_pfc_bmac2(params, vars, bmac_loopback); bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
else else
...@@ -3166,7 +3156,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, ...@@ -3166,7 +3156,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "write phy register failed\n"); DP(NETIF_MSG_LINK, "write phy register failed\n");
netdev_err(bp->dev, "MDC/MDIO access timeout\n"); netdev_err(bp->dev, "MDC/MDIO access timeout\n");
rc = -EFAULT; rc = -EFAULT;
} else { } else {
/* data */ /* data */
tmp = ((phy->addr << 21) | (devad << 16) | val | tmp = ((phy->addr << 21) | (devad << 16) | val |
...@@ -3203,8 +3192,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, ...@@ -3203,8 +3192,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
EMAC_MDIO_STATUS_10MB); EMAC_MDIO_STATUS_10MB);
return rc; return rc;
} }
/******************************************************************/ /******************************************************************/
/* BSC access functions from E3 */ /* BSC access functions from E3 */
/******************************************************************/ /******************************************************************/
...@@ -3452,7 +3439,7 @@ static void bnx2x_set_aer_mmd(struct link_params *params, ...@@ -3452,7 +3439,7 @@ static void bnx2x_set_aer_mmd(struct link_params *params,
aer_val = 0x3800 + offset - 1; aer_val = 0x3800 + offset - 1;
else else
aer_val = 0x3800 + offset; aer_val = 0x3800 + offset;
DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, aer_val); MDIO_AER_BLOCK_AER_REG, aer_val);
...@@ -4154,9 +4141,7 @@ static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, ...@@ -4154,9 +4141,7 @@ static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_MISC6, &val); MDIO_WC_REG_DIGITAL5_MISC6, &val);
} }
/* Clear SFI/XFI link settings registers */
/* Clear SFI/XFI link settings registers */
static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
struct link_params *params, struct link_params *params,
u16 lane) u16 lane)
...@@ -4557,25 +4542,14 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy, ...@@ -4557,25 +4542,14 @@ static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
} }
void bnx2x_link_status_update(struct link_params *params, void bnx2x_sync_link(struct link_params *params,
struct link_vars *vars) struct link_vars *vars)
{ {
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
u8 link_10g_plus; u8 link_10g_plus;
u8 port = params->port;
u32 sync_offset, media_types;
/* Update PHY configuration */
set_phy_vars(params, vars);
vars->link_status = REG_RD(bp, params->shmem_base +
offsetof(struct shmem_region,
port_mb[port].link_status));
vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
vars->phy_flags = PHY_XGXS_FLAG;
if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
if (vars->link_up) { if (vars->link_up) {
DP(NETIF_MSG_LINK, "phy link up\n"); DP(NETIF_MSG_LINK, "phy link up\n");
...@@ -4670,7 +4644,23 @@ void bnx2x_link_status_update(struct link_params *params, ...@@ -4670,7 +4644,23 @@ void bnx2x_link_status_update(struct link_params *params,
if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
} }
}
void bnx2x_link_status_update(struct link_params *params,
struct link_vars *vars)
{
struct bnx2x *bp = params->bp;
u8 port = params->port;
u32 sync_offset, media_types;
/* Update PHY configuration */
set_phy_vars(params, vars);
vars->link_status = REG_RD(bp, params->shmem_base +
offsetof(struct shmem_region,
port_mb[port].link_status));
vars->phy_flags = PHY_XGXS_FLAG;
bnx2x_sync_link(params, vars);
/* Sync media type */ /* Sync media type */
sync_offset = params->shmem_base + sync_offset = params->shmem_base +
offsetof(struct shmem_region, offsetof(struct shmem_region,
...@@ -4709,7 +4699,6 @@ void bnx2x_link_status_update(struct link_params *params, ...@@ -4709,7 +4699,6 @@ void bnx2x_link_status_update(struct link_params *params,
vars->line_speed, vars->duplex, vars->flow_ctrl); vars->line_speed, vars->duplex, vars->flow_ctrl);
} }
static void bnx2x_set_master_ln(struct link_params *params, static void bnx2x_set_master_ln(struct link_params *params,
struct bnx2x_phy *phy) struct bnx2x_phy *phy)
{ {
...@@ -4783,11 +4772,8 @@ static void bnx2x_set_swap_lanes(struct link_params *params, ...@@ -4783,11 +4772,8 @@ static void bnx2x_set_swap_lanes(struct link_params *params,
* Each two bits represents a lane number: * Each two bits represents a lane number:
* No swap is 0123 => 0x1b no need to enable the swap * No swap is 0123 => 0x1b no need to enable the swap
*/ */
u16 ser_lane, rx_lane_swap, tx_lane_swap; u16 rx_lane_swap, tx_lane_swap;
ser_lane = ((params->lane_config &
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
rx_lane_swap = ((params->lane_config & rx_lane_swap = ((params->lane_config &
PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
...@@ -5463,7 +5449,6 @@ static int bnx2x_link_settings_status(struct bnx2x_phy *phy, ...@@ -5463,7 +5449,6 @@ static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
struct link_params *params, struct link_params *params,
struct link_vars *vars) struct link_vars *vars)
{ {
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
...@@ -5510,9 +5495,7 @@ static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy, ...@@ -5510,9 +5495,7 @@ static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
struct link_params *params, struct link_params *params,
struct link_vars *vars) struct link_vars *vars)
{ {
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
u8 lane; u8 lane;
u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
int rc = 0; int rc = 0;
...@@ -6785,7 +6768,6 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars) ...@@ -6785,7 +6768,6 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
return rc; return rc;
} }
/*****************************************************************************/ /*****************************************************************************/
/* External Phy section */ /* External Phy section */
/*****************************************************************************/ /*****************************************************************************/
...@@ -9155,13 +9137,13 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, ...@@ -9155,13 +9137,13 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, DP(NETIF_MSG_LINK,
"8727 Power fault has been detected on port %d\n", "8727 Power fault has been detected on port %d\n",
oc_port); oc_port);
netdev_err(bp->dev, "Error: Power fault on Port %d has" netdev_err(bp->dev, "Error: Power fault on Port %d has "
" been detected and the power to " "been detected and the power to "
"that SFP+ module has been removed" "that SFP+ module has been removed "
" to prevent failure of the card." "to prevent failure of the card. "
" Please remove the SFP+ module and" "Please remove the SFP+ module and "
" restart the system to clear this" "restart the system to clear this "
" error.\n", "error.\n",
oc_port); oc_port);
/* Disable all RX_ALARMs except for mod_abs */ /* Disable all RX_ALARMs except for mod_abs */
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
...@@ -10234,8 +10216,10 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy, ...@@ -10234,8 +10216,10 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "54618SE cfg init\n"); DP(NETIF_MSG_LINK, "54618SE cfg init\n");
usleep_range(1000, 1000); usleep_range(1000, 1000);
/* This works with E3 only, no need to check the chip /*
before determining the port. */ * This works with E3 only, no need to check the chip
* before determining the port.
*/
port = params->port; port = params->port;
cfg_pin = (REG_RD(bp, params->shmem_base + cfg_pin = (REG_RD(bp, params->shmem_base +
...@@ -11666,7 +11650,7 @@ u32 bnx2x_phy_selection(struct link_params *params) ...@@ -11666,7 +11650,7 @@ u32 bnx2x_phy_selection(struct link_params *params)
int bnx2x_phy_probe(struct link_params *params) int bnx2x_phy_probe(struct link_params *params)
{ {
u8 phy_index, actual_phy_idx, link_cfg_idx; u8 phy_index, actual_phy_idx;
u32 phy_config_swapped, sync_offset, media_types; u32 phy_config_swapped, sync_offset, media_types;
struct bnx2x *bp = params->bp; struct bnx2x *bp = params->bp;
struct bnx2x_phy *phy; struct bnx2x_phy *phy;
...@@ -11677,7 +11661,6 @@ int bnx2x_phy_probe(struct link_params *params) ...@@ -11677,7 +11661,6 @@ int bnx2x_phy_probe(struct link_params *params)
for (phy_index = INT_PHY; phy_index < MAX_PHYS; for (phy_index = INT_PHY; phy_index < MAX_PHYS;
phy_index++) { phy_index++) {
link_cfg_idx = LINK_CONFIG_IDX(phy_index);
actual_phy_idx = phy_index; actual_phy_idx = phy_index;
if (phy_config_swapped) { if (phy_config_swapped) {
if (phy_index == EXT_PHY1) if (phy_index == EXT_PHY1)
......
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