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Commit 302c9454 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'uniphier/dt' into arm/dt 

Updates from Kunihiko Hayashi via email:

 "Update devicetree sources for UniPhier armv8 SoCs to remove dtschema
  warnings, add support existing features that haven't yet been
  described, and replace constants with macros."

* uniphier/dt:
  arm64: dts: uniphier: Add L2 cache node
  arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node
  arm64: dts: uniphier: Fix opp-table node name for LD20
  arm64: dts: uniphier: Add USB-device support for PXs3 reference board
  arm64: dts: uniphier: Add ahci controller nodes for PXs3
  arm64: dts: uniphier: Use GIC interrupt definitions
  arm64: dts: uniphier: Rename gpio-hog nodes
  arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
  arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
  arm64: dts: uniphier: Rename pvtctl node to thermal-sensor
  ARM: dts: uniphier: Remove compatible "snps,dw-pcie-ep" from pcie-ep node
  ARM: dts: uniphier: Move interrupt-parent property to each child node in uniphier-support-card
  ARM: dts: uniphier: Add ahci controller nodes for PXs2
  ARM: dts: uniphier: Add ahci controller nodes for Pro4
  ARM: dts: uniphier: Use GIC interrupt definitions
  ARM: dts: uniphier: Rename gpio-hog node
  ARM: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
  ARM: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
  ARM: dts: uniphier: Rename pvtctl node to thermal-sensor
parents 3ba2d4bb 5381a96c
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Showing with 651 additions and 240 deletions
arch/arm/boot/dts/uniphier-ld4-ref.dts
View file @ 302c9454
......@@ -36,11 +36,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <1 8>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <1 8>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -56,7 +56,7 @@ &serial3 {
};
&gpio {
xirq1 {
xirq1-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
input;
......
arch/arm/boot/dts/uniphier-ld4.dtsi
View file @ 302c9454
......@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld4";
......@@ -55,7 +56,8 @@ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
......@@ -69,7 +71,7 @@ spi: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -80,7 +82,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -91,7 +93,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -102,7 +104,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -113,7 +115,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 29 4>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -140,7 +142,7 @@ i2c0: i2c@58400000 {
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -154,7 +156,7 @@ i2c1: i2c@58480000 {
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -168,7 +170,7 @@ i2c2: i2c@58500000 {
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -182,7 +184,7 @@ i2c3: i2c@58580000 {
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -240,8 +242,13 @@ peri_rst: reset {
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
......@@ -251,7 +258,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......@@ -271,7 +278,7 @@ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
......@@ -289,7 +296,7 @@ usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
......@@ -303,7 +310,7 @@ usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
......@@ -317,7 +324,7 @@ usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
......@@ -358,14 +365,16 @@ efuse@130 {
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
interrupts = <GIC_PPI 11
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
......@@ -407,7 +416,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm/boot/dts/uniphier-ld6b-ref.dts
View file @ 302c9454
......@@ -40,11 +40,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <4 8>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <4 8>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -60,7 +60,7 @@ &serial2 {
};
&gpio {
xirq4 {
xirq4-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
input;
......
arch/arm/boot/dts/uniphier-pinctrl.dtsi
View file @ 302c9454
......@@ -196,11 +196,21 @@ pinctrl_usb0: usb0 {
function = "usb0";
};
pinctrl_usb0_device: usb0-device {
groups = "usb0_device";
function = "usb0";
};
pinctrl_usb1: usb1 {
groups = "usb1";
function = "usb1";
};
pinctrl_usb1_device: usb1-device {
groups = "usb1_device";
function = "usb1";
};
pinctrl_usb2: usb2 {
groups = "usb2";
function = "usb2";
......
arch/arm/boot/dts/uniphier-pro4-ace.dts
View file @ 302c9454
......@@ -99,3 +99,11 @@ &usb0 {
&usb1 {
status = "okay";
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
arch/arm/boot/dts/uniphier-pro4-ref.dts
View file @ 302c9454
......@@ -39,11 +39,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <2 8>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <2 8>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -59,7 +59,7 @@ &serial2 {
};
&gpio {
xirq2 {
xirq2-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
input;
......@@ -108,3 +108,11 @@ nand@0 {
reg = <0>;
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
arch/arm/boot/dts/uniphier-pro4.dtsi
View file @ 302c9454
......@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-pro4";
......@@ -63,7 +64,8 @@ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(768 * 1024)>;
cache-sets = <256>;
......@@ -77,7 +79,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -88,7 +90,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -99,7 +101,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -110,7 +112,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -121,7 +123,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -148,7 +150,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -162,7 +164,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -176,7 +178,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -190,7 +192,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -206,7 +208,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
......@@ -218,7 +220,7 @@ i2c6: i2c@58786000 {
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
......@@ -274,8 +276,14 @@ peri_rst: reset {
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
......@@ -285,7 +293,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......@@ -305,7 +313,7 @@ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
......@@ -323,7 +331,7 @@ sd1: mmc@5a600000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a600000 0x200>;
interrupts = <0 85 4>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
clocks = <&mio_clk 2>;
......@@ -339,7 +347,7 @@ usb2: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
......@@ -355,7 +363,7 @@ usb3: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
......@@ -376,7 +384,7 @@ pinctrl: pinctrl {
compatible = "socionext,uniphier-pro4-pinctrl";
};
usb-phy {
usb-controller {
compatible = "socionext,uniphier-pro4-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
......@@ -403,6 +411,11 @@ usb_phy3: phy@3 {
vbus-supply = <&usb1_vbus>;
};
};
sg_clk: clock {
compatible = "socionext,uniphier-pro4-sg-clock";
#clock-cells = <1>;
};
};
soc-glue@5f900000 {
......@@ -431,7 +444,7 @@ efuse@200 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -446,14 +459,16 @@ aidet: interrupt-controller@5fc20000 {
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x304>;
interrupts = <GIC_PPI 11
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x304>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
......@@ -485,7 +500,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-pro4-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "gio", "ether", "ether-gb", "ether-phy";
......@@ -503,12 +518,105 @@ mdio: mdio {
};
};
ahci0: sata@65600000 {
compatible = "socionext,uniphier-pro4-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65600000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 12>, <&sys_clk 28>;
resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
ports-implemented = <1>;
phys = <&ahci0_phy>;
assigned-clocks = <&sg_clk 0>;
assigned-clock-rates = <25000000>;
};
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro4-ahci-reset";
reg = <0x0 0x4>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 28>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 28>;
#reset-cells = <1>;
};
ahci0_phy: sata-phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
clocks = <&sys_clk 28>, <&sys_clk 12>;
reset-names = "link", "gio", "phy",
"pm", "tx", "rx";
resets = <&sys_rst 28>, <&sys_rst 12>,
<&sys_rst 30>,
<&ahci0_rst 0>, <&ahci0_rst 1>,
<&ahci0_rst 2>;
#phy-cells = <0>;
};
};
ahci1: sata@65800000 {
compatible = "socionext,uniphier-pro4-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65800000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 12>, <&sys_clk 29>;
resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
ports-implemented = <1>;
phys = <&ahci1_phy>;
assigned-clocks = <&sg_clk 0>;
assigned-clock-rates = <25000000>;
};
sata-controller@65900000 {
compatible = "socionext,uniphier-pro4-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65900000 0x100>;
ahci1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro4-ahci-reset";
reg = <0x0 0x4>;
clock-names = "gio", "link";
clocks = <&sys_clk 12>, <&sys_clk 29>;
reset-names = "gio", "link";
resets = <&sys_rst 12>, <&sys_rst 29>;
#reset-cells = <1>;
};
ahci1_phy: sata-phy@10 {
compatible = "socionext,uniphier-pro4-ahci-phy";
reg = <0x10 0x40>;
clock-names = "link", "gio";
clocks = <&sys_clk 29>, <&sys_clk 12>;
reset-names = "link", "gio", "phy",
"pm", "tx", "rx";
resets = <&sys_rst 29>, <&sys_rst 12>,
<&sys_rst 30>,
<&ahci1_rst 0>, <&ahci1_rst 1>,
<&ahci1_rst 2>;
#phy-cells = <0>;
};
};
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host", "peripheral";
interrupts = <0 134 4>, <0 135 4>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
......@@ -518,7 +626,7 @@ usb0: usb@65a00000 {
dr_mode = "host";
};
usb-glue@65b00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -561,7 +669,8 @@ usb1: usb@65c00000 {
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host", "peripheral";
interrupts = <0 137 4>, <0 138 4>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clock-names = "ref", "bus_early", "suspend";
......@@ -571,7 +680,7 @@ usb1: usb@65c00000 {
dr_mode = "host";
};
usb-glue@65d00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pro4-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -605,7 +714,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm/boot/dts/uniphier-pro5.dtsi
View file @ 302c9454
......@@ -5,6 +5,8 @@
// Copyright (C) 2015-2016 Socionext Inc.
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-pro5";
#address-cells = <1>;
......@@ -135,7 +137,8 @@ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
interrupts = <0 190 4>, <0 191 4>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
......@@ -148,7 +151,8 @@ l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
......@@ -162,7 +166,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -175,7 +179,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 216 4>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 11>; /* common with spi0 */
......@@ -186,7 +190,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -197,7 +201,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -208,7 +212,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -219,7 +223,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -246,7 +250,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -260,7 +264,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -274,7 +278,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -288,7 +292,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -304,7 +308,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
......@@ -316,7 +320,7 @@ i2c6: i2c@58786000 {
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
......@@ -415,7 +419,7 @@ efuse@400 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -430,14 +434,16 @@ aidet: interrupt-controller@5fc20000 {
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x304>;
interrupts = <GIC_PPI 11
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x304>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
......@@ -470,7 +476,7 @@ usb0: usb@65a00000 {
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 134 4>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clock-names = "ref", "bus_early", "suspend";
......@@ -480,7 +486,7 @@ usb0: usb@65a00000 {
dr_mode = "host";
};
usb-glue@65b00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -534,7 +540,7 @@ usb1: usb@65c00000 {
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 137 4>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
......@@ -544,7 +550,7 @@ usb1: usb@65c00000 {
dr_mode = "host";
};
usb-glue@65d00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pro5-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -614,8 +620,7 @@ usb1_ssphy0: ss-phy@380 {
};
pcie_ep: pcie-ep@66000000 {
compatible = "socionext,uniphier-pro5-pcie-ep",
"snps,dw-pcie-ep";
compatible = "socionext,uniphier-pro5-pcie-ep";
status = "disabled";
reg-names = "dbi", "dbi2", "link", "addr_space";
reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
......@@ -650,7 +655,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......@@ -663,7 +668,7 @@ emmc: mmc@68400000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68400000 0x800>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
......@@ -679,7 +684,7 @@ sd: mmc@68800000 {
compatible = "socionext,uniphier-sd-v3.1";
status = "disabled";
reg = <0x68800000 0x800>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......
arch/arm/boot/dts/uniphier-pxs2-gentil.dts
View file @ 302c9454
......@@ -99,3 +99,7 @@ &usb0 {
&usb1 {
status = "okay";
};
&ahci {
status = "okay";
};
arch/arm/boot/dts/uniphier-pxs2.dtsi
View file @ 302c9454
......@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
......@@ -161,7 +162,10 @@ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(1280 * 1024)>;
cache-sets = <512>;
......@@ -175,7 +179,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -188,7 +192,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 216 4>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
......@@ -199,7 +203,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -210,7 +214,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -221,7 +225,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -232,7 +236,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -259,7 +263,7 @@ gpio: gpio@55000000 {
audio@56000000 {
compatible = "socionext,uniphier-pxs2-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ain1>,
<&pinctrl_ain2>,
......@@ -317,7 +321,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -331,7 +335,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -345,7 +349,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -359,7 +363,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -373,7 +377,7 @@ i2c4: i2c@58784000 {
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 8>;
resets = <&peri_rst 8>;
clock-frequency = <400000>;
......@@ -385,7 +389,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
......@@ -397,7 +401,7 @@ i2c6: i2c@58786000 {
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
......@@ -454,7 +458,7 @@ emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a000000 0x800>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sd_clk 1>;
......@@ -470,7 +474,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......@@ -515,7 +519,7 @@ efuse@200 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -530,14 +534,16 @@ aidet: interrupt-controller@5fc20000 {
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0xf04>;
interrupts = <GIC_PPI 11
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0xf04>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
......@@ -564,9 +570,9 @@ sys_rst: reset {
#reset-cells = <1>;
};
pvtctl: pvtctl {
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs2-thermal";
interrupts = <0 3 4>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f86 0x6844>;
};
......@@ -576,7 +582,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-pxs2-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
......@@ -593,12 +599,52 @@ mdio: mdio {
};
};
ahci: sata@65600000 {
compatible = "socionext,uniphier-pxs2-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65600000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 28>;
resets = <&sys_rst 28>, <&ahci_rst 0>;
ports-implemented = <1>;
phys = <&ahci_phy>;
};
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs2-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs2-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link";
resets = <&sys_rst 28>;
#reset-cells = <1>;
};
ahci_phy: sata-phy@10 {
compatible = "socionext,uniphier-pxs2-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "dwc_usb3";
interrupts = <0 134 4>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
......@@ -609,7 +655,7 @@ usb0: usb@65a00000 {
dr_mode = "host";
};
usb-glue@65b00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -694,7 +740,7 @@ usb1: usb@65c00000 {
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "dwc_usb3";
interrupts = <0 137 4>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
......@@ -704,7 +750,7 @@ usb1: usb@65c00000 {
dr_mode = "host";
};
usb-glue@65d00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs2-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -780,7 +826,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm/boot/dts/uniphier-sld8-ref.dts
View file @ 302c9454
......@@ -36,11 +36,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -56,7 +56,7 @@ &serial3 {
};
&gpio {
xirq0 {
xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
......
arch/arm/boot/dts/uniphier-sld8.dtsi
View file @ 302c9454
......@@ -6,6 +6,7 @@
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-sld8";
......@@ -55,7 +56,8 @@ l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-size = <(256 * 1024)>;
cache-sets = <256>;
......@@ -69,7 +71,7 @@ spi: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -80,7 +82,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -91,7 +93,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -102,7 +104,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -113,7 +115,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 29 4>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -144,7 +146,7 @@ i2c0: i2c@58400000 {
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -158,7 +160,7 @@ i2c1: i2c@58480000 {
reg = <0x58480000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 1>;
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -172,7 +174,7 @@ i2c2: i2c@58500000 {
reg = <0x58500000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 1>;
interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -186,7 +188,7 @@ i2c3: i2c@58580000 {
reg = <0x58580000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -244,8 +246,13 @@ peri_rst: reset {
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
......@@ -255,7 +262,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a400000 0x200>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......@@ -275,7 +282,7 @@ emmc: mmc@5a500000 {
compatible = "socionext,uniphier-sd-v2.91";
status = "disabled";
reg = <0x5a500000 0x200>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&mio_clk 1>;
......@@ -293,7 +300,7 @@ usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 80 4>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
......@@ -307,7 +314,7 @@ usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 81 4>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
......@@ -321,7 +328,7 @@ usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 82 4>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
......@@ -362,14 +369,16 @@ efuse@200 {
timer@60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
interrupts = <1 11 0x104>;
interrupts = <GIC_PPI 11
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
timer@60000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
interrupts = <1 13 0x104>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&arm_timer_clk>;
};
......@@ -411,7 +420,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm/boot/dts/uniphier-support-card.dtsi
View file @ 302c9454
......@@ -8,13 +8,13 @@
&system_bus {
status = "okay";
ranges = <1 0x00000000 0x42000000 0x02000000>;
interrupt-parent = <&gpio>;
ethsc: ethernet@1,1f00000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <1 0x01f00000 0x1000>;
phy-mode = "mii";
reg-io-width = <4>;
interrupt-parent = <&gpio>;
};
serialsc: serial@1,1fb0000 {
......@@ -22,5 +22,6 @@ serialsc: serial@1,1fb0000 {
reg = <1 0x01fb0000 0x20>;
clock-frequency = <12288000>;
reg-shift = <1>;
interrupt-parent = <&gpio>;
};
};
arch/arm64/boot/dts/socionext/Makefile
View file @ 302c9454
......@@ -5,4 +5,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld20-akebi96.dtb \
uniphier-ld20-global.dtb \
uniphier-ld20-ref.dtb \
uniphier-pxs3-ref.dtb
uniphier-pxs3-ref.dtb \
uniphier-pxs3-ref-gadget0.dtb \
uniphier-pxs3-ref-gadget1.dtb
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
View file @ 302c9454
......@@ -39,11 +39,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -51,7 +51,7 @@ &serial0 {
};
&gpio {
xirq0 {
xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
......
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View file @ 302c9454
......@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld11";
......@@ -35,6 +36,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
......@@ -44,8 +46,13 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
l2: l2-cache {
compatible = "cache";
};
};
cluster0_opp: opp-table {
......@@ -102,10 +109,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
......@@ -131,7 +138,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -144,7 +151,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 216 4>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
......@@ -155,7 +162,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -166,7 +173,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -177,7 +184,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -188,7 +195,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -223,7 +230,7 @@ gpio: gpio@55000000 {
audio@56000000 {
compatible = "socionext,uniphier-ld11-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
......@@ -323,7 +330,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -337,7 +344,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -350,7 +357,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
......@@ -362,7 +369,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -376,7 +383,7 @@ i2c4: i2c@58784000 {
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
......@@ -389,7 +396,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
......@@ -440,7 +447,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
......@@ -460,7 +467,7 @@ usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 243 4>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
......@@ -476,7 +483,7 @@ usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 244 4>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
......@@ -492,7 +499,7 @@ usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 245 4>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
......@@ -530,7 +537,7 @@ pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
usb-phy {
usb-controller {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
......@@ -573,7 +580,7 @@ efuse@200 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -591,7 +598,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe40000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
......@@ -618,7 +625,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld11-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ether";
clocks = <&sys_clk 6>;
reset-names = "ether";
......@@ -640,7 +647,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
View file @ 302c9454
......@@ -110,7 +110,7 @@ usb-over-spi@0 {
spi-max-frequency = <12500000>;
interrupt-parent = <&gpio>;
interrupt-names = "udc";
interrupts = <0 2>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
};
......@@ -168,12 +168,12 @@ &pcie {
&gpio {
/* IRQs for Max3421 */
xirq0 {
xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 1>;
input;
};
xirq10 {
xirq10-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(10) 1>;
input;
......
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
View file @ 302c9454
......@@ -39,11 +39,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <0 8>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
......@@ -51,7 +51,7 @@ &serial0 {
};
&gpio {
xirq0 {
xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
......
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View file @ 302c9454
......@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
......@@ -45,6 +46,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
......@@ -55,6 +57,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
......@@ -65,6 +68,7 @@ cpu2: cpu@100 {
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
......@@ -75,12 +79,21 @@ cpu3: cpu@101 {
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
a72_l2: l2-cache0 {
compatible = "cache";
};
a53_l2: l2-cache1 {
compatible = "cache";
};
};
cluster0_opp: opp-table0 {
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
......@@ -118,7 +131,7 @@ opp-1100000000 {
};
};
cluster1_opp: opp-table1 {
cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
......@@ -176,10 +189,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
......@@ -236,7 +249,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -249,7 +262,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 216 4>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
......@@ -262,7 +275,7 @@ spi2: spi@54006200 {
reg = <0x54006200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 229 4>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
clocks = <&peri_clk 13>;
......@@ -275,7 +288,7 @@ spi3: spi@54006300 {
reg = <0x54006300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 230 4>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3>;
clocks = <&peri_clk 14>;
......@@ -286,7 +299,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -297,7 +310,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -308,7 +321,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -319,7 +332,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -348,7 +361,7 @@ gpio: gpio@55000000 {
audio@56000000 {
compatible = "socionext,uniphier-ld20-aio";
reg = <0x56000000 0x80000>;
interrupts = <0 144 4>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
......@@ -448,7 +461,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -462,7 +475,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -475,7 +488,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
......@@ -487,7 +500,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -501,7 +514,7 @@ i2c4: i2c@58784000 {
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
......@@ -514,7 +527,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
......@@ -570,7 +583,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
......@@ -590,7 +603,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&sd_clk 0>;
......@@ -675,7 +688,7 @@ usb_hs_i2: trim@5a,0 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -693,7 +706,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
......@@ -715,9 +728,9 @@ watchdog {
compatible = "socionext,uniphier-wdt";
};
pvtctl: pvtctl {
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
interrupts = <0 3 4>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
......@@ -727,7 +740,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld20-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
......@@ -749,7 +762,7 @@ usb: usb@65a00000 {
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
interrupts = <0 134 4>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
......@@ -762,7 +775,7 @@ usb: usb@65a00000 {
dr_mode = "host";
};
usb-glue@65b00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -895,7 +908,7 @@ usb_ssphy1: ss-phy@310 {
};
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
......@@ -915,7 +928,8 @@ pcie: pcie@66000000 {
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
......@@ -928,7 +942,7 @@ pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
......@@ -950,7 +964,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts 0 → 100644
View file @ 302c9454
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
//
// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #0)
//
// Copyright (C) 2021 Socionext Inc.
// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
#include "uniphier-pxs3-ref.dts"
/ {
model = "UniPhier PXs3 Reference Board (USB-Device #0)";
};
/* I2C3 pinctrl is shared with USB*VBUSIN */
&i2c3 {
status = "disabled";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
pinctrl-0 = <&pinctrl_usb0_device>;
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,usb2_gadget_lpm_disable;
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
};
&usb0_hsphy0 {
/delete-property/ vbus-supply;
};
&usb0_ssphy0 {
/delete-property/ vbus-supply;
};
/delete-node/ &usb0_hsphy1;
/delete-node/ &usb0_ssphy1;
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts 0 → 100644
View file @ 302c9454
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
//
// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #1)
//
// Copyright (C) 2021 Socionext Inc.
// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
/dts-v1/;
#include "uniphier-pxs3-ref.dts"
/ {
model = "UniPhier PXs3 Reference Board (USB-Device #1)";
};
/* I2C3 pinctrl is shared with USB*VBUSIN */
&i2c3 {
status = "disabled";
};
&usb1 {
status = "okay";
dr_mode = "peripheral";
pinctrl-0 = <&pinctrl_usb1_device>;
snps,dis_enblslpm_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,usb2_gadget_lpm_disable;
phy-names = "usb2-phy", "usb3-phy";
phys = <&usb1_hsphy0>, <&usb1_ssphy0>;
};
&usb1_hsphy0 {
/delete-property/ vbus-supply;
};
&usb1_ssphy0 {
/delete-property/ vbus-supply;
};
/delete-node/ &usb1_hsphy1;
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
View file @ 302c9454
......@@ -40,11 +40,11 @@ memory@80000000 {
};
&ethsc {
interrupts = <4 8>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
interrupts = <4 8>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&spi0 {
......@@ -68,7 +68,7 @@ &serial3 {
};
&gpio {
xirq4 {
xirq4-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
input;
......@@ -137,6 +137,14 @@ nand@0 {
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
&pinctrl_ether_rgmii {
tx {
pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
......
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View file @ 302c9454
......@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
......@@ -42,6 +43,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
......@@ -52,6 +54,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
......@@ -62,6 +65,7 @@ cpu2: cpu@2 {
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
......@@ -72,9 +76,14 @@ cpu3: cpu@3 {
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
l2: l2-cache {
compatible = "cache";
};
};
cluster0_opp: opp-table {
......@@ -135,10 +144,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
......@@ -195,7 +204,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 39 4>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
......@@ -208,7 +217,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 216 4>;
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
......@@ -219,7 +228,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
......@@ -230,7 +239,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
......@@ -241,7 +250,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
......@@ -252,7 +261,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
......@@ -284,7 +293,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
......@@ -298,7 +307,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
......@@ -312,7 +321,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
......@@ -326,7 +335,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
......@@ -340,7 +349,7 @@ i2c6: i2c@58786000 {
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 26 4>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
......@@ -396,7 +405,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
interrupts = <0 78 4>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
......@@ -416,7 +425,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
interrupts = <0 76 4>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
......@@ -505,7 +514,7 @@ usb_hs_i2: trim@5a,0 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
interrupts = <0 188 4>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
......@@ -523,7 +532,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
......@@ -545,9 +554,9 @@ watchdog {
compatible = "socionext,uniphier-wdt";
};
pvtctl: pvtctl {
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs3-thermal";
interrupts = <0 3 4>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
......@@ -557,7 +566,7 @@ eth0: ethernet@65000000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
interrupts = <0 66 4>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
......@@ -578,7 +587,7 @@ eth1: ethernet@65200000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65200000 0x8500>;
interrupts = <0 67 4>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether1_rgmii>;
clock-names = "ether";
......@@ -595,12 +604,92 @@ mdio1: mdio {
};
};
ahci0: sata@65600000 {
compatible = "socionext,uniphier-pxs3-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65600000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 28>;
resets = <&sys_rst 28>, <&ahci0_rst 0>;
ports-implemented = <1>;
phys = <&ahci0_phy>;
};
sata-controller@65700000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65700000 0x100>;
ahci0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 28>;
reset-names = "link";
resets = <&sys_rst 28>;
#reset-cells = <1>;
};
ahci0_phy: sata-phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link", "phy";
clocks = <&sys_clk 28>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 28>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
ahci1: sata@65800000 {
compatible = "socionext,uniphier-pxs3-ahci",
"generic-ahci";
status = "disabled";
reg = <0x65800000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clk 29>;
resets = <&sys_rst 29>, <&ahci1_rst 0>;
ports-implemented = <1>;
phys = <&ahci1_phy>;
};
sata-controller@65900000 {
compatible = "socionext,uniphier-pxs3-ahci-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65900000 0x100>;
ahci1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pxs3-ahci-reset";
reg = <0x0 0x4>;
clock-names = "link";
clocks = <&sys_clk 29>;
reset-names = "link";
resets = <&sys_rst 29>;
#reset-cells = <1>;
};
ahci1_phy: sata-phy@10 {
compatible = "socionext,uniphier-pxs3-ahci-phy";
reg = <0x10 0x10>;
clock-names = "link", "phy";
clocks = <&sys_clk 29>, <&sys_clk 30>;
reset-names = "link", "phy";
resets = <&sys_rst 29>, <&sys_rst 30>;
#phy-cells = <0>;
};
};
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "dwc_usb3";
interrupts = <0 134 4>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
......@@ -611,7 +700,7 @@ usb0: usb@65a00000 {
dr_mode = "host";
};
usb-glue@65b00000 {
usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -702,7 +791,7 @@ usb1: usb@65c00000 {
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "dwc_usb3";
interrupts = <0 137 4>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
......@@ -713,7 +802,7 @@ usb1: usb@65c00000 {
dr_mode = "host";
};
usb-glue@65d00000 {
usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
......@@ -792,7 +881,7 @@ usb1_ssphy0: ss-phy@300 {
};
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
......@@ -812,7 +901,8 @@ pcie: pcie@66000000 {
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
......@@ -825,7 +915,7 @@ pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
......@@ -847,7 +937,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 65 4>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
......
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