Commit 30d8dffa authored by Victor Lu's avatar Victor Lu Committed by Alex Deucher

drm/amdgpu: Do not program VM_L2_CNTL under SRIOV

VM_L2_CNTL* should not be programmed on driver unload under SRIOV.
These regs are skipped during SRIOV driver init.
Signed-off-by: default avatarVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: default avatarVignesh Chander <Vignesh.Chander@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6616b5e1
...@@ -456,11 +456,13 @@ static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev, ...@@ -456,11 +456,13 @@ static void gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev,
WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp); WREG32_SOC15_RLC(GC, GET_INST(GC, j), regMC_VM_MX_L1_TLB_CNTL, tmp);
/* Setup L2 cache */ /* Setup L2 cache */
if (!amdgpu_sriov_vf(adev)) {
tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL); tmp = RREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp); WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL, tmp);
WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0); WREG32_SOC15(GC, GET_INST(GC, j), regVM_L2_CNTL3, 0);
} }
}
} }
static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev)
......
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