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Commit 311b79bb authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v3.12/cleanup-unused-defines' of... 

Merge tag 'omap-for-v3.12/cleanup-unused-defines' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

From Tony Lindgren:
Removal of unused omap defines via Paul Walmsley <paul@pwsan.com>:

This series removes the currently-unused PRCM macros from
arch/arm/mach-omap2.

Basic test logs are available at:

http://www.pwsan.com/omap/testlogs/drop_unused_prcm_macros_v3.11-rc/20130721211401/

Once, years ago, we thought that it would be good to document the PRCM
register bits in the Linux codebase.  Most folks in the broader
community did not have access to the same documentation, so we thought
that they might be able to use these bits to fix bugs and improve the
code.

We were also able to autogenerate most of these macros, so it was
thought that defining them in advance would reduce the risk of error,
inconsistencies, and merge conflicts caused when patch sets
incrementally defined them by hand.

Well, nice thoughts.  But the first rationale was rendered partially
obsolete when TI started to release public TRM documentation PDFs at
some point in the OMAP3 timeframe.  (Despite their weaknesses, TI's
public OMAP TRMs remain the most useful public documentation available
for any ARM Linux SoC -- at least to the extent of my knowledge.)  And
then the current Linux development tropism towards
development-by-negative-diffstat obliterated the remainder of the
above two philosophies.

So, for the few, the masochistic, out there who wish to continue
developing TI PRCM code, I would ask that you resurrect any
additionally-needed macros from these commits, rather than writing
them manually.  Purely for the sake of a pleasant atavism, perhaps; the
way one appreciates a used bookstore, or a video rental store...

And thanks to the upstream maintainers for being patient while we
adjust.

* tag 'omap-for-v3.12/cleanup-unused-defines' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP5: PRM/CM: Cleanup unused header
  ARM: OMAP4: PRM/CM: Cleanup unused header
  ARM: OMAP3: PRM/CM: Cleanup unused header
  ARM: OMAP2: PRM/CM: Cleanup unused header
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 1cb3fd09 dc46c790
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arch/arm/mach-omap2/cm-regbits-24xx.h
View file @ 311b79bb
......@@ -14,439 +14,121 @@
* published by the Free Software Foundation.
*/
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP24XX_EN_CAM_SHIFT 31
#define OMAP24XX_EN_CAM_MASK (1 << 31)
#define OMAP24XX_EN_WDT4_SHIFT 29
#define OMAP24XX_EN_WDT4_MASK (1 << 29)
#define OMAP2420_EN_WDT3_SHIFT 28
#define OMAP2420_EN_WDT3_MASK (1 << 28)
#define OMAP24XX_EN_MSPRO_SHIFT 27
#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
#define OMAP24XX_EN_FAC_SHIFT 25
#define OMAP24XX_EN_FAC_MASK (1 << 25)
#define OMAP2420_EN_EAC_SHIFT 24
#define OMAP2420_EN_EAC_MASK (1 << 24)
#define OMAP24XX_EN_HDQ_SHIFT 23
#define OMAP24XX_EN_HDQ_MASK (1 << 23)
#define OMAP2420_EN_I2C2_SHIFT 20
#define OMAP2420_EN_I2C2_MASK (1 << 20)
#define OMAP2420_EN_I2C1_SHIFT 19
#define OMAP2420_EN_I2C1_MASK (1 << 19)
/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
#define OMAP2430_EN_MCBSP5_SHIFT 5
#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
#define OMAP2430_EN_MCBSP4_SHIFT 4
#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
#define OMAP2430_EN_MCBSP3_SHIFT 3
#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
#define OMAP24XX_EN_SSI_SHIFT 1
#define OMAP24XX_EN_SSI_MASK (1 << 1)
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP24XX_EN_MPU_WDT_SHIFT 3
#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
/* Bits specific to each register */
/* CM_IDLEST_MPU */
/* 2430 only */
#define OMAP2430_ST_MPU_MASK (1 << 0)
/* CM_CLKSEL_MPU */
#define OMAP24XX_CLKSEL_MPU_SHIFT 0
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_MPU_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits*/
#define OMAP24XX_EN_TV_SHIFT 2
#define OMAP24XX_EN_TV_MASK (1 << 2)
#define OMAP24XX_EN_DSS2_SHIFT 1
#define OMAP24XX_EN_DSS2_MASK (1 << 1)
#define OMAP24XX_EN_DSS1_SHIFT 0
#define OMAP24XX_EN_DSS1_MASK (1 << 0)
/* CM_FCLKEN2_CORE specific bits */
#define OMAP2430_EN_I2CHS2_SHIFT 20
#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
#define OMAP2430_EN_I2CHS1_SHIFT 19
#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
#define OMAP2430_EN_MMCHSDB2_SHIFT 17
#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
#define OMAP2430_EN_MMCHSDB1_SHIFT 16
#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
/* CM_ICLKEN1_CORE specific bits */
#define OMAP24XX_EN_MAILBOXES_SHIFT 30
#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_EN_DSS_SHIFT 0
#define OMAP24XX_EN_DSS_MASK (1 << 0)
/* CM_ICLKEN2_CORE specific bits */
/* CM_ICLKEN3_CORE */
/* 2430 only */
#define OMAP2430_EN_SDRC_SHIFT 2
#define OMAP2430_EN_SDRC_MASK (1 << 2)
/* CM_ICLKEN4_CORE */
#define OMAP24XX_EN_PKA_SHIFT 4
#define OMAP24XX_EN_PKA_MASK (1 << 4)
#define OMAP24XX_EN_AES_SHIFT 3
#define OMAP24XX_EN_AES_MASK (1 << 3)
#define OMAP24XX_EN_RNG_SHIFT 2
#define OMAP24XX_EN_RNG_MASK (1 << 2)
#define OMAP24XX_EN_SHA_SHIFT 1
#define OMAP24XX_EN_SHA_MASK (1 << 1)
#define OMAP24XX_EN_DES_SHIFT 0
#define OMAP24XX_EN_DES_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
#define OMAP24XX_ST_MAILBOXES_SHIFT 30
#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_ST_WDT4_SHIFT 29
#define OMAP24XX_ST_WDT4_MASK (1 << 29)
#define OMAP2420_ST_WDT3_SHIFT 28
#define OMAP2420_ST_WDT3_MASK (1 << 28)
#define OMAP24XX_ST_MSPRO_SHIFT 27
#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
#define OMAP24XX_ST_FAC_SHIFT 25
#define OMAP24XX_ST_FAC_MASK (1 << 25)
#define OMAP2420_ST_EAC_SHIFT 24
#define OMAP2420_ST_EAC_MASK (1 << 24)
#define OMAP24XX_ST_HDQ_SHIFT 23
#define OMAP24XX_ST_HDQ_MASK (1 << 23)
#define OMAP2420_ST_I2C2_SHIFT 20
#define OMAP2420_ST_I2C2_MASK (1 << 20)
#define OMAP2430_ST_I2CHS1_SHIFT 19
#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
#define OMAP2420_ST_I2C1_SHIFT 19
#define OMAP2420_ST_I2C1_MASK (1 << 19)
#define OMAP2430_ST_I2CHS2_SHIFT 20
#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
#define OMAP24XX_ST_MCBSP2_SHIFT 16
#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT 15
#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
#define OMAP24XX_ST_DSS_SHIFT 0
#define OMAP24XX_ST_DSS_MASK (1 << 0)
/* CM_IDLEST2_CORE */
#define OMAP2430_ST_MCBSP5_SHIFT 5
#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
#define OMAP2430_ST_MCBSP4_SHIFT 4
#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
#define OMAP2430_ST_MCBSP3_SHIFT 3
#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
#define OMAP24XX_ST_SSI_SHIFT 1
#define OMAP24XX_ST_SSI_MASK (1 << 1)
/* CM_IDLEST3_CORE */
/* 2430 only */
#define OMAP2430_ST_SDRC_MASK (1 << 2)
/* CM_IDLEST4_CORE */
#define OMAP24XX_ST_PKA_SHIFT 4
#define OMAP24XX_ST_PKA_MASK (1 << 4)
#define OMAP24XX_ST_AES_SHIFT 3
#define OMAP24XX_ST_AES_MASK (1 << 3)
#define OMAP24XX_ST_RNG_SHIFT 2
#define OMAP24XX_ST_RNG_MASK (1 << 2)
#define OMAP24XX_ST_SHA_SHIFT 1
#define OMAP24XX_ST_SHA_MASK (1 << 1)
#define OMAP24XX_ST_DES_SHIFT 0
#define OMAP24XX_ST_DES_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
#define OMAP2420_AUTO_MMC_MASK (1 << 26)
#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
#define OMAP2420_AUTO_EAC_MASK (1 << 24)
#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
/* CM_AUTOIDLE2_CORE */
#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
#define OMAP24XX_AUTO_USB_MASK (1 << 0)
/* CM_AUTOIDLE3_CORE */
#define OMAP24XX_AUTO_SDRC_SHIFT 2
#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
#define OMAP24XX_AUTO_GPMC_SHIFT 1
#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
#define OMAP24XX_AUTO_SDMA_SHIFT 0
#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
/* CM_AUTOIDLE4_CORE */
#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
#define OMAP24XX_AUTO_AES_MASK (1 << 3)
#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
#define OMAP24XX_AUTO_DES_MASK (1 << 0)
/* CM_CLKSEL1_CORE */
#define OMAP24XX_CLKSEL_USB_SHIFT 25
#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
#define OMAP24XX_CLKSEL_SSI_SHIFT 20
#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
#define OMAP24XX_CLKSEL_L4_SHIFT 5
#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
#define OMAP24XX_CLKSEL_L4_WIDTH 2
#define OMAP24XX_CLKSEL_L3_SHIFT 0
#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_L3_WIDTH 5
/* CM_CLKSEL2_CORE */
#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
/* CM_CLKSTCTRL_CORE */
#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */
#define OMAP24XX_EN_3D_SHIFT 2
#define OMAP24XX_EN_3D_MASK (1 << 2)
#define OMAP24XX_EN_2D_SHIFT 1
#define OMAP24XX_EN_2D_MASK (1 << 1)
/* CM_ICLKEN_GFX specific bits */
/* CM_IDLEST_GFX specific bits */
/* CM_CLKSEL_GFX specific bits */
/* CM_CLKSTCTRL_GFX */
#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */
/* CM_ICLKEN_WKUP specific bits */
#define OMAP2430_EN_ICR_SHIFT 6
#define OMAP2430_EN_ICR_MASK (1 << 6)
#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_EN_WDT1_SHIFT 4
#define OMAP24XX_EN_WDT1_MASK (1 << 4)
#define OMAP24XX_EN_32KSYNC_SHIFT 1
#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
/* CM_IDLEST_WKUP specific bits */
#define OMAP2430_ST_ICR_SHIFT 6
#define OMAP2430_ST_ICR_MASK (1 << 6)
#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_ST_WDT1_SHIFT 4
#define OMAP24XX_ST_WDT1_MASK (1 << 4)
#define OMAP24XX_ST_MPU_WDT_SHIFT 3
#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
#define OMAP24XX_ST_32KSYNC_SHIFT 1
#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
/* CM_AUTOIDLE_WKUP */
#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
/* CM_CLKSEL_WKUP */
#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
/* CM_CLKEN_PLL */
#define OMAP24XX_EN_54M_PLL_SHIFT 6
#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
#define OMAP24XX_EN_96M_PLL_SHIFT 2
#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
#define OMAP24XX_EN_DPLL_SHIFT 0
#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
/* CM_IDLEST_CKGEN */
#define OMAP24XX_ST_54M_APLL_SHIFT 9
#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
#define OMAP24XX_ST_96M_APLL_SHIFT 8
#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
#define OMAP24XX_ST_CORE_CLK_SHIFT 0
#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
/* CM_AUTOIDLE_PLL */
#define OMAP24XX_AUTO_54M_SHIFT 6
#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
#define OMAP24XX_AUTO_96M_SHIFT 2
#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
/* CM_CLKSEL1_PLL */
#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
#define OMAP24XX_APLLS_CLKIN_SHIFT 23
#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
#define OMAP24XX_DPLL_MULT_SHIFT 12
#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
#define OMAP24XX_DPLL_DIV_SHIFT 8
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
#define OMAP24XX_54M_SOURCE_SHIFT 5
#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
#define OMAP24XX_54M_SOURCE_WIDTH 1
#define OMAP2430_96M_SOURCE_SHIFT 4
#define OMAP2430_96M_SOURCE_MASK (1 << 4)
#define OMAP2430_96M_SOURCE_WIDTH 1
#define OMAP24XX_48M_SOURCE_SHIFT 3
#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
/* CM_CLKSEL2_PLL */
#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
/* CM_FCLKEN_DSP */
#define OMAP2420_EN_IVA_COP_SHIFT 10
#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
#define OMAP2420_EN_IVA_MPU_SHIFT 8
#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
/* CM_ICLKEN_DSP */
#define OMAP2420_EN_DSP_IPI_SHIFT 1
#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
/* CM_IDLEST_DSP */
#define OMAP2420_ST_IVA_MASK (1 << 8)
#define OMAP2420_ST_IPI_MASK (1 << 1)
#define OMAP24XX_ST_DSP_MASK (1 << 0)
/* CM_AUTOIDLE_DSP */
#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
/* CM_CLKSEL_DSP */
#define OMAP2420_SYNC_IVA_MASK (1 << 13)
#define OMAP2420_CLKSEL_IVA_SHIFT 8
#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
#define OMAP24XX_CLKSEL_DSP_SHIFT 0
#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
/* CM_CLKSTCTRL_DSP */
#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
/* CM_FCLKEN_MDM */
/* 2430 only */
#define OMAP2430_EN_OSC_SHIFT 1
#define OMAP2430_EN_OSC_MASK (1 << 1)
/* CM_ICLKEN_MDM */
/* 2430 only */
#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
/* CM_IDLEST_MDM specific bits */
/* 2430 only */
/* CM_AUTOIDLE_MDM */
/* 2430 only */
#define OMAP2430_AUTO_OSC_MASK (1 << 1)
#define OMAP2430_AUTO_MDM_MASK (1 << 0)
/* CM_CLKSEL_MDM */
/* 2430 only */
#define OMAP2430_SYNC_MDM_MASK (1 << 4)
#define OMAP2430_CLKSEL_MDM_SHIFT 0
#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
/* CM_CLKSTCTRL_MDM */
/* 2430 only */
#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
#endif
arch/arm/mach-omap2/cm-regbits-33xx.h
View file @ 311b79bb
......@@ -20,798 +20,49 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
/*
* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
*/
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_CPSW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3S_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4FW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
/* Used by CM_MPU_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2DIV_SHIFT 3
#define AM33XX_CLKOUT2DIV_WIDTH 3
#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2EN_SHIFT 7
#define AM33XX_CLKOUT2EN_WIDTH 1
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
/*
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
* CLKSEL_TIMER7_CLK
*/
#define AM33XX_CLKSEL_SHIFT 0
#define AM33XX_CLKSEL_WIDTH 1
#define AM33XX_CLKSEL_MASK (0x01 << 0)
/*
* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
* CM_CPTS_RFT_CLKSEL
*/
#define AM33XX_CLKSEL_0_0_SHIFT 0
#define AM33XX_CLKSEL_0_0_WIDTH 1
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
#define AM33XX_CLKSEL_0_1_SHIFT 0
#define AM33XX_CLKSEL_0_1_WIDTH 2
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
#define AM33XX_CLKSEL_0_2_SHIFT 0
#define AM33XX_CLKSEL_0_2_WIDTH 3
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
/*
* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
*/
#define AM33XX_CLKTRCTRL_SHIFT 0
#define AM33XX_CLKTRCTRL_WIDTH 2
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define AM33XX_DELTAMSTEP_SHIFT 0
#define AM33XX_DELTAMSTEP_WIDTH 20
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_DIV_SHIFT 0
#define AM33XX_DPLL_DIV_WIDTH 7
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_EN_SHIFT 0
#define AM33XX_DPLL_EN_WIDTH 3
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_MULT_SHIFT 8
#define AM33XX_DPLL_MULT_WIDTH 11
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_SD_DIV_SHIFT 24
#define AM33XX_DPLL_SD_DIV_WIDTH 8
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_EN_SHIFT 12
#define AM33XX_DPLL_SSC_EN_WIDTH 1
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_IDLEST_SHIFT 16
#define AM33XX_IDLEST_WIDTH 2
#define AM33XX_IDLEST_MASK (0x3 << 16)
/* Used by CM_MAC_CLKSEL */
#define AM33XX_MII_CLK_SEL_SHIFT 2
#define AM33XX_MII_CLK_SEL_WIDTH 1
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
* CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_MODULEMODE_SHIFT 0
#define AM33XX_MODULEMODE_WIDTH 2
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
/* Used by CM_WKUP_GPIO0_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO1_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO2_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO3_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO4_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO5_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO6_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
*/
#define AM33XX_STBYST_SHIFT 18
#define AM33XX_STBYST_WIDTH 1
#define AM33XX_STBYST_MASK (1 << 18)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLK_SHIFT 0
#define AM33XX_ST_DPLL_CLK_WIDTH 1
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_MN_BYPASS_SHIFT 8
#define AM33XX_ST_MN_BYPASS_WIDTH 1
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
/* Used by CONTROL_SEC_CLK_CTRL */
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
#endif
arch/arm/mach-omap2/cm-regbits-34xx.h
View file @ 311b79bb
......@@ -14,833 +14,201 @@
* published by the Free Software Foundation.
*/
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
#define OMAP3430ES2_EN_MMC3_SHIFT 30
#define OMAP3430_EN_MSPRO_MASK (1 << 23)
#define OMAP3430_EN_MSPRO_SHIFT 23
#define OMAP3430_EN_HDQ_MASK (1 << 22)
#define OMAP3430_EN_HDQ_SHIFT 22
#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
#define OMAP3430ES1_EN_D2D_SHIFT 3
#define OMAP3430_EN_SSI_MASK (1 << 0)
#define OMAP3430_EN_SSI_SHIFT 0
/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
#define OMAP3430ES2_EN_USBTLL_SHIFT 2
#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP3430_EN_WDT2_MASK (1 << 5)
#define OMAP3430_EN_WDT2_SHIFT 5
/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
#define OMAP3430_EN_CAM_MASK (1 << 0)
#define OMAP3430_EN_CAM_SHIFT 0
/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
#define OMAP3430_EN_WDT3_MASK (1 << 12)
#define OMAP3430_EN_WDT3_SHIFT 12
/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
/* Bits specific to each register */
/* CM_FCLKEN_IVA2 */
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
/* CM_CLKEN_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_IVA2 */
#define OMAP3430_ST_IVA2_SHIFT 0
#define OMAP3430_ST_IVA2_MASK (1 << 0)
/* CM_IDLEST_PLL_IVA2 */
#define OMAP3430_ST_IVA2_CLK_SHIFT 0
#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL_IVA2 */
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_IVA2 */
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
/* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
/* CM_REVISION specific bits */
/* CM_SYSCONFIG specific bits */
/* CM_CLKEN_PLL_MPU */
#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_MPU_DPLL_SHIFT 0
#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_MPU */
#define OMAP3430_ST_MPU_MASK (1 << 0)
/* CM_IDLEST_PLL_MPU */
#define OMAP3430_ST_MPU_CLK_SHIFT 0
#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
#define OMAP3430_ST_MPU_CLK_WIDTH 1
/* CM_AUTOIDLE_PLL_MPU */
#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_MPU_CLK_SRC_WIDTH 3
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_MPU */
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
/* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits */
#define OMAP3430_EN_MODEM_MASK (1 << 31)
#define OMAP3430_EN_MODEM_SHIFT 31
/* CM_ICLKEN1_CORE specific bits */
#define OMAP3430_EN_ICR_MASK (1 << 29)
#define OMAP3430_EN_ICR_SHIFT 29
#define OMAP3430_EN_AES2_MASK (1 << 28)
#define OMAP3430_EN_AES2_SHIFT 28
#define OMAP3430_EN_SHA12_MASK (1 << 27)
#define OMAP3430_EN_SHA12_SHIFT 27
#define OMAP3430_EN_DES2_MASK (1 << 26)
#define OMAP3430_EN_DES2_SHIFT 26
#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
#define OMAP3430ES1_EN_FAC_SHIFT 8
#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
#define OMAP3430_EN_MAILBOXES_SHIFT 7
#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_EN_OMAPCTRL_SHIFT 6
#define OMAP3430_EN_SAD2D_MASK (1 << 3)
#define OMAP3430_EN_SAD2D_SHIFT 3
#define OMAP3430_EN_SDRC_MASK (1 << 1)
#define OMAP3430_EN_SDRC_SHIFT 1
/* AM35XX specific CM_ICLKEN1_CORE bits */
#define AM35XX_EN_IPSS_MASK (1 << 4)
#define AM35XX_EN_IPSS_SHIFT 4
/* CM_ICLKEN2_CORE */
#define OMAP3430_EN_PKA_MASK (1 << 4)
#define OMAP3430_EN_PKA_SHIFT 4
#define OMAP3430_EN_AES1_MASK (1 << 3)
#define OMAP3430_EN_AES1_SHIFT 3
#define OMAP3430_EN_RNG_MASK (1 << 2)
#define OMAP3430_EN_RNG_SHIFT 2
#define OMAP3430_EN_SHA11_MASK (1 << 1)
#define OMAP3430_EN_SHA11_SHIFT 1
#define OMAP3430_EN_DES1_MASK (1 << 0)
#define OMAP3430_EN_DES1_SHIFT 0
/* CM_ICLKEN3_CORE */
#define OMAP3430_EN_MAD2D_SHIFT 3
#define OMAP3430_EN_MAD2D_MASK (1 << 3)
/* CM_FCLKEN3_CORE specific bits */
#define OMAP3430ES2_EN_TS_SHIFT 1
#define OMAP3430ES2_EN_TS_MASK (1 << 1)
#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
#define OMAP3430ES2_ST_MMC3_SHIFT 30
#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
#define OMAP3430_ST_ICR_SHIFT 29
#define OMAP3430_ST_ICR_MASK (1 << 29)
#define OMAP3430_ST_AES2_SHIFT 28
#define OMAP3430_ST_AES2_MASK (1 << 28)
#define OMAP3430_ST_SHA12_SHIFT 27
#define OMAP3430_ST_SHA12_MASK (1 << 27)
#define OMAP3430_ST_DES2_SHIFT 26
#define OMAP3430_ST_DES2_MASK (1 << 26)
#define OMAP3430_ST_MSPRO_SHIFT 23
#define OMAP3430_ST_MSPRO_MASK (1 << 23)
#define AM35XX_ST_UART4_SHIFT 23
#define AM35XX_ST_UART4_MASK (1 << 23)
#define OMAP3430_ST_HDQ_SHIFT 22
#define OMAP3430_ST_HDQ_MASK (1 << 22)
#define OMAP3430ES1_ST_FAC_SHIFT 8
#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
#define OMAP3430_ST_MAILBOXES_SHIFT 7
#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
#define OMAP3430_ST_OMAPCTRL_SHIFT 6
#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_ST_SAD2D_SHIFT 3
#define OMAP3430_ST_SAD2D_MASK (1 << 3)
#define OMAP3430_ST_SDMA_SHIFT 2
#define OMAP3430_ST_SDMA_MASK (1 << 2)
#define OMAP3430_ST_SDRC_SHIFT 1
#define OMAP3430_ST_SDRC_MASK (1 << 1)
#define OMAP3430_ST_SSI_STDBY_SHIFT 0
#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
/* AM35xx specific CM_IDLEST1_CORE bits */
#define AM35XX_ST_IPSS_SHIFT 5
#define AM35XX_ST_IPSS_MASK (1 << 5)
/* CM_IDLEST2_CORE */
#define OMAP3430_ST_PKA_SHIFT 4
#define OMAP3430_ST_PKA_MASK (1 << 4)
#define OMAP3430_ST_AES1_SHIFT 3
#define OMAP3430_ST_AES1_MASK (1 << 3)
#define OMAP3430_ST_RNG_SHIFT 2
#define OMAP3430_ST_RNG_MASK (1 << 2)
#define OMAP3430_ST_SHA11_SHIFT 1
#define OMAP3430_ST_SHA11_MASK (1 << 1)
#define OMAP3430_ST_DES1_SHIFT 0
#define OMAP3430_ST_DES1_MASK (1 << 0)
/* CM_IDLEST3_CORE */
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
#define OMAP3430_AUTO_MODEM_SHIFT 31
#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
#define OMAP3430ES2_AUTO_ICR_SHIFT 29
#define OMAP3430_AUTO_AES2_MASK (1 << 28)
#define OMAP3430_AUTO_AES2_SHIFT 28
#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
#define OMAP3430_AUTO_SHA12_SHIFT 27
#define OMAP3430_AUTO_DES2_MASK (1 << 26)
#define OMAP3430_AUTO_DES2_SHIFT 26
#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
#define OMAP3430_AUTO_MMC2_SHIFT 25
#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
#define OMAP3430_AUTO_MMC1_SHIFT 24
#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
#define OMAP3430_AUTO_MSPRO_SHIFT 23
#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
#define OMAP3430_AUTO_HDQ_SHIFT 22
#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
#define OMAP3430_AUTO_MCSPI4_SHIFT 21
#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
#define OMAP3430_AUTO_MCSPI3_SHIFT 20
#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
#define OMAP3430_AUTO_MCSPI2_SHIFT 19
#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
#define OMAP3430_AUTO_MCSPI1_SHIFT 18
#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
#define OMAP3430_AUTO_I2C3_SHIFT 17
#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
#define OMAP3430_AUTO_I2C2_SHIFT 16
#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
#define OMAP3430_AUTO_I2C1_SHIFT 15
#define OMAP3430_AUTO_UART2_MASK (1 << 14)
#define OMAP3430_AUTO_UART2_SHIFT 14
#define OMAP3430_AUTO_UART1_MASK (1 << 13)
#define OMAP3430_AUTO_UART1_SHIFT 13
#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
#define OMAP3430_AUTO_GPT11_SHIFT 12
#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
#define OMAP3430_AUTO_GPT10_SHIFT 11
#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
#define OMAP3430_AUTO_MCBSP5_SHIFT 10
#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
#define OMAP3430_AUTO_MCBSP1_SHIFT 9
#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
#define OMAP3430ES1_AUTO_FAC_SHIFT 8
#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
#define OMAP3430ES1_AUTO_D2D_SHIFT 3
#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
#define OMAP3430_AUTO_SAD2D_SHIFT 3
#define OMAP3430_AUTO_SSI_MASK (1 << 0)
#define OMAP3430_AUTO_SSI_SHIFT 0
/* CM_AUTOIDLE2_CORE */
#define OMAP3430_AUTO_PKA_MASK (1 << 4)
#define OMAP3430_AUTO_PKA_SHIFT 4
#define OMAP3430_AUTO_AES1_MASK (1 << 3)
#define OMAP3430_AUTO_AES1_SHIFT 3
#define OMAP3430_AUTO_RNG_MASK (1 << 2)
#define OMAP3430_AUTO_RNG_SHIFT 2
#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
#define OMAP3430_AUTO_SHA11_SHIFT 1
#define OMAP3430_AUTO_DES1_MASK (1 << 0)
#define OMAP3430_AUTO_DES1_SHIFT 0
/* CM_AUTOIDLE3_CORE */
#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
#define OMAP3430_AUTO_MAD2D_SHIFT 3
#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
/* CM_CLKSEL_CORE */
#define OMAP3430_CLKSEL_SSI_SHIFT 8
#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT11_SHIFT 7
#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT10_SHIFT 6
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_L4_SHIFT 2
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKSEL_L4_WIDTH 2
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
#define OMAP3430_CLKSEL_L3_WIDTH 2
#define OMAP3630_CLKSEL_96M_SHIFT 12
#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
#define OMAP3630_CLKSEL_96M_WIDTH 2
/* CM_CLKSTCTRL_CORE */
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */
#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */
#define OMAP3430ES1_EN_3D_MASK (1 << 2)
#define OMAP3430ES1_EN_3D_SHIFT 2
#define OMAP3430ES1_EN_2D_MASK (1 << 1)
#define OMAP3430ES1_EN_2D_SHIFT 1
/* CM_ICLKEN_GFX specific bits */
/* CM_IDLEST_GFX specific bits */
/* CM_CLKSEL_GFX specific bits */
/* CM_SLEEPDEP_GFX specific bits */
/* CM_CLKSTCTRL_GFX */
#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
/* CM_CLKSTST_GFX */
#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
/* CM_FCLKEN_SGX */
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
/* CM_IDLEST_SGX */
#define OMAP3430ES2_ST_SGX_SHIFT 1
#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
/* CM_ICLKEN_SGX */
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
/* CM_CLKSEL_SGX */
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
/* CM_CLKSTCTRL_SGX */
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
/* CM_CLKSTST_SGX */
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
/* CM_ICLKEN_WKUP specific bits */
#define OMAP3430_EN_WDT1_MASK (1 << 4)
#define OMAP3430_EN_WDT1_SHIFT 4
#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
#define OMAP3430_EN_32KSYNC_SHIFT 2
/* CM_IDLEST_WKUP specific bits */
#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
#define OMAP3430_ST_WDT2_SHIFT 5
#define OMAP3430_ST_WDT2_MASK (1 << 5)
#define OMAP3430_ST_WDT1_SHIFT 4
#define OMAP3430_ST_WDT1_MASK (1 << 4)
#define OMAP3430_ST_32KSYNC_SHIFT 2
#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
/* CM_AUTOIDLE_WKUP */
#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
#define OMAP3430_AUTO_WDT2_SHIFT 5
#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
#define OMAP3430_AUTO_WDT1_SHIFT 4
#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
#define OMAP3430_AUTO_GPIO1_SHIFT 3
#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
#define OMAP3430_AUTO_32KSYNC_SHIFT 2
#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
#define OMAP3430_AUTO_GPT12_SHIFT 1
#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
#define OMAP3430_AUTO_GPT1_SHIFT 0
/* CM_CLKSEL_WKUP */
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
#define OMAP3430_CLKSEL_RM_SHIFT 1
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
#define OMAP3430_CLKSEL_RM_WIDTH 2
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
/* CM_CLKEN_PLL */
#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
#define OMAP3430_PWRDN_CAM_SHIFT 30
#define OMAP3430_PWRDN_DSS1_SHIFT 29
#define OMAP3430_PWRDN_TV_SHIFT 28
#define OMAP3430_PWRDN_96M_SHIFT 27
#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_CORE_DPLL_SHIFT 0
#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
/* CM_CLKEN2_PLL */
#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_CKGEN */
#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
#define OMAP3430_ST_CORE_CLK_SHIFT 0
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
/* CM_IDLEST2_CKGEN */
#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL */
#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
/* CM_AUTOIDLE2_PLL */
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL */
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
#define OMAP3430_SOURCE_96M_SHIFT 6
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
#define OMAP3430_SOURCE_96M_WIDTH 1
#define OMAP3430_SOURCE_54M_SHIFT 5
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
#define OMAP3430_SOURCE_54M_WIDTH 1
#define OMAP3430_SOURCE_48M_SHIFT 3
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
/* CM_CLKSEL2_PLL */
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
/* CM_CLKSEL3_PLL */
#define OMAP3430_DIV_96M_SHIFT 0
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
#define OMAP3430_DIV_96M_WIDTH 5
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
#define OMAP3630_DIV_96M_WIDTH 6
/* CM_CLKSEL4_PLL */
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL5_PLL */
#define OMAP3430ES2_DIV_120M_SHIFT 0
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
#define OMAP3430ES2_DIV_120M_WIDTH 5
/* CM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT2_EN_SHIFT 7
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
#define OMAP3430_CLKOUT2_DIV_WIDTH 3
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
/* CM_FCLKEN_DSS */
#define OMAP3430_EN_TV_MASK (1 << 2)
#define OMAP3430_EN_TV_SHIFT 2
#define OMAP3430_EN_DSS2_MASK (1 << 1)
#define OMAP3430_EN_DSS2_SHIFT 1
#define OMAP3430_EN_DSS1_MASK (1 << 0)
#define OMAP3430_EN_DSS1_SHIFT 0
/* CM_ICLKEN_DSS */
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
/* CM_IDLEST_DSS */
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
#define OMAP3430ES1_ST_DSS_SHIFT 0
#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
/* CM_AUTOIDLE_DSS */
#define OMAP3430_AUTO_DSS_MASK (1 << 0)
#define OMAP3430_AUTO_DSS_SHIFT 0
/* CM_CLKSEL_DSS */
#define OMAP3430_CLKSEL_TV_SHIFT 8
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
#define OMAP3430_CLKSEL_TV_WIDTH 5
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
#define OMAP3630_CLKSEL_TV_WIDTH 6
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
#define OMAP3430_CLKSEL_DSS1_WIDTH 5
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
#define OMAP3630_CLKSEL_DSS1_WIDTH 6
/* CM_SLEEPDEP_DSS specific bits */
/* CM_CLKSTCTRL_DSS */
#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
/* CM_CLKSTST_DSS */
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
/* CM_FCLKEN_CAM specific bits */
#define OMAP3430_EN_CSI2_MASK (1 << 1)
#define OMAP3430_EN_CSI2_SHIFT 1
/* CM_ICLKEN_CAM specific bits */
/* CM_IDLEST_CAM */
#define OMAP3430_ST_CAM_MASK (1 << 0)
/* CM_AUTOIDLE_CAM */
#define OMAP3430_AUTO_CAM_MASK (1 << 0)
#define OMAP3430_AUTO_CAM_SHIFT 0
/* CM_CLKSEL_CAM */
#define OMAP3430_CLKSEL_CAM_SHIFT 0
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
#define OMAP3430_CLKSEL_CAM_WIDTH 5
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
#define OMAP3630_CLKSEL_CAM_WIDTH 6
/* CM_SLEEPDEP_CAM specific bits */
/* CM_CLKSTCTRL_CAM */
#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
/* CM_CLKSTST_CAM */
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
/* CM_FCLKEN_PER specific bits */
/* CM_ICLKEN_PER specific bits */
/* CM_IDLEST_PER */
#define OMAP3430_ST_WDT3_SHIFT 12
#define OMAP3430_ST_WDT3_MASK (1 << 12)
#define OMAP3430_ST_MCBSP4_SHIFT 2
#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
#define OMAP3430_ST_MCBSP3_SHIFT 1
#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
#define OMAP3430_ST_MCBSP2_SHIFT 0
#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
/* CM_AUTOIDLE_PER */
#define OMAP3630_AUTO_UART4_MASK (1 << 18)
#define OMAP3630_AUTO_UART4_SHIFT 18
#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
#define OMAP3430_AUTO_GPIO6_SHIFT 17
#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
#define OMAP3430_AUTO_GPIO5_SHIFT 16
#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
#define OMAP3430_AUTO_GPIO4_SHIFT 15
#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
#define OMAP3430_AUTO_GPIO3_SHIFT 14
#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
#define OMAP3430_AUTO_GPIO2_SHIFT 13
#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
#define OMAP3430_AUTO_WDT3_SHIFT 12
#define OMAP3430_AUTO_UART3_MASK (1 << 11)
#define OMAP3430_AUTO_UART3_SHIFT 11
#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
#define OMAP3430_AUTO_GPT9_SHIFT 10
#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
#define OMAP3430_AUTO_GPT8_SHIFT 9
#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
#define OMAP3430_AUTO_GPT7_SHIFT 8
#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
#define OMAP3430_AUTO_GPT6_SHIFT 7
#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
#define OMAP3430_AUTO_GPT5_SHIFT 6
#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
#define OMAP3430_AUTO_GPT4_SHIFT 5
#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
#define OMAP3430_AUTO_GPT3_SHIFT 4
#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
#define OMAP3430_AUTO_GPT2_SHIFT 3
#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
#define OMAP3430_AUTO_MCBSP4_SHIFT 2
#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
#define OMAP3430_AUTO_MCBSP3_SHIFT 1
#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
#define OMAP3430_AUTO_MCBSP2_SHIFT 0
/* CM_CLKSEL_PER */
#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT9_SHIFT 7
#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT8_SHIFT 6
#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
#define OMAP3430_CLKSEL_GPT7_SHIFT 5
#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
#define OMAP3430_CLKSEL_GPT6_SHIFT 4
#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
#define OMAP3430_CLKSEL_GPT5_SHIFT 3
#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
#define OMAP3430_CLKSEL_GPT4_SHIFT 2
#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
#define OMAP3430_CLKSEL_GPT3_SHIFT 1
#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
/* CM_SLEEPDEP_PER specific bits */
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_PER */
#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
/* CM_CLKSTST_PER */
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
/* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
#define OMAP3430_DIV_DPLL4_WIDTH 5
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
#define OMAP3630_DIV_DPLL4_WIDTH 6
#define OMAP3430_DIV_DPLL3_SHIFT 16
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
#define OMAP3430_DIV_DPLL3_WIDTH 5
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
#define OMAP3430_CLKSEL_PCLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
#define OMAP3430_MUX_CTRL_SHIFT 0
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
#define OMAP3430_MUX_CTRL_WIDTH 2
/* CM_CLKSTCTRL_EMU */
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
/* CM_CLKSTST_EMU */
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
/* CM_CLKSEL2_EMU specific bits */
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_CLKSEL3_EMU specific bits */
#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_POLCTRL */
#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
/* CM_IDLEST_NEON */
#define OMAP3430_ST_NEON_MASK (1 << 0)
/* CM_CLKSTCTRL_NEON */
#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
/* CM_FCLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
/* CM_ICLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST_SHIFT 0
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
/* CM_IDLEST_USBHOST */
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
/* CM_AUTOIDLE_USBHOST */
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
/* CM_SLEEPDEP_USBHOST */
#define OMAP3430ES2_EN_MPU_SHIFT 1
#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
#define OMAP3430ES2_EN_IVA2_SHIFT 2
#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_USBHOST */
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
/* CM_CLKSTST_USBHOST */
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
/*
*
*/
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
#endif
arch/arm/mach-omap2/cm-regbits-44xx.h
View file @ 311b79bb
......@@ -22,1683 +22,125 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_ABE_DYNDEP_SHIFT 3
#define OMAP4430_ABE_DYNDEP_WIDTH 0x1
#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_ABE_STATDEP_WIDTH 0x1
#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1
#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1
#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
/*
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
* CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
* CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
*/
#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1
#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1
#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1
#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9)
/* Used by CM_DUCATI_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8)
/* Used by CM_IVAHD_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
/* Used by CM_L3_1_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
/* Used by CM_L3_2_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8)
/* Used by CM_SDMA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
/* Used by CM_D2D_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
/* Used by CM_MPU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
/* Used by CM1_ABE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
/* Used by CM_GFX_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10)
/* Used by CM_ALWON_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
/* Used by CM_TESLA_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
/* Used by CM_WKUP_CLKSTCTRL */
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1
#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
/*
* Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
* CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
* CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
* CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
* CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
*/
#define OMAP4430_CLKSEL_SHIFT 24
#define OMAP4430_CLKSEL_WIDTH 0x1
#define OMAP4430_CLKSEL_MASK (1 << 24)
/*
* Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
* CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
*/
#define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
#define OMAP4430_CLKSEL_0_1_SHIFT 0
#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0)
/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
#define OMAP4430_CLKSEL_24_25_SHIFT 24
#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_CLKSEL_60M_SHIFT 24
#define OMAP4430_CLKSEL_60M_WIDTH 0x1
#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
/* Used by CM1_ABE_AESS_CLKCTRL */
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1
#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_CLKSEL_DIV_SHIFT 24
#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1
#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP4430_CLKSEL_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
/* Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25)
/*
* Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL
*/
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_WIDTH 0x1
#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1
#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_WIDTH 0x1
#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_CLKSEL_OPP_SHIFT 0
#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3
#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
/* Used by CM_GFX_GFX_CLKCTRL */
#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1
#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
/*
* Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
* CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
*/
#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2
#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
/*
* Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
* CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
* CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
* CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
* CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
* CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
*/
#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_WIDTH 0x2
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7
#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb
#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_CUSTOM_SHIFT 6
#define OMAP4430_CUSTOM_WIDTH 0x2
#define OMAP4430_CUSTOM_MASK (0x3 << 6)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_D2D_DYNDEP_SHIFT 18
#define OMAP4430_D2D_DYNDEP_WIDTH 0x1
#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
/* Used by CM_MPU_STATICDEP */
#define OMAP4430_D2D_STATDEP_SHIFT 18
#define OMAP4430_D2D_STATDEP_WIDTH 0x1
#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
/* Used by CM_CLKSEL_DPLL_MPU */
#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8
#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
/* Used by CM_CLKSEL_DPLL_MPU */
#define OMAP4460_DCC_EN_SHIFT 22
#define OMAP4460_DCC_EN_MASK (1 << 22)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
* CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
* CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
*/
#define OMAP4430_DELTAMSTEP_SHIFT 0
#define OMAP4430_DELTAMSTEP_WIDTH 0x14
#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15
#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
/* Used by CM_DLL_CTRL */
#define OMAP4430_DLL_OVERRIDE_SHIFT 0
#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1
#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1
#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_RESET_SHIFT 3
#define OMAP4430_DLL_RESET_WIDTH 0x1
#define OMAP4430_DLL_RESET_MASK (1 << 3)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
*/
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
/*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
/*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5
#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5
#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_DIV_SHIFT 0
#define OMAP4430_DPLL_DIV_WIDTH 0x7
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_EN_SHIFT 0
#define OMAP4430_DPLL_EN_WIDTH 0x3
#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
* CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
* CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_MULT_SHIFT 8
#define OMAP4430_DPLL_MULT_WIDTH 0xb
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_MULT_USB_SHIFT 8
#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_USB */
#define OMAP4430_DPLL_SD_DIV_SHIFT 24
#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1
#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
* CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
* CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_EN_SHIFT 12
#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1
#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_DSS_DYNDEP_SHIFT 8
#define OMAP4430_DSS_DYNDEP_WIDTH 0x1
#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DSS_STATDEP_WIDTH 0x1
#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1
#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1
#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_FREQ_UPDATE_SHIFT 0
#define OMAP4430_FREQ_UPDATE_WIDTH 0x1
#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_FUNC_SHIFT 16
#define OMAP4430_FUNC_WIDTH 0xc
#define OMAP4430_FUNC_MASK (0xfff << 16)
/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_GFX_DYNDEP_SHIFT 10
#define OMAP4430_GFX_DYNDEP_WIDTH 0x1
#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_GFX_STATDEP_WIDTH 0x1
#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1
#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
/*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
/*
* Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
* CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
* CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
* CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
* CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
* CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
* CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
* CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
* CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
* CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
* CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
* CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
*/
#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_WIDTH 0x2
#define OMAP4430_IDLEST_MASK (0x3 << 16)
/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ISS_DYNDEP_SHIFT 9
#define OMAP4430_ISS_DYNDEP_WIDTH 0x1
#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
/*
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
* CM_TESLA_STATICDEP
*/
#define OMAP4430_ISS_STATDEP_SHIFT 9
#define OMAP4430_ISS_STATDEP_WIDTH 0x1
#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1
#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
/*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
* CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1
#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1
#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1
#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
/*
* Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_L3_1_DYNDEP_SHIFT 5
#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1
#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
/*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_1_STATDEP_WIDTH 0x1
#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
/*
* Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
* CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
* CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
*/
#define OMAP4430_L3_2_DYNDEP_SHIFT 6
#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1
#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
/*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L3_2_STATDEP_WIDTH 0x1
#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
/* Used by CM_L3_1_DYNAMICDEP */
#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1
#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1
#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_L4PER_DYNDEP_SHIFT 13
#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1
#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
/*
* Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
* CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4PER_STATDEP_WIDTH 0x1
#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1
#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
/*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP
*/
#define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1
#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1
#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
/*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1
#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
/*
* Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_MPU_DYNAMICDEP
*/
#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1
#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
/*
* Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
* CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
* CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1
#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3
#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
* CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7
#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
* CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
* CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
* CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
* CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
* CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
* CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
* CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
* CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
* CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
* CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
* CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
* CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
* CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
* CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
* CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
* CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
* CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
* CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
* CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
* CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
* CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
* CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
*/
#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_WIDTH 0x2
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4460_MPU_DYNDEP_SHIFT 19
#define OMAP4460_MPU_DYNDEP_WIDTH 0x1
#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
/* Used by CM_WKUP_BANDGAP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8)
/* Used by CM_ALWON_USBPHY_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8)
/* Used by CM_CAM_ISS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/*
* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
* CM_WKUP_GPIO1_CLKCTRL
*/
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8)
/* Used by CM_WKUP_USIM_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9)
/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9)
/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8)
/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10)
/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
/* Used by CM_WKUP_BANDGAP_CLKCTRL */
#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1
#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1
#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8)
/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1
#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1
#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8)
/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
#define OMAP4430_PERF_CURRENT_SHIFT 0
#define OMAP4430_PERF_CURRENT_WIDTH 0x8
#define OMAP4430_PERF_CURRENT_MASK (0xff << 0)
/*
* Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
* CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
* CM_IVA_DVFS_PERF_TESLA
*/
#define OMAP4430_PERF_REQ_SHIFT 0
#define OMAP4430_PERF_REQ_WIDTH 0x8
#define OMAP4430_PERF_REQ_MASK (0xff << 0)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1
#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1
#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1)
/* Used by CM_RESTORE_ST */
#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1
#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20)
/* Used by CM_EMU_DEBUGSS_CLKCTRL */
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
/* Used by CM_DYN_DEP_PRESCAL */
#define OMAP4430_PRESCAL_SHIFT 0
#define OMAP4430_PRESCAL_WIDTH 0x6
#define OMAP4430_PRESCAL_MASK (0x3f << 0)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_R_RTL_SHIFT 11
#define OMAP4430_R_RTL_WIDTH 0x5
#define OMAP4430_R_RTL_MASK (0x1f << 11)
/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_SAR_MODE_SHIFT 4
#define OMAP4430_SAR_MODE_WIDTH 0x1
#define OMAP4430_SAR_MODE_MASK (1 << 4)
/* Used by CM_SCALE_FCLK */
#define OMAP4430_SCALE_FCLK_SHIFT 0
#define OMAP4430_SCALE_FCLK_WIDTH 0x1
#define OMAP4430_SCALE_FCLK_MASK (1 << 0)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_SCHEME_SHIFT 30
#define OMAP4430_SCHEME_WIDTH 0x2
#define OMAP4430_SCHEME_MASK (0x3 << 30)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_SDMA_DYNDEP_SHIFT 11
#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1
#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_SDMA_STATDEP_SHIFT 11
#define OMAP4430_SDMA_STATDEP_WIDTH 0x1
#define OMAP4430_SDMA_STATDEP_MASK (1 << 11)
/* Used by CM_CLKSEL_ABE */
#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1
#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10)
/*
* Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
* CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
* CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
*/
#define OMAP4430_STBYST_SHIFT 18
#define OMAP4430_STBYST_WIDTH 0x1
#define OMAP4430_STBYST_MASK (1 << 18)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
* CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
*/
#define OMAP4430_ST_DPLL_CLK_SHIFT 0
#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1
#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_USB */
#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/*
* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1
#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
/*
* Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
* CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/*
* Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
* CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
* CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
* CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
*/
#define OMAP4430_ST_MN_BYPASS_SHIFT 8
#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1
#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_SYS_CLKSEL */
#define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_TESLA_DYNDEP_SHIFT 1
#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1
#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
#define OMAP4430_TESLA_STATDEP_SHIFT 1
#define OMAP4430_TESLA_STATDEP_WIDTH 0x1
#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
/*
* Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
* CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_WINDOWSIZE_SHIFT 24
#define OMAP4430_WINDOWSIZE_WIDTH 0x4
#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_X_MAJOR_SHIFT 8
#define OMAP4430_X_MAJOR_WIDTH 0x3
#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
/* Used by REVISION_CM1, REVISION_CM2 */
#define OMAP4430_Y_MINOR_SHIFT 0
#define OMAP4430_Y_MINOR_WIDTH 0x6
#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
#endif
arch/arm/mach-omap2/cm-regbits-54xx.h
View file @ 311b79bb
......@@ -21,1717 +21,84 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
#define OMAP54XX_ABE_DYNDEP_SHIFT 3
#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_ABE_STATDEP_SHIFT 3
#define OMAP54XX_ABE_STATDEP_WIDTH 0x1
#define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
/*
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
* CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
*/
#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_C2C_DYNDEP_SHIFT 18
#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
/* Used by CM_MPU_STATICDEP */
#define OMAP54XX_C2C_STATDEP_SHIFT 18
#define OMAP54XX_C2C_STATDEP_WIDTH 0x1
#define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_CAM_DYNDEP_SHIFT 9
#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
/*
* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
* CM_MPU_STATICDEP
*/
#define OMAP54XX_CAM_STATDEP_SHIFT 9
#define OMAP54XX_CAM_STATDEP_WIDTH 0x1
#define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
/* Used by CM_C2C_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
/* Used by CM_CUSTEFUSE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
/* Used by CM_CUSTEFUSE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
/* Used by CM_DMA_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
/* Used by CM_DSP_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
/* Used by CM_EMIF_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
/* Used by CM_EMU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
/* Used by CM_CAM_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
/* Used by CM_GPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
/* Used by CM_DSS_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
/* Used by CM_IPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
/* Used by CM_IVA_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3INSTR_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
/* Used by CM_L3MAIN1_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
/* Used by CM_L3MAIN2_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
/* Used by CM_L4SEC_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
/* Used by CM_MPU_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
/* Used by CM_ABE_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
/* Used by CM_COREAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
/* Used by CM_MIPIEXT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
/* Used by CM_WKUPAON_CLKSTCTRL */
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
/*
* Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SHIFT 24
#define OMAP54XX_CLKSEL_WIDTH 0x1
#define OMAP54XX_CLKSEL_MASK (1 << 24)
/*
* Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
* CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
*/
#define OMAP54XX_CLKSEL_0_0_SHIFT 0
#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
#define OMAP54XX_CLKSEL_0_1_SHIFT 0
#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
#define OMAP54XX_CLKSEL_24_25_SHIFT 24
#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
/* Used by CM_ABE_AESS_CLKCTRL */
#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
#define OMAP54XX_CLKSEL_DIV_SHIFT 25
#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
/* Used by CM_MPU_MPU_CLKCTRL */
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP54XX_CLKSEL_FCLK_SHIFT 24
#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
/* Used by CM_GPU_GPU_CLKCTRL */
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
/*
* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
*/
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
/* Used by CM_CLKSEL_CORE */
#define OMAP54XX_CLKSEL_L3_SHIFT 4
#define OMAP54XX_CLKSEL_L3_WIDTH 0x1
#define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
/* Used by CM_CLKSEL_CORE */
#define OMAP54XX_CLKSEL_L4_SHIFT 8
#define OMAP54XX_CLKSEL_L4_WIDTH 0x1
#define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
/* Used by CM_EMIF_EMIF1_CLKCTRL */
#define OMAP54XX_CLKSEL_LL_SHIFT 24
#define OMAP54XX_CLKSEL_LL_WIDTH 0x1
#define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_CLKSEL_OPP_SHIFT 0
#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
/*
* Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
* CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
/*
* Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL
*/
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
/*
* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
* CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
* CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
* CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP54XX_CLKST_SHIFT 9
#define OMAP54XX_CLKST_WIDTH 0x1
#define OMAP54XX_CLKST_MASK (1 << 9)
/*
* Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
* CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
* CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
* CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
* CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
* CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
*/
#define OMAP54XX_CLKTRCTRL_SHIFT 0
#define OMAP54XX_CLKTRCTRL_WIDTH 0x2
#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
#define OMAP54XX_CLKX2ST_SHIFT 11
#define OMAP54XX_CLKX2ST_WIDTH 0x1
#define OMAP54XX_CLKX2ST_MASK (1 << 11)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_COREAON_DYNDEP_SHIFT 16
#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_COREAON_STATDEP_SHIFT 16
#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_CUSTOM_SHIFT 6
#define OMAP54XX_CUSTOM_WIDTH 0x2
#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DCC_EN_SHIFT 22
#define OMAP54XX_DCC_EN_WIDTH 0x1
#define OMAP54XX_DCC_EN_MASK (1 << 22)
/*
* Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
* CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
* CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
*/
#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
* CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
* CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
* CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
* CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
* CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
/*
* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
* CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
*/
#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
* CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define OMAP54XX_DELTAMSTEP_SHIFT 0
#define OMAP54XX_DELTAMSTEP_WIDTH 0x14
#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
/*
* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
* CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
*/
#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
/*
* Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
* CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
* CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
* CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
* CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
*/
#define OMAP54XX_DIVHS_SHIFT 0
#define OMAP54XX_DIVHS_WIDTH 0x6
#define OMAP54XX_DIVHS_MASK (0x3f << 0)
/*
* Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
* CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
* CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
*/
#define OMAP54XX_DIVHS_0_4_SHIFT 0
#define OMAP54XX_DIVHS_0_4_WIDTH 0x5
#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
/*
* Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
* CM_DIV_M2_DPLL_USB
*/
#define OMAP54XX_DIVHS_0_6_SHIFT 0
#define OMAP54XX_DIVHS_0_6_WIDTH 0x7
#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
/* Used by CM_DLL_CTRL */
#define OMAP54XX_DLL_OVERRIDE_SHIFT 0
#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DLL_RESET_SHIFT 3
#define OMAP54XX_DLL_RESET_WIDTH 0x1
#define OMAP54XX_DLL_RESET_MASK (1 << 3)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
*/
#define OMAP54XX_DPLL_DIV_SHIFT 0
#define OMAP54XX_DPLL_DIV_WIDTH 0x7
#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
/*
* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_EN_SHIFT 0
#define OMAP54XX_DPLL_EN_WIDTH 0x3
#define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
* CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
*/
#define OMAP54XX_DPLL_MULT_SHIFT 8
#define OMAP54XX_DPLL_MULT_WIDTH 0xb
#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
/*
* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
* CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
*/
#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
#define OMAP54XX_DPLL_SD_DIV_SHIFT 24
#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
* CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
*/
#define OMAP54XX_DPLL_SSC_EN_SHIFT 12
#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_DSP_DYNDEP_SHIFT 1
#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_DSP_STATDEP_SHIFT 1
#define OMAP54XX_DSP_STATDEP_WIDTH 0x1
#define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_DSS_DYNDEP_SHIFT 8
#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_DSS_STATDEP_SHIFT 8
#define OMAP54XX_DSS_STATDEP_WIDTH 0x1
#define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
/*
* Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
* CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_EMIF_DYNDEP_SHIFT 4
#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_EMIF_STATDEP_SHIFT 4
#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP54XX_FREQ_UPDATE_SHIFT 0
#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_FUNC_SHIFT 16
#define OMAP54XX_FUNC_WIDTH 0xc
#define OMAP54XX_FUNC_MASK (0xfff << 16)
/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_GPU_DYNDEP_SHIFT 10
#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_GPU_STATDEP_SHIFT 10
#define OMAP54XX_GPU_STATDEP_WIDTH 0x1
#define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
*/
#define OMAP54XX_IDLEST_SHIFT 16
#define OMAP54XX_IDLEST_WIDTH 0x2
#define OMAP54XX_IDLEST_MASK (0x3 << 16)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_IPU_DYNDEP_SHIFT 0
#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_IPU_STATDEP_SHIFT 0
#define OMAP54XX_IPU_STATDEP_WIDTH 0x1
#define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_IVA_DYNDEP_SHIFT 2
#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_IVA_STATDEP_SHIFT 2
#define OMAP54XX_IVA_STATDEP_WIDTH 0x1
#define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3INIT_STATDEP_SHIFT 7
#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
/*
* Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
* CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
/*
* Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
* CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
* CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
*/
#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
/*
* Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
* CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
* CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
/* Used by CM_L3MAIN1_DYNAMICDEP */
#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L4CFG_STATDEP_SHIFT 12
#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
/* Used by CM_L3MAIN2_DYNAMICDEP */
#define OMAP54XX_L4PER_DYNDEP_SHIFT 13
#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
/*
* Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
* CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
* CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_L4PER_STATDEP_SHIFT 13
#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
/*
* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
* CM_MPU_STATICDEP
*/
#define OMAP54XX_L4SEC_STATDEP_SHIFT 14
#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
/* Used by CM_MPU_STATICDEP */
#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
* CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
* CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
* CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
* CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
* CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
* CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
* CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
* CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
* CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
* CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
* CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
* CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
* CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
* CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
* CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
* CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
* CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
* CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
* CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
* CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
* CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
* CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
* CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
* CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
* CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
* CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
* CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
* CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
* CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
* CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
* CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
* CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
* CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
* CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
* CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
* CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
* CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
* CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
* CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
* CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
* CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
* CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
* CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
* CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
* CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
*/
#define OMAP54XX_MODULEMODE_SHIFT 0
#define OMAP54XX_MODULEMODE_WIDTH 0x2
#define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_MPU_DYNDEP_SHIFT 19
#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
/* Used by CM_CAM_ISS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/*
* Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
* CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
* CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
*/
#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
/* Used by CM_L3INIT_SATA_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
/* Used by CM_WKUPAON_SCRM_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
/* Used by CM_WKUPAON_SCRM_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
/* Used by CM_MIPIEXT_LLI_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
/* Used by CM_MIPIEXT_LLI_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
#define OMAP54XX_OUTPUT_SHIFT 0
#define OMAP54XX_OUTPUT_WIDTH 0x20
#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
/* Used by CM_RESTORE_ST */
#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
/* Used by CM_DYN_DEP_PRESCAL */
#define OMAP54XX_PRESCAL_SHIFT 0
#define OMAP54XX_PRESCAL_WIDTH 0x6
#define OMAP54XX_PRESCAL_MASK (0x3f << 0)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_R_RTL_SHIFT 11
#define OMAP54XX_R_RTL_WIDTH 0x5
#define OMAP54XX_R_RTL_MASK (0x1f << 11)
/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
#define OMAP54XX_SAR_MODE_SHIFT 4
#define OMAP54XX_SAR_MODE_WIDTH 0x1
#define OMAP54XX_SAR_MODE_MASK (1 << 4)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_SCHEME_SHIFT 30
#define OMAP54XX_SCHEME_WIDTH 0x2
#define OMAP54XX_SCHEME_MASK (0x3 << 30)
/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP54XX_SDMA_DYNDEP_SHIFT 11
#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
#define OMAP54XX_SDMA_STATDEP_SHIFT 11
#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL0_SHIFT 0
#define OMAP54XX_SEL0_WIDTH 0x7
#define OMAP54XX_SEL0_MASK (0x7f << 0)
/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL0_0_7_SHIFT 0
#define OMAP54XX_SEL0_0_7_WIDTH 0x8
#define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL1_SHIFT 8
#define OMAP54XX_SEL1_WIDTH 0x7
#define OMAP54XX_SEL1_MASK (0x7f << 8)
/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL2_SHIFT 16
#define OMAP54XX_SEL2_WIDTH 0x7
#define OMAP54XX_SEL2_MASK (0x7f << 16)
/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
/* Used by CM_CORE_AON_DEBUG_CFG */
#define OMAP54XX_SEL3_SHIFT 24
#define OMAP54XX_SEL3_WIDTH 0x7
#define OMAP54XX_SEL3_MASK (0x7f << 24)
/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
/* Used by CM_CLKSEL_ABE */
#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
/*
* Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
* CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
* CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
* CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
* CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
* CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
* CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
* CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
*/
#define OMAP54XX_STBYST_SHIFT 18
#define OMAP54XX_STBYST_WIDTH 0x1
#define OMAP54XX_STBYST_MASK (1 << 18)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_CLK_SHIFT 0
#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
/*
* Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
* CM_CLKDCOLDO_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_INIT_SHIFT 4
#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
/*
* Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
* CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
*/
#define OMAP54XX_ST_DPLL_MODE_SHIFT 1
#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
/* Used by CM_CLKSEL_SYS */
#define OMAP54XX_SYS_CLKSEL_SHIFT 0
#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
/*
* Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
* CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
* CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
* CM_MPU_DYNAMICDEP
*/
#define OMAP54XX_WINDOWSIZE_SHIFT 24
#define OMAP54XX_WINDOWSIZE_WIDTH 0x4
#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
/* Used by CM_L3MAIN1_DYNAMICDEP */
#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
/*
* Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
* CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
*/
#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_X_MAJOR_SHIFT 8
#define OMAP54XX_X_MAJOR_WIDTH 0x3
#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
#define OMAP54XX_Y_MINOR_SHIFT 0
#define OMAP54XX_Y_MINOR_WIDTH 0x6
#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
#endif
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file @ 311b79bb
......@@ -32,7 +32,6 @@
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
#include "prm-regbits-54xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
......
arch/arm/mach-omap2/powerdomains54xx_data.c
View file @ 311b79bb
......@@ -25,7 +25,6 @@
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm_mpu54xx.h"
......
arch/arm/mach-omap2/prm-regbits-24xx.h
View file @ 311b79bb
......@@ -16,274 +16,27 @@
#include "prm2xxx.h"
/* Bits shared between registers */
/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
#define OMAP24XX_EN_MPU_SHIFT 1
#define OMAP24XX_EN_MPU_MASK (1 << 1)
#define OMAP24XX_EN_CORE_SHIFT 0
#define OMAP24XX_EN_CORE_MASK (1 << 0)
/*
* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
* shared bits
*/
#define OMAP24XX_MEMONSTATE_SHIFT 10
#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
#define OMAP24XX_FORCESTATE_MASK (1 << 18)
/*
* PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
* PM_PWSTST_MDM shared bits
*/
#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
#define OMAP2430_MEMSTATEST_SHIFT 10
#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
#define OMAP24XX_POWERSTATEST_SHIFT 0
#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
/* Bits specific to each register */
/* PRCM_REVISION */
#define OMAP24XX_REV_SHIFT 0
#define OMAP24XX_REV_MASK (0xff << 0)
/* PRCM_SYSCONFIG */
#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
/* PRCM_IRQSTATUS_MPU specific bits */
#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
/* PRCM_IRQENABLE_MPU specific bits */
#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
/* PRCM_VOLTCTRL */
#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
#define OMAP24XX_SETRET_LEVEL_SHIFT 6
#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
#define OMAP24XX_VOLT_LEVEL_SHIFT 0
#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
/* PRCM_VOLTST */
#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
/* PRCM_CLKSRC_CTRL specific bits */
/* PRCM_CLKOUT_CTRL */
#define OMAP2420_CLKOUT2_EN_SHIFT 15
#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
#define OMAP2420_CLKOUT2_DIV_SHIFT 11
#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
#define OMAP2420_CLKOUT2_DIV_WIDTH 3
#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
#define OMAP24XX_CLKOUT_EN_SHIFT 7
#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
#define OMAP24XX_CLKOUT_DIV_SHIFT 3
#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
#define OMAP24XX_CLKOUT_DIV_WIDTH 3
#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
/* PRCM_CLKEMUL_CTRL */
#define OMAP24XX_EMULATION_EN_SHIFT 0
#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
/* PRCM_CLKCFG_CTRL */
#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
/* PRCM_CLKCFG_STATUS */
#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
/* PRCM_VOLTSETUP specific bits */
/* PRCM_CLKSSETUP specific bits */
/* PRCM_POLCTRL */
#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
#define OMAP2430_USE_POWEROK_MASK (1 << 2)
#define OMAP2430_POWEROK_POL_MASK (1 << 1)
#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
/* RM_RSTST_MPU specific bits */
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
/* PM_WKDEP_MPU specific bits */
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
/* PM_EVGENCTRL_MPU specific bits */
/* PM_EVEGENONTIM_MPU specific bits */
/* PM_EVEGENOFFTIM_MPU specific bits */
/* PM_PWSTCTRL_MPU specific bits */
#define OMAP2430_FORCESTATE_MASK (1 << 18)
/* PM_PWSTST_MPU specific bits */
/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
/* PM_WKEN1_CORE specific bits */
/* PM_WKEN2_CORE specific bits */
/* PM_WKST1_CORE specific bits*/
/* PM_WKST2_CORE specific bits */
/* PM_WKDEP_CORE specific bits*/
#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
/* PM_PWSTCTRL_CORE specific bits */
#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
#define OMAP24XX_MEM3ONSTATE_SHIFT 14
#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
#define OMAP24XX_MEM2ONSTATE_SHIFT 12
#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
#define OMAP24XX_MEM1ONSTATE_SHIFT 10
#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
/* PM_PWSTST_CORE specific bits */
#define OMAP24XX_MEM3STATEST_SHIFT 14
#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
#define OMAP24XX_MEM2STATEST_SHIFT 12
#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
#define OMAP24XX_MEM1STATEST_SHIFT 10
#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
/* RM_RSTCTRL_GFX */
#define OMAP24XX_GFX_RST_MASK (1 << 0)
/* RM_RSTST_GFX specific bits */
#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
/* PM_PWSTCTRL_GFX specific bits */
/* PM_WKDEP_GFX specific bits */
/* 2430 often calls EN_WAKEUP "EN_WKUP" */
/* RM_RSTCTRL_WKUP specific bits */
/* RM_RSTTIME_WKUP specific bits */
/* RM_RSTST_WKUP specific bits */
/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
#define OMAP24XX_EXTWMPU_RST_SHIFT 6
#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
#define OMAP24XX_SECU_WD_RST_SHIFT 5
#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
#define OMAP24XX_MPU_WD_RST_SHIFT 4
#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
/* PM_WKEN_WKUP specific bits */
/* PM_WKST_WKUP specific bits */
/* RM_RSTCTRL_DSP */
#define OMAP2420_RST_IVA_MASK (1 << 8)
#define OMAP24XX_RST2_DSP_MASK (1 << 1)
#define OMAP24XX_RST1_DSP_MASK (1 << 0)
/* RM_RSTST_DSP specific bits */
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
/* PM_WKDEP_DSP specific bits */
/* PM_PWSTCTRL_DSP specific bits */
/* 2430 only: MEMONSTATE, MEMRETSTATE */
#define OMAP2420_MEMIONSTATE_SHIFT 12
#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
/* PM_PWSTST_DSP specific bits */
/* MEMSTATEST is 2430 only */
#define OMAP2420_MEMISTATEST_SHIFT 12
#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
/* PRCM_IRQSTATUS_DSP specific bits */
/* PRCM_IRQENABLE_DSP specific bits */
/* RM_RSTCTRL_MDM */
/* 2430 only */
#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
#define OMAP2430_RST1_MDM_MASK (1 << 0)
/* RM_RSTST_MDM specific bits */
/* 2430 only */
#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
/* PM_WKEN_MDM */
/* 2430 only */
#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
/* PM_WKST_MDM specific bits */
/* 2430 only */
/* PM_WKDEP_MDM specific bits */
/* 2430 only */
/* PM_PWSTCTRL_MDM specific bits */
/* 2430 only */
#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
/* PM_PWSTST_MDM specific bits */
/* 2430 only */
/* PRCM_IRQSTATUS_IVA */
/* 2420 only */
/* PRCM_IRQENABLE_IVA */
/* 2420 only */
#endif
arch/arm/mach-omap2/prm-regbits-33xx.h
View file @ 311b79bb
......@@ -18,340 +18,34 @@
#include "prm.h"
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_AIPOFF_SHIFT 8
#define AM33XX_AIPOFF_MASK (1 << 8)
/* Used by PM_WKUP_PWRSTST */
#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
/* Used by RM_WKUP_RSTST */
#define AM33XX_EMULATION_M3_RST_SHIFT 6
#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
/* Used by RM_MPU_RSTST */
#define AM33XX_EMULATION_MPU_RST_SHIFT 5
#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC4_SHIFT 6
#define AM33XX_ENFUNC4_MASK (1 << 6)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC5_SHIFT 7
#define AM33XX_ENFUNC5_MASK (1 << 7)
/* Used by PRM_RSTST */
#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_FORCEWKUP_EN_SHIFT 10
#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_FORCEWKUP_ST_SHIFT 10
#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
/* Used by PM_GFX_PWRSTST */
#define AM33XX_GFX_MEM_STATEST_SHIFT 4
#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
#define AM33XX_GFX_RST_SHIFT 0
#define AM33XX_GFX_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
/* Used by RM_WKUP_RSTST */
#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
/* Used by RM_MPU_RSTST */
#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
/* Used by PRM_RSTST */
#define AM33XX_ICEPICK_RST_SHIFT 9
#define AM33XX_ICEPICK_RST_MASK (1 << 9)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PRUSS_LRST_SHIFT 1
#define AM33XX_PRUSS_LRST_MASK (1 << 1)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_INTRANSITION_SHIFT 20
#define AM33XX_INTRANSITION_MASK (1 << 20)
/* Used by PM_CEFUSE_PWRSTST */
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_SHIFT 2
#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_LOGICSTATEST_SHIFT 2
#define AM33XX_LOGICSTATEST_MASK (1 << 2)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
*/
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L1_STATEST_SHIFT 6
#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L2_STATEST_SHIFT 8
#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_RAM_STATEST_SHIFT 4
#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
/* Used by PRM_RSTST */
#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PCI_LRST_SHIFT 0
#define AM33XX_PCI_LRST_MASK (1 << 0)
/* Renamed from PCI_LRST Used by RM_PER_RSTST */
#define AM33XX_PCI_LRST_5_5_SHIFT 5
#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PER_MEM_STATEST_SHIFT 17
#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL
*/
#define AM33XX_POWERSTATE_SHIFT 0
#define AM33XX_POWERSTATE_MASK (0x3 << 0)
/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
#define AM33XX_POWERSTATEST_SHIFT 0
#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
/* Used by PM_PER_PWRSTST */
#define AM33XX_RAM_MEM_STATEST_SHIFT 21
#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_RETMODE_ENABLE_SHIFT 0
#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
/* Used by REVISION_PRM */
#define AM33XX_REV_SHIFT 0
#define AM33XX_REV_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME1_SHIFT 0
#define AM33XX_RSTTIME1_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME2_SHIFT 8
#define AM33XX_RSTTIME2_MASK (0x1f << 8)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_SLPCNT_VALUE_SHIFT 16
#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAMLDO_STATUS_SHIFT 8
#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_STARTUP_COUNT_SHIFT 24
#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_TRANSITION_EN_SHIFT 8
#define AM33XX_TRANSITION_EN_MASK (1 << 8)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_TRANSITION_ST_SHIFT 8
#define AM33XX_TRANSITION_ST_MASK (1 << 8)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
/* Used by PRM_RSTST */
#define AM33XX_WDT0_RST_SHIFT 3
#define AM33XX_WDT0_RST_MASK (1 << 3)
/* Used by PRM_RSTST */
#define AM33XX_WDT1_RST_SHIFT 4
#define AM33XX_WDT1_RST_MASK (1 << 4)
/* Used by RM_WKUP_RSTCTRL */
#define AM33XX_WKUP_M3_LRST_SHIFT 3
#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
#endif
arch/arm/mach-omap2/prm-regbits-34xx.h
View file @ 311b79bb
......@@ -16,115 +16,25 @@
#include "prm3xxx.h"
/* Shared register bits */
/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
#define OMAP3430_ON_SHIFT 24
#define OMAP3430_ON_MASK (0xff << 24)
#define OMAP3430_ONLP_SHIFT 16
#define OMAP3430_ONLP_MASK (0xff << 16)
#define OMAP3430_RET_SHIFT 8
#define OMAP3430_RET_MASK (0xff << 8)
#define OMAP3430_OFF_SHIFT 0
#define OMAP3430_OFF_MASK (0xff << 0)
/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
#define OMAP3430_ERROROFFSET_SHIFT 24
#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
#define OMAP3430_ERRORGAIN_SHIFT 16
#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
#define OMAP3430_INITVOLTAGE_SHIFT 8
#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
#define OMAP3430_INITVDD_MASK (1 << 2)
#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
#define OMAP3430_VPENABLE_MASK (1 << 0)
/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
#define OMAP3430_VSTEPMIN_SHIFT 0
#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
#define OMAP3430_VSTEPMAX_SHIFT 0
#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
#define OMAP3430_VDDMAX_SHIFT 24
#define OMAP3430_VDDMAX_MASK (0xff << 24)
#define OMAP3430_VDDMIN_SHIFT 16
#define OMAP3430_VDDMIN_MASK (0xff << 16)
#define OMAP3430_TIMEOUT_SHIFT 0
#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
#define OMAP3430_VPVOLTAGE_SHIFT 0
#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
#define OMAP3430_VPINIDLE_MASK (1 << 0)
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
#define OMAP3430_EN_PER_SHIFT 7
#define OMAP3430_EN_PER_MASK (1 << 7)
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
#define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
/*
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
* PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
* PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
*/
#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
#define OMAP3430_WKUP_ST_MASK (1 << 0)
/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
#define OMAP3430_WKUP_EN_MASK (1 << 0)
/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
#define OMAP3430_GRPSEL_I2C3_SHIFT 17
#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
#define OMAP3430_GRPSEL_I2C2_SHIFT 16
#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
#define OMAP3430_GRPSEL_I2C1_SHIFT 15
#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
#define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
/*
* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
* PM_PWSTCTRL_PER shared bits
*/
#define OMAP3430_MEMONSTATE_SHIFT 16
#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
#define OMAP3430_MEMRETSTATE_MASK (1 << 8)
/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
......@@ -132,480 +42,89 @@
#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
/* Bits specific to each register */
/* RM_RSTCTRL_IVA2 */
#define OMAP3430_RST3_IVA2_MASK (1 << 2)
#define OMAP3430_RST2_IVA2_MASK (1 << 1)
#define OMAP3430_RST1_IVA2_MASK (1 << 0)
/* RM_RSTST_IVA2 specific bits */
#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
/* PM_WKDEP_IVA2 specific bits */
/* PM_PWSTCTRL_IVA2 specific bits */
#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
/* PM_PWSTST_IVA2 specific bits */
#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
/* PM_PREPWSTST_IVA2 specific bits */
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
/* PRM_IRQSTATUS_IVA2 specific bits */
#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
/* PRM_IRQENABLE_IVA2 specific bits */
#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
/* PRM_REVISION specific bits */
/* PRM_SYSCONFIG specific bits */
/* PRM_IRQSTATUS_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
#define OMAP3430_IO_ST_MASK (1 << 9)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
#define OMAP3430_MPU_DPLL_ST_SHIFT 7
#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
#define OMAP3430_CORE_DPLL_ST_SHIFT 5
#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
#define OMAP3430_EVGENON_ST_MASK (1 << 2)
#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
/* PRM_IRQENABLE_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
#define OMAP3430_IO_EN_MASK (1 << 9)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
#define OMAP3430_EVGENON_EN_MASK (1 << 2)
#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
/* RM_RSTST_MPU specific bits */
#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
/* PM_WKDEP_MPU specific bits */
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
/* PM_EVGENCTRL_MPU */
#define OMAP3430_OFFLOADMODE_SHIFT 3
#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
#define OMAP3430_ONLOADMODE_SHIFT 1
#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
#define OMAP3430_ENABLE_MASK (1 << 0)
/* PM_EVGENONTIM_MPU */
#define OMAP3430_ONTIMEVAL_SHIFT 0
#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
/* PM_EVGENOFFTIM_MPU */
#define OMAP3430_OFFTIMEVAL_SHIFT 0
#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
/* PM_PWSTCTRL_MPU specific bits */
#define OMAP3430_L2CACHEONSTATE_SHIFT 16
#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
/* PM_PWSTST_MPU specific bits */
#define OMAP3430_L2CACHESTATEST_SHIFT 6
#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
/* PM_PREPWSTST_MPU specific bits */
#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
/* RM_RSTCTRL_CORE */
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
/* RM_RSTST_CORE specific bits */
#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
/* PM_WKEN1_CORE specific bits */
/* PM_MPUGRPSEL1_CORE specific bits */
#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
/* PM_IVA2GRPSEL1_CORE specific bits */
/* PM_WKST1_CORE specific bits */
/* PM_PWSTCTRL_CORE specific bits */
#define OMAP3430_MEM2ONSTATE_SHIFT 18
#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
#define OMAP3430_MEM1ONSTATE_SHIFT 16
#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
/* PM_PWSTST_CORE specific bits */
#define OMAP3430_MEM2STATEST_SHIFT 6
#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
#define OMAP3430_MEM1STATEST_SHIFT 4
#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
/* PM_PREPWSTST_CORE specific bits */
#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
/* RM_RSTST_GFX specific bits */
/* PM_WKDEP_GFX specific bits */
#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_GFX specific bits */
/* PM_PWSTST_GFX specific bits */
/* PM_PREPWSTST_GFX specific bits */
/* PM_WKEN_WKUP specific bits */
#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
#define OMAP3430_EN_IO_MASK (1 << 8)
#define OMAP3430_EN_GPIO1_MASK (1 << 3)
/* PM_MPUGRPSEL_WKUP specific bits */
/* PM_IVA2GRPSEL_WKUP specific bits */
/* PM_WKST_WKUP specific bits */
#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
#define OMAP3430_ST_IO_MASK (1 << 8)
/* PRM_CLKSEL */
#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
/* PRM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT_EN_SHIFT 7
/* RM_RSTST_DSS specific bits */
/* PM_WKEN_DSS */
#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
/* PM_WKDEP_DSS specific bits */
#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_DSS specific bits */
/* PM_PWSTST_DSS specific bits */
/* PM_PREPWSTST_DSS specific bits */
/* RM_RSTST_CAM specific bits */
/* PM_WKDEP_CAM specific bits */
#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_CAM specific bits */
/* PM_PWSTST_CAM specific bits */
/* PM_PREPWSTST_CAM specific bits */
/* PM_PWSTCTRL_USBHOST specific bits */
#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
/* RM_RSTST_PER specific bits */
/* PM_WKEN_PER specific bits */
/* PM_MPUGRPSEL_PER specific bits */
/* PM_IVA2GRPSEL_PER specific bits */
/* PM_WKST_PER specific bits */
/* PM_WKDEP_PER specific bits */
#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_PER specific bits */
/* PM_PWSTST_PER specific bits */
/* PM_PREPWSTST_PER specific bits */
/* RM_RSTST_EMU specific bits */
/* PM_PWSTST_EMU specific bits */
/* PRM_VC_SMPS_SA */
#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
/* PRM_VC_SMPS_VOL_RA */
#define OMAP3430_VOLRA1_SHIFT 16
#define OMAP3430_VOLRA1_MASK (0xff << 16)
#define OMAP3430_VOLRA0_SHIFT 0
#define OMAP3430_VOLRA0_MASK (0xff << 0)
/* PRM_VC_SMPS_CMD_RA */
#define OMAP3430_CMDRA1_SHIFT 16
#define OMAP3430_CMDRA1_MASK (0xff << 16)
#define OMAP3430_CMDRA0_SHIFT 0
#define OMAP3430_CMDRA0_MASK (0xff << 0)
/* PRM_VC_CMD_VAL_0 specific bits */
#define OMAP3430_VC_CMD_ON_SHIFT 24
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
#define OMAP3430_VC_CMD_RET_SHIFT 8
#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
/* PRM_VC_CMD_VAL_1 specific bits */
/* PRM_VC_CH_CONF */
#define OMAP3430_CMD1_MASK (1 << 20)
#define OMAP3430_RACEN1_MASK (1 << 19)
#define OMAP3430_RAC1_MASK (1 << 18)
#define OMAP3430_RAV1_MASK (1 << 17)
#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
#define OMAP3430_CMD0_MASK (1 << 4)
#define OMAP3430_RACEN0_MASK (1 << 3)
#define OMAP3430_RAC0_MASK (1 << 2)
#define OMAP3430_RAV0_MASK (1 << 1)
#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
/* PRM_VC_I2C_CFG */
#define OMAP3430_HSMASTER_MASK (1 << 5)
#define OMAP3430_SREN_MASK (1 << 4)
#define OMAP3430_HSEN_MASK (1 << 3)
#define OMAP3430_MCODE_SHIFT 0
#define OMAP3430_MCODE_MASK (0x7 << 0)
/* PRM_VC_BYPASS_VAL */
#define OMAP3430_VALID_MASK (1 << 24)
#define OMAP3430_DATA_SHIFT 16
#define OMAP3430_DATA_MASK (0xff << 16)
#define OMAP3430_REGADDR_SHIFT 8
#define OMAP3430_REGADDR_MASK (0xff << 8)
#define OMAP3430_SLAVEADDR_SHIFT 0
#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
/* PRM_RSTCTRL */
#define OMAP3430_RST_DPLL3_MASK (1 << 2)
#define OMAP3430_RST_GS_MASK (1 << 1)
/* PRM_RSTTIME */
#define OMAP3430_RSTTIME2_SHIFT 8
#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
#define OMAP3430_RSTTIME1_SHIFT 0
#define OMAP3430_RSTTIME1_MASK (0xff << 0)
/* PRM_RSTST */
#define OMAP3430_ICECRUSHER_RST_SHIFT 10
#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
#define OMAP3430_ICEPICK_RST_SHIFT 9
#define OMAP3430_ICEPICK_RST_MASK (1 << 9)
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
#define OMAP3430_SECURE_WD_RST_SHIFT 5
#define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
#define OMAP3430_MPU_WD_RST_SHIFT 4
#define OMAP3430_MPU_WD_RST_MASK (1 << 4)
#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
/* PRM_VOLTCTRL */
#define OMAP3430_SEL_VMODE_MASK (1 << 4)
#define OMAP3430_SEL_OFF_MASK (1 << 3)
#define OMAP3430_AUTO_OFF_MASK (1 << 2)
#define OMAP3430_AUTO_RET_MASK (1 << 1)
#define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
/* PRM_SRAM_PCHARGE */
#define OMAP3430_PCHARGE_TIME_SHIFT 0
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
/* PRM_CLKSRC_CTRL */
#define OMAP3430_SYSCLKDIV_SHIFT 6
#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
#define OMAP3430_SYSCLKSEL_SHIFT 0
#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
/* PRM_VOLTSETUP1 */
#define OMAP3430_SETUP_TIME2_SHIFT 16
#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
#define OMAP3430_SETUP_TIME1_SHIFT 0
#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
/* PRM_VOLTOFFSET */
#define OMAP3430_OFFSET_TIME_SHIFT 0
#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
/* PRM_CLKSETUP */
#define OMAP3430_SETUP_TIME_SHIFT 0
#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
/* PRM_POLCTRL */
#define OMAP3430_OFFMODE_POL_MASK (1 << 3)
#define OMAP3430_CLKOUT_POL_MASK (1 << 2)
#define OMAP3430_CLKREQ_POL_MASK (1 << 1)
#define OMAP3430_EXTVOL_POL_MASK (1 << 0)
/* PRM_VOLTSETUP2 */
#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
/* PRM_VP1_CONFIG specific bits */
/* PRM_VP1_VSTEPMIN specific bits */
/* PRM_VP1_VSTEPMAX specific bits */
/* PRM_VP1_VLIMITTO specific bits */
/* PRM_VP1_VOLTAGE specific bits */
/* PRM_VP1_STATUS specific bits */
/* PRM_VP2_CONFIG specific bits */
/* PRM_VP2_VSTEPMIN specific bits */
/* PRM_VP2_VSTEPMAX specific bits */
/* PRM_VP2_VLIMITTO specific bits */
/* PRM_VP2_VOLTAGE specific bits */
/* PRM_VP2_STATUS specific bits */
/* RM_RSTST_NEON specific bits */
/* PM_WKDEP_NEON specific bits */
/* PM_PWSTCTRL_NEON specific bits */
/* PM_PWSTST_NEON specific bits */
/* PM_PREPWSTST_NEON specific bits */
#endif
arch/arm/mach-omap2/prm-regbits-44xx.h
View file @ 311b79bb
......@@ -22,2306 +22,80 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1)
/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8)
/* Used by PM_ABE_PWRSTST */
#define OMAP4430_AESSMEM_STATEST_SHIFT 4
#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_AIPOFF_SHIFT 8
#define OMAP4430_AIPOFF_MASK (1 << 8)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_RA_ERR_SHIFT 25
#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25)
/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_SA_ERR_SHIFT 24
#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24)
/* Used by PRM_VC_ERRST */
#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26
#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26)
/* Used by PRM_RSTST */
#define OMAP4430_C2C_RST_SHIFT 10
#define OMAP4430_C2C_RST_MASK (1 << 10)
/* Used by PM_CAM_PWRSTCTRL */
#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_CAM_PWRSTST */
#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4)
/* Used by PRM_CLKREQCTRL */
#define OMAP4430_CLKREQ_COND_SHIFT 0
#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
/* Used by PRM_VC_VAL_SMPS_RA_CMD */
#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
/* Used by PM_CORE_PWRSTST */
#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
/* Used by PM_CORE_PWRSTST */
#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
/* Used by REVISION_PRM */
#define OMAP4430_CUSTOM_SHIFT 6
#define OMAP4430_CUSTOM_MASK (0x3 << 6)
/* Used by PRM_VC_VAL_BYPASS */
#define OMAP4430_DATA_SHIFT 16
#define OMAP4430_DATA_MASK (0xff << 16)
/* Used by PRM_DEVICE_OFF_CTRL */
#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
/* Used by PRM_VC_CFG_I2C_MODE */
#define OMAP4430_DFILTEREN_SHIFT 6
#define OMAP4430_DFILTEREN_MASK (1 << 6)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
*/
#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
/* Used by PRM_IRQENABLE_MPU */
#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
/* Used by PRM_IRQSTATUS_MPU */
#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
/* Used by PRM_IRQENABLE_MPU */
#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
/* Used by PRM_IRQSTATUS_MPU */
#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
/* Used by PM_DSS_PWRSTCTRL */
#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_DSS_PWRSTCTRL */
#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
/* Used by PM_DSS_PWRSTST */
#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
/* Used by PM_CORE_PWRSTST */
#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
/* Used by PM_CORE_PWRSTST */
#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
/* Used by PRM_DEVICE_OFF_CTRL */
#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
/* Used by PRM_DEVICE_OFF_CTRL */
#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
/* Used by RM_MPU_RSTST */
#define OMAP4430_EMULATION_RST_SHIFT 0
#define OMAP4430_EMULATION_RST_MASK (1 << 0)
/* Used by RM_DUCATI_RSTST */
#define OMAP4430_EMULATION_RST1ST_SHIFT 3
#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
/* Used by RM_DUCATI_RSTST */
#define OMAP4430_EMULATION_RST2ST_SHIFT 4
#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
/* Used by RM_IVAHD_RSTST */
#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
/* Used by RM_IVAHD_RSTST */
#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
/* Used by PM_EMU_PWRSTCTRL */
#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
/* Used by PM_EMU_PWRSTST */
#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ENFUNC4_SHIFT 6
#define OMAP4430_ENFUNC4_MASK (1 << 6)
/*
* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
* PRM_LDO_SRAM_MPU_SETUP
*/
#define OMAP4430_ENFUNC5_SHIFT 7
#define OMAP4430_ENFUNC5_MASK (1 << 7)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_ERRORGAIN_SHIFT 16
#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_ERROROFFSET_SHIFT 24
#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
/* Used by PRM_RSTST */
#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_FORCEUPDATE_SHIFT 1
#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
#define OMAP4430_FORCEWKUP_EN_SHIFT 10
#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
#define OMAP4430_FORCEWKUP_ST_SHIFT 10
#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10)
/* Used by REVISION_PRM */
#define OMAP4430_FUNC_SHIFT 16
#define OMAP4430_FUNC_MASK (0xfff << 16)
/* Used by PM_GFX_PWRSTCTRL */
#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_GFX_PWRSTST */
#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4)
/* Used by PRM_RSTST */
#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_GLOBAL_WUEN_SHIFT 16
#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
/* Used by PRM_VC_CFG_I2C_MODE */
#define OMAP4430_HSMCODE_SHIFT 0
#define OMAP4430_HSMCODE_MASK (0x7 << 0)
/* Used by PRM_VC_CFG_I2C_MODE */
#define OMAP4430_HSMODEEN_SHIFT 3
#define OMAP4430_HSMODEEN_MASK (1 << 3)
/* Used by PRM_VC_CFG_I2C_CLK */
#define OMAP4430_HSSCLH_SHIFT 16
#define OMAP4430_HSSCLH_MASK (0xff << 16)
/* Used by PRM_VC_CFG_I2C_CLK */
#define OMAP4430_HSSCLL_SHIFT 24
#define OMAP4430_HSSCLL_MASK (0xff << 24)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8)
/* Used by PM_IVAHD_PWRSTST */
#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4)
/* Used by RM_MPU_RSTST */
#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1)
/* Used by RM_DUCATI_RSTST */
#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5)
/* Used by RM_DUCATI_RSTST */
#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6)
/* Used by RM_IVAHD_RSTST */
#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5)
/* Used by RM_IVAHD_RSTST */
#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6)
/* Used by PRM_RSTST */
#define OMAP4430_ICEPICK_RST_SHIFT 9
#define OMAP4430_ICEPICK_RST_MASK (1 << 9)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_INITVDD_SHIFT 2
#define OMAP4430_INITVDD_MASK (1 << 2)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_INITVOLTAGE_SHIFT 8
#define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
/*
* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
* PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
* PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
*/
#define OMAP4430_INTRANSITION_SHIFT 20
#define OMAP4430_INTRANSITION_MASK (1 << 20)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_IO_EN_SHIFT 9
#define OMAP4430_IO_EN_MASK (1 << 9)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_IO_ON_STATUS_SHIFT 5
#define OMAP4430_IO_ON_STATUS_MASK (1 << 5)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_IO_ST_SHIFT 9
#define OMAP4430_IO_ST_MASK (1 << 9)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_ISOCLK_STATUS_SHIFT 1
#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4)
/* Used by PRM_IO_COUNT */
#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0)
/* Used by PM_L3INIT_PWRSTCTRL */
#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
/* Used by PM_L3INIT_PWRSTCTRL */
#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
/* Used by PM_L3INIT_PWRSTST */
#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
/*
* Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
* PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
*/
#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
/*
* Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
* PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
*/
#define OMAP4430_LOGICRETSTATE_SHIFT 2
#define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
/*
* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
* PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
* PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
*/
#define OMAP4430_LOGICSTATEST_SHIFT 2
#define OMAP4430_LOGICSTATEST_MASK (1 << 2)
/*
* Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
* RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
* RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
* RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
* RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
* RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
* RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
* RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
* RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
* RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
* RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
* RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
* RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
* RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
* RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
* RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
* RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
* RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
* RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
* RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
* RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
* RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
* RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
* RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
* RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
* RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
* RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
* RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
* RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
* RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
* RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
* RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
* RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
* RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
*/
#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
/*
* Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
* RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
* RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
* RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
* RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
* RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
* RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
* RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
* RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
* RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
* RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
* RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
* RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
* RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
* RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
* RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
* RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
*/
#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1)
/* Used by RM_ABE_AESS_CONTEXT */
#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8)
/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9)
/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
/*
* Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
* RM_SDMA_SDMA_CONTEXT
*/
#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8)
/* Used by RM_DUCATI_DUCATI_CONTEXT */
#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9)
/* Used by RM_DUCATI_DUCATI_CONTEXT */
#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8)
/* Used by RM_EMU_DEBUGSS_CONTEXT */
#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8)
/* Used by RM_GFX_GFX_CONTEXT */
#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10)
/*
* Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
* RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
* RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
* RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
* RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
*/
#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
/* Used by RM_MPU_MPU_CONTEXT */
#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8)
/* Used by RM_MPU_MPU_CONTEXT */
#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9)
/* Used by RM_MPU_MPU_CONTEXT */
#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10)
/*
* Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
* RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
* RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
*/
#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
/*
* Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
* RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
*/
#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8)
/*
* Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
* RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
* RM_L4SEC_CRYPTODMA_CONTEXT
*/
#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
/* Used by RM_IVAHD_SL2_CONTEXT */
#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8)
/* Used by RM_IVAHD_IVAHD_CONTEXT */
#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9)
/* Used by RM_TESLA_TESLA_CONTEXT */
#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10)
/* Used by RM_TESLA_TESLA_CONTEXT */
#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8)
/* Used by RM_TESLA_TESLA_CONTEXT */
#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9)
/* Used by RM_WKUP_SARRAM_CONTEXT */
#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8)
/*
* Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
* PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
* PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
*/
#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
/* Used by PRM_MODEM_IF_CTRL */
#define OMAP4430_MODEM_READY_SHIFT 1
#define OMAP4430_MODEM_READY_MASK (1 << 1)
/* Used by PRM_MODEM_IF_CTRL */
#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
/* Used by PRM_MODEM_IF_CTRL */
#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
/* Used by PRM_MODEM_IF_CTRL */
#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
/* Used by PM_MPU_PWRSTST */
#define OMAP4430_MPU_L1_STATEST_SHIFT 4
#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
/* Used by PM_MPU_PWRSTST */
#define OMAP4430_MPU_L2_STATEST_SHIFT 6
#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
/* Used by PM_MPU_PWRSTCTRL */
#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
/* Used by PM_MPU_PWRSTST */
#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
/* Used by PRM_RSTST */
#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
/* Used by PRM_RSTST */
#define OMAP4430_MPU_WDT_RST_SHIFT 3
#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
/* Used by PM_L4PER_PWRSTCTRL */
#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
/* Used by PM_L4PER_PWRSTCTRL */
#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
/* Used by PM_L4PER_PWRSTST */
#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
/* Used by PM_CORE_PWRSTCTRL */
#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
/* Used by PM_CORE_PWRSTST */
#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
#define OMAP4430_OFF_SHIFT 0
#define OMAP4430_OFF_MASK (0xff << 0)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
#define OMAP4430_ON_SHIFT 24
#define OMAP4430_ON_MASK (0xff << 24)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
#define OMAP4430_ONLP_SHIFT 16
#define OMAP4430_ONLP_MASK (0xff << 16)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
#define OMAP4430_OPP_CHANGE_SHIFT 2
#define OMAP4430_OPP_CHANGE_MASK (1 << 2)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
#define OMAP4430_OPP_SEL_SHIFT 0
#define OMAP4430_OPP_SEL_MASK (0x3 << 0)
/* Used by PRM_SRAM_COUNT */
#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0)
/* Used by PRM_PSCON_COUNT */
#define OMAP4430_PCHARGE_TIME_SHIFT 0
#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0)
/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
/* Used by PM_ABE_PWRSTCTRL */
#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10)
/* Used by PM_ABE_PWRSTST */
#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8)
/* Used by PRM_PHASE1_CNDP */
#define OMAP4430_PHASE1_CNDP_SHIFT 0
#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0)
/* Used by PRM_PHASE2A_CNDP */
#define OMAP4430_PHASE2A_CNDP_SHIFT 0
#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0)
/* Used by PRM_PHASE2B_CNDP */
#define OMAP4430_PHASE2B_CNDP_SHIFT 0
#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0)
/* Used by PRM_PSCON_COUNT */
#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
/*
* Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
* PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
* PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
*/
#define OMAP4430_POWERSTATE_SHIFT 0
#define OMAP4430_POWERSTATE_MASK (0x3 << 0)
/*
* Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
* PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
* PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
*/
#define OMAP4430_POWERSTATEST_SHIFT 0
#define OMAP4430_POWERSTATEST_MASK (0x3 << 0)
/* Used by PRM_PWRREQCTRL */
#define OMAP4430_PWRREQ_COND_SHIFT 0
#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19)
/*
* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16)
/*
* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
/*
* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0)
/*
* Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
* PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
* PRM_VOLTSETUP_MPU_RET_SLEEP
*/
#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18)
/* Used by PRM_VC_VAL_BYPASS */
#define OMAP4430_REGADDR_SHIFT 8
#define OMAP4430_REGADDR_MASK (0xff << 8)
/*
* Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
* PRM_VC_VAL_CMD_VDD_MPU_L
*/
#define OMAP4430_RET_SHIFT 8
#define OMAP4430_RET_MASK (0xff << 8)
/* Used by PM_L4PER_PWRSTCTRL */
#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
/* Used by PM_L4PER_PWRSTCTRL */
#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8)
/* Used by PM_L4PER_PWRSTST */
#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
#define OMAP4430_RETMODE_ENABLE_SHIFT 0
#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0)
/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
#define OMAP4430_RST1_SHIFT 0
#define OMAP4430_RST1_MASK (1 << 0)
/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
#define OMAP4430_RST1ST_SHIFT 0
#define OMAP4430_RST1ST_MASK (1 << 0)
/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
#define OMAP4430_RST2_SHIFT 1
#define OMAP4430_RST2_MASK (1 << 1)
/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
#define OMAP4430_RST2ST_SHIFT 1
#define OMAP4430_RST2ST_MASK (1 << 1)
/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
#define OMAP4430_RST3_SHIFT 2
#define OMAP4430_RST3_MASK (1 << 2)
/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
#define OMAP4430_RST3ST_SHIFT 2
#define OMAP4430_RST3ST_MASK (1 << 2)
/* Used by PRM_RSTTIME */
#define OMAP4430_RSTTIME1_SHIFT 0
#define OMAP4430_RSTTIME1_MASK (0x3ff << 0)
/* Used by PRM_RSTTIME */
#define OMAP4430_RSTTIME2_SHIFT 10
#define OMAP4430_RSTTIME2_MASK (0x1f << 10)
/* Used by PRM_RSTCTRL */
#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1)
/* Used by PRM_RSTCTRL */
#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
/* Used by REVISION_PRM */
#define OMAP4430_R_RTL_SHIFT 11
#define OMAP4430_R_RTL_MASK (0x1f << 11)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0)
/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8)
/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
/* Used by PRM_VC_CFG_CHANNEL */
#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16)
/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
/* Used by REVISION_PRM */
#define OMAP4430_SCHEME_SHIFT 30
#define OMAP4430_SCHEME_MASK (0x3 << 30)
/* Used by PRM_VC_CFG_I2C_CLK */
#define OMAP4430_SCLH_SHIFT 0
#define OMAP4430_SCLH_MASK (0xff << 0)
/* Used by PRM_VC_CFG_I2C_CLK */
#define OMAP4430_SCLL_SHIFT 8
#define OMAP4430_SCLL_MASK (0xff << 8)
/* Used by PRM_RSTST */
#define OMAP4430_SECURE_WDT_RST_SHIFT 4
#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9)
/* Used by PM_IVAHD_PWRSTST */
#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6)
/* Used by PRM_VC_VAL_BYPASS */
#define OMAP4430_SLAVEADDR_SHIFT 0
#define OMAP4430_SLAVEADDR_MASK (0x7f << 0)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3)
/* Used by PRM_SRAM_COUNT */
#define OMAP4430_SLPCNT_VALUE_SHIFT 16
#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16)
/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1
#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9
#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17
#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0
#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8
#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16
#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10
#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10)
/* Used by PRM_VC_ERRST */
#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18
#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_SR2EN_SHIFT 0
#define OMAP4430_SR2EN_MASK (1 << 0)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6)
/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
#define OMAP4430_SR2_STATUS_SHIFT 3
#define OMAP4430_SR2_STATUS_MASK (0x3 << 3)
/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8)
/*
* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
* PRM_LDO_SRAM_MPU_CTRL
*/
#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9)
/* Used by PRM_VC_CFG_I2C_MODE */
#define OMAP4430_SRMODEEN_SHIFT 4
#define OMAP4430_SRMODEEN_MASK (1 << 4)
/* Used by PRM_VOLTSETUP_WARMRESET */
#define OMAP4430_STABLE_COUNT_SHIFT 0
#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0)
/* Used by PRM_VOLTSETUP_WARMRESET */
#define OMAP4430_STABLE_PRESCAL_SHIFT 8
#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8)
/* Used by PRM_LDO_BANDGAP_SETUP */
#define OMAP4430_STARTUP_COUNT_SHIFT 0
#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0)
/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24
#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10)
/* Used by PM_IVAHD_PWRSTST */
#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
/* Used by PM_IVAHD_PWRSTCTRL */
#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11)
/* Used by PM_IVAHD_PWRSTST */
#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10)
/* Used by RM_TESLA_RSTST */
#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2)
/* Used by RM_TESLA_RSTST */
#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10)
/* Used by PM_TESLA_PWRSTST */
#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8)
/* Used by PM_TESLA_PWRSTST */
#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18)
/* Used by PM_TESLA_PWRSTCTRL */
#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9)
/* Used by PM_TESLA_PWRSTST */
#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
#define OMAP4430_TIMEOUT_SHIFT 0
#define OMAP4430_TIMEOUT_MASK (0xffff << 0)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_TIMEOUTEN_SHIFT 3
#define OMAP4430_TIMEOUTEN_MASK (1 << 3)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_TRANSITION_EN_SHIFT 8
#define OMAP4430_TRANSITION_EN_MASK (1 << 8)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_TRANSITION_ST_SHIFT 8
#define OMAP4430_TRANSITION_ST_MASK (1 << 8)
/* Used by PRM_VC_VAL_BYPASS */
#define OMAP4430_VALID_SHIFT 24
#define OMAP4430_VALID_MASK (1 << 24)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22
#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22
#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_RAERR_EN_SHIFT 12
#define OMAP4430_VC_RAERR_EN_MASK (1 << 12)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_RAERR_ST_SHIFT 12
#define OMAP4430_VC_RAERR_ST_MASK (1 << 12)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_SAERR_EN_SHIFT 11
#define OMAP4430_VC_SAERR_EN_MASK (1 << 11)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_SAERR_ST_SHIFT 11
#define OMAP4430_VC_SAERR_ST_MASK (1 << 11)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VC_TOERR_EN_SHIFT 13
#define OMAP4430_VC_TOERR_EN_MASK (1 << 13)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VC_TOERR_ST_SHIFT 13
#define OMAP4430_VC_TOERR_ST_MASK (1 << 13)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
#define OMAP4430_VDDMAX_SHIFT 24
#define OMAP4430_VDDMAX_MASK (0xff << 24)
/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
#define OMAP4430_VDDMIN_SHIFT 16
#define OMAP4430_VDDMIN_MASK (0xff << 16)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
/* Used by PRM_RSTST */
#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9)
/* Used by PRM_RSTST */
#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
/* Used by PRM_VOLTCTRL */
#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8)
/* Used by PRM_RSTST */
#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4
#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12
#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20
#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3
#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11
#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19
#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13
#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13)
/* Used by PRM_VC_ERRST */
#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21
#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
/* Used by PRM_VC_VAL_SMPS_RA_VOL */
#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
#define OMAP4430_VPENABLE_SHIFT 0
#define OMAP4430_VPENABLE_MASK (1 << 0)
/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
#define OMAP4430_VPINIDLE_SHIFT 0
#define OMAP4430_VPINIDLE_MASK (1 << 0)
/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
#define OMAP4430_VPVOLTAGE_SHIFT 0
#define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24)
/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29)
/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
/* Used by PRM_IRQENABLE_MPU_2 */
#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
/* Used by PRM_IRQSTATUS_MPU_2 */
#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
/* Used by PRM_SRAM_COUNT */
#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8)
/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
#define OMAP4430_VSTEPMAX_SHIFT 0
#define OMAP4430_VSTEPMAX_MASK (0xff << 0)
/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
#define OMAP4430_VSTEPMIN_SHIFT 0
#define OMAP4430_VSTEPMIN_MASK (0xff << 0)
/* Used by PRM_MODEM_IF_CTRL */
#define OMAP4430_WAKE_MODEM_SHIFT 0
#define OMAP4430_WAKE_MODEM_MASK (1 << 0)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2)
/* Used by PM_ABE_DMIC_WKDEP */
#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
/* Used by PM_ABE_DMIC_WKDEP */
#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6)
/* Used by PM_ABE_DMIC_WKDEP */
#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
/* Used by PM_ABE_DMIC_WKDEP */
#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_DMTIMER10_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0)
/* Used by PM_L4PER_DMTIMER11_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_DMTIMER11_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0)
/* Used by PM_L4PER_DMTIMER2_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0)
/* Used by PM_L4PER_DMTIMER3_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_DMTIMER3_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0)
/* Used by PM_L4PER_DMTIMER4_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_DMTIMER4_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0)
/* Used by PM_L4PER_DMTIMER9_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_DMTIMER9_WKDEP */
#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10)
/* Used by PM_WKUP_GPIO1_WKDEP */
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1)
/* Used by PM_WKUP_GPIO1_WKDEP */
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_WKUP_GPIO1_WKDEP */
#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_GPIO2_WKDEP */
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_GPIO2_WKDEP */
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_GPIO2_WKDEP */
#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_GPIO3_WKDEP */
#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_GPIO3_WKDEP */
#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_GPIO4_WKDEP */
#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_GPIO4_WKDEP */
#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_GPIO5_WKDEP */
#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_GPIO5_WKDEP */
#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_GPIO6_WKDEP */
#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_GPIO6_WKDEP */
#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
/* Used by PM_DSS_DSS_WKDEP */
#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14)
/* Used by PM_L4PER_HECC1_WKDEP */
#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_HECC2_WKDEP */
#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_HSI_WKDEP */
#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6)
/* Used by PM_L3INIT_HSI_WKDEP */
#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_HSI_WKDEP */
#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
/* Used by PM_L4PER_I2C1_WKDEP */
#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_I2C1_WKDEP */
#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_I2C1_WKDEP */
#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_I2C2_WKDEP */
#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_I2C2_WKDEP */
#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_I2C2_WKDEP */
#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_I2C3_WKDEP */
#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_I2C3_WKDEP */
#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_I2C3_WKDEP */
#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_I2C4_WKDEP */
#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_I2C4_WKDEP */
#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_I2C4_WKDEP */
#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_I2C5_WKDEP */
#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_I2C5_WKDEP */
#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
/* Used by PM_WKUP_KEYBOARD_WKDEP */
#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0)
/* Used by PM_ABE_MCASP_WKDEP */
#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7)
/* Used by PM_ABE_MCASP_WKDEP */
#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6)
/* Used by PM_ABE_MCASP_WKDEP */
#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
/* Used by PM_ABE_MCASP_WKDEP */
#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MCASP2_WKDEP */
#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_MCASP2_WKDEP */
#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_MCASP2_WKDEP */
#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCASP2_WKDEP */
#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MCASP3_WKDEP */
#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_MCASP3_WKDEP */
#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_MCASP3_WKDEP */
#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCASP3_WKDEP */
#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_ABE_MCBSP1_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
/* Used by PM_ABE_MCBSP1_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
/* Used by PM_ABE_MCBSP1_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2)
/* Used by PM_ABE_MCBSP2_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
/* Used by PM_ABE_MCBSP2_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
/* Used by PM_ABE_MCBSP2_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2)
/* Used by PM_ABE_MCBSP3_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
/* Used by PM_ABE_MCBSP3_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
/* Used by PM_ABE_MCBSP3_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MCBSP4_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCBSP4_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MCBSP4_WKDEP */
#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MCSPI1_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_MCSPI1_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCSPI1_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MCSPI1_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MCSPI2_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_MCSPI2_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCSPI2_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MCSPI3_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCSPI3_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MCSPI4_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MCSPI4_WKDEP */
#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
/* Used by PM_L3INIT_MMC1_WKDEP */
#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_MMC1_WKDEP */
#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_MMC1_WKDEP */
#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
/* Used by PM_L3INIT_MMC1_WKDEP */
#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2)
/* Used by PM_L3INIT_MMC2_WKDEP */
#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_MMC2_WKDEP */
#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_MMC2_WKDEP */
#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
/* Used by PM_L3INIT_MMC2_WKDEP */
#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2)
/* Used by PM_L3INIT_MMC6_WKDEP */
#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_MMC6_WKDEP */
#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_MMC6_WKDEP */
#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_MMCSD3_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_MMCSD3_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MMCSD3_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MMCSD4_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_MMCSD4_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MMCSD4_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_MMCSD5_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_MMCSD5_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0)
/* Used by PM_L4PER_MMCSD5_WKDEP */
#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3)
/* Used by PM_L3INIT_PCIESS_WKDEP */
#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_PCIESS_WKDEP */
#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2)
/* Used by PM_ABE_PDM_WKDEP */
#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7)
/* Used by PM_ABE_PDM_WKDEP */
#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6)
/* Used by PM_ABE_PDM_WKDEP */
#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0)
/* Used by PM_ABE_PDM_WKDEP */
#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_WKUP_RTC_WKDEP */
#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_SATA_WKDEP */
#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_SATA_WKDEP */
#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2)
/* Used by PM_ABE_SLIMBUS_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
/* Used by PM_ABE_SLIMBUS_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6)
/* Used by PM_ABE_SLIMBUS_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
/* Used by PM_ABE_SLIMBUS_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0)
/* Used by PM_L4PER_SLIMBUS2_WKDEP */
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2)
/* Used by PM_ALWON_SR_CORE_WKDEP */
#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1)
/* Used by PM_ALWON_SR_CORE_WKDEP */
#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0)
/* Used by PM_ALWON_SR_IVA_WKDEP */
#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1)
/* Used by PM_ALWON_SR_IVA_WKDEP */
#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0)
/* Used by PM_ALWON_SR_MPU_WKDEP */
#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0)
/* Used by PM_WKUP_TIMER12_WKDEP */
#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
/* Used by PM_WKUP_TIMER1_WKDEP */
#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
/* Used by PM_ABE_TIMER5_WKDEP */
#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
/* Used by PM_ABE_TIMER5_WKDEP */
#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2)
/* Used by PM_ABE_TIMER6_WKDEP */
#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
/* Used by PM_ABE_TIMER6_WKDEP */
#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2)
/* Used by PM_ABE_TIMER7_WKDEP */
#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
/* Used by PM_ABE_TIMER7_WKDEP */
#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2)
/* Used by PM_ABE_TIMER8_WKDEP */
#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
/* Used by PM_ABE_TIMER8_WKDEP */
#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_UART1_WKDEP */
#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0)
/* Used by PM_L4PER_UART1_WKDEP */
#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_UART2_WKDEP */
#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0)
/* Used by PM_L4PER_UART2_WKDEP */
#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_UART3_WKDEP */
#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1)
/* Used by PM_L4PER_UART3_WKDEP */
#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0)
/* Used by PM_L4PER_UART3_WKDEP */
#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3)
/* Used by PM_L4PER_UART3_WKDEP */
#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2)
/* Used by PM_L4PER_UART4_WKDEP */
#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0)
/* Used by PM_L4PER_UART4_WKDEP */
#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3)
/* Used by PM_L3INIT_UNIPRO1_WKDEP */
#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_UNIPRO1_WKDEP */
#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_USB_HOST_WKDEP */
#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_USB_HOST_WKDEP */
#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_USB_OTG_WKDEP */
#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_USB_OTG_WKDEP */
#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_USB_TLL_WKDEP */
#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1)
/* Used by PM_L3INIT_USB_TLL_WKDEP */
#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0)
/* Used by PM_WKUP_USIM_WKDEP */
#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0)
/* Used by PM_WKUP_USIM_WKDEP */
#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3)
/* Used by PM_WKUP_WDT2_WKDEP */
#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1)
/* Used by PM_WKUP_WDT2_WKDEP */
#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0)
/* Used by PM_ABE_WDT3_WKDEP */
#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0)
/* Used by PM_L3INIT_HSI_WKDEP */
#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8)
/* Used by PM_L3INIT_XHPI_WKDEP */
#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_WUCLK_CTRL_SHIFT 8
#define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
/* Used by PRM_IO_PMCTRL */
#define OMAP4430_WUCLK_STATUS_SHIFT 9
#define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
/* Used by REVISION_PRM */
#define OMAP4430_X_MAJOR_SHIFT 8
#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
/* Used by REVISION_PRM */
#define OMAP4430_Y_MINOR_SHIFT 0
#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
#endif
arch/arm/mach-omap2/prm-regbits-54xx.h deleted 100644 → 0
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