Skip to content

L
linux
Commit 315a6998 authored by Anton Blanchard's avatar Anton Blanchard Committed by Linus Torvalds
Browse files
Options

[PATCH] ppc64: use c99 initialisers in cputable code 

Use c99 initialisers in the cputable code.
Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 2098eec2
Hide whitespace changes
Inline Side-by-side
Showing with 212 additions and 153 deletions
arch/ppc64/kernel/cputable.c
View file @ 315a6998
...@@ -49,160 +49,219 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec); ...@@ -49,160 +49,219 @@ extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
#endif #endif
struct cpu_spec cpu_specs[] = { struct cpu_spec cpu_specs[] = {
{ /* Power3 */ { /* Power3 */
0xffff0000, 0x00400000, "POWER3 (630)", .pvr_mask = 0xffff0000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_value = 0x00400000,
CPU_FTR_IABR | CPU_FTR_PMC8, .cpu_name = "POWER3 (630)",
COMMON_USER_PPC64, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
128, 128, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
__setup_cpu_power3, CPU_FTR_PMC8,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64,
}, .icache_bsize = 128,
{ /* Power3+ */ .dcache_bsize = 128,
0xffff0000, 0x00410000, "POWER3 (630+)", .cpu_setup = __setup_cpu_power3,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .firmware_features = COMMON_PPC64_FW,
CPU_FTR_IABR | CPU_FTR_PMC8, },
COMMON_USER_PPC64, { /* Power3+ */
128, 128, .pvr_mask = 0xffff0000,
__setup_cpu_power3, .pvr_value = 0x00410000,
COMMON_PPC64_FW .cpu_name = "POWER3 (630+)",
}, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
{ /* Northstar */ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
0xffff0000, 0x00330000, "RS64-II (northstar)", CPU_FTR_PMC8,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_user_features = COMMON_USER_PPC64,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .icache_bsize = 128,
COMMON_USER_PPC64, .dcache_bsize = 128,
128, 128, .cpu_setup = __setup_cpu_power3,
__setup_cpu_power3, .firmware_features = COMMON_PPC64_FW,
COMMON_PPC64_FW },
}, { /* Northstar */
{ /* Pulsar */ .pvr_mask = 0xffff0000,
0xffff0000, 0x00340000, "RS64-III (pulsar)", .pvr_value = 0x00330000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_name = "RS64-II (northstar)",
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
COMMON_USER_PPC64, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
128, 128, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
__setup_cpu_power3, .cpu_user_features = COMMON_USER_PPC64,
COMMON_PPC64_FW .icache_bsize = 128,
}, .dcache_bsize = 128,
{ /* I-star */ .cpu_setup = __setup_cpu_power3,
0xffff0000, 0x00360000, "RS64-III (icestar)", .firmware_features = COMMON_PPC64_FW,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | },
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, { /* Pulsar */
COMMON_USER_PPC64, .pvr_mask = 0xffff0000,
128, 128, .pvr_value = 0x00340000,
__setup_cpu_power3, .cpu_name = "RS64-III (pulsar)",
COMMON_PPC64_FW .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
}, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
{ /* S-star */ CPU_FTR_PMC8 | CPU_FTR_MMCRA,
0xffff0000, 0x00370000, "RS64-IV (sstar)", .cpu_user_features = COMMON_USER_PPC64,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .icache_bsize = 128,
CPU_FTR_IABR | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .dcache_bsize = 128,
COMMON_USER_PPC64, .cpu_setup = __setup_cpu_power3,
128, 128, .firmware_features = COMMON_PPC64_FW,
__setup_cpu_power3, },
COMMON_PPC64_FW { /* I-star */
}, .pvr_mask = 0xffff0000,
{ /* Power4 */ .pvr_value = 0x00360000,
0xffff0000, 0x00350000, "POWER4 (gp)", .cpu_name = "RS64-III (icestar)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
COMMON_USER_PPC64, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
128, 128, .cpu_user_features = COMMON_USER_PPC64,
__setup_cpu_power4, .icache_bsize = 128,
COMMON_PPC64_FW .dcache_bsize = 128,
}, .cpu_setup = __setup_cpu_power3,
{ /* Power4+ */ .firmware_features = COMMON_PPC64_FW,
0xffff0000, 0x00380000, "POWER4+ (gq)", },
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | { /* S-star */
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .pvr_mask = 0xffff0000,
COMMON_USER_PPC64, .pvr_value = 0x00370000,
128, 128, .cpu_name = "RS64-IV (sstar)",
__setup_cpu_power4, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
COMMON_PPC64_FW CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
}, CPU_FTR_PMC8 | CPU_FTR_MMCRA,
{ /* PPC970 */ .cpu_user_features = COMMON_USER_PPC64,
0xffff0000, 0x00390000, "PPC970", .icache_bsize = 128,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .dcache_bsize = 128,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | .cpu_setup = __setup_cpu_power3,
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .firmware_features = COMMON_PPC64_FW,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, },
128, 128, { /* Power4 */
__setup_cpu_ppc970, .pvr_mask = 0xffff0000,
COMMON_PPC64_FW .pvr_value = 0x00350000,
}, .cpu_name = "POWER4 (gp)",
{ /* PPC970FX */ .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
0xffff0000, 0x003c0000, "PPC970FX", CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | .cpu_user_features = COMMON_USER_PPC64,
CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA, .icache_bsize = 128,
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, .dcache_bsize = 128,
128, 128, .cpu_setup = __setup_cpu_power4,
__setup_cpu_ppc970, .firmware_features = COMMON_PPC64_FW,
COMMON_PPC64_FW },
}, { /* Power4+ */
{ /* Power5 */ .pvr_mask = 0xffff0000,
0xffff0000, 0x003a0000, "POWER5 (gr)", .pvr_value = 0x00380000,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_name = "POWER4+ (gq)",
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT | .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_MMCRA_SIHV, CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_USER_PPC64, .cpu_user_features = COMMON_USER_PPC64,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_power4,
}, .firmware_features = COMMON_PPC64_FW,
{ /* Power5 */ },
0xffff0000, 0x003b0000, "POWER5 (gs)", { /* PPC970 */
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .pvr_mask = 0xffff0000,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT | .pvr_value = 0x00390000,
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | .cpu_name = "PPC970",
CPU_FTR_MMCRA_SIHV, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
COMMON_USER_PPC64, CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
128, 128, CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
__setup_cpu_power4, CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
COMMON_PPC64_FW .cpu_user_features = COMMON_USER_PPC64 |
}, PPC_FEATURE_HAS_ALTIVEC_COMP,
{ /* BE DD1.x */ .icache_bsize = 128,
0xffff0000, 0x00700000, "Broadband Engine", .dcache_bsize = 128,
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | .cpu_setup = __setup_cpu_ppc970,
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | .firmware_features = COMMON_PPC64_FW,
CPU_FTR_SMT, },
COMMON_USER_PPC64 | PPC_FEATURE_HAS_ALTIVEC_COMP, { /* PPC970FX */
128, 128, .pvr_mask = 0xffff0000,
__setup_cpu_be, .pvr_value = 0x003c0000,
COMMON_PPC64_FW .cpu_name = "PPC970FX",
}, .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
{ /* default match */ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
0x00000000, 0x00000000, "POWER4 (compatible)", CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
CPU_FTR_PPCAS_ARCH_V2, .cpu_user_features = COMMON_USER_PPC64 |
COMMON_USER_PPC64, PPC_FEATURE_HAS_ALTIVEC_COMP,
128, 128, .icache_bsize = 128,
__setup_cpu_power4, .dcache_bsize = 128,
COMMON_PPC64_FW .cpu_setup = __setup_cpu_ppc970,
} .firmware_features = COMMON_PPC64_FW,
},
{ /* Power5 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003a0000,
.cpu_name = "POWER5 (gr)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
CPU_FTR_MMCRA_SIHV,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
},
{ /* Power5 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003b0000,
.cpu_name = "POWER5 (gs)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
CPU_FTR_MMCRA_SIHV,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
},
{ /* BE DD1.x */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
.cpu_name = "Broadband Engine",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_SMT,
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_be,
.firmware_features = COMMON_PPC64_FW,
},
{ /* default match */
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
.cpu_name = "POWER4 (compatible)",
.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2,
.cpu_user_features = COMMON_USER_PPC64,
.icache_bsize = 128,
.dcache_bsize = 128,
.cpu_setup = __setup_cpu_power4,
.firmware_features = COMMON_PPC64_FW,
}
}; };
firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = { firmware_feature_t firmware_features_table[FIRMWARE_MAX_FEATURES] = {
{FW_FEATURE_PFT, "hcall-pft"}, {FW_FEATURE_PFT, "hcall-pft"},
{FW_FEATURE_TCE, "hcall-tce"}, {FW_FEATURE_TCE, "hcall-tce"},
{FW_FEATURE_SPRG0, "hcall-sprg0"}, {FW_FEATURE_SPRG0, "hcall-sprg0"},
{FW_FEATURE_DABR, "hcall-dabr"}, {FW_FEATURE_DABR, "hcall-dabr"},
{FW_FEATURE_COPY, "hcall-copy"}, {FW_FEATURE_COPY, "hcall-copy"},
{FW_FEATURE_ASR, "hcall-asr"}, {FW_FEATURE_ASR, "hcall-asr"},
{FW_FEATURE_DEBUG, "hcall-debug"}, {FW_FEATURE_DEBUG, "hcall-debug"},
{FW_FEATURE_PERF, "hcall-perf"}, {FW_FEATURE_PERF, "hcall-perf"},
{FW_FEATURE_DUMP, "hcall-dump"}, {FW_FEATURE_DUMP, "hcall-dump"},
{FW_FEATURE_INTERRUPT, "hcall-interrupt"}, {FW_FEATURE_INTERRUPT, "hcall-interrupt"},
{FW_FEATURE_MIGRATE, "hcall-migrate"}, {FW_FEATURE_MIGRATE, "hcall-migrate"},
{FW_FEATURE_PERFMON, "hcall-perfmon"}, {FW_FEATURE_PERFMON, "hcall-perfmon"},
{FW_FEATURE_CRQ, "hcall-crq"}, {FW_FEATURE_CRQ, "hcall-crq"},
{FW_FEATURE_VIO, "hcall-vio"}, {FW_FEATURE_VIO, "hcall-vio"},
{FW_FEATURE_RDMA, "hcall-rdma"}, {FW_FEATURE_RDMA, "hcall-rdma"},
{FW_FEATURE_LLAN, "hcall-lLAN"}, {FW_FEATURE_LLAN, "hcall-lLAN"},
{FW_FEATURE_BULK, "hcall-bulk"}, {FW_FEATURE_BULK, "hcall-bulk"},
{FW_FEATURE_XDABR, "hcall-xdabr"}, {FW_FEATURE_XDABR, "hcall-xdabr"},
{FW_FEATURE_MULTITCE, "hcall-multi-tce"}, {FW_FEATURE_MULTITCE, "hcall-multi-tce"},
{FW_FEATURE_SPLPAR, "hcall-splpar"}, {FW_FEATURE_SPLPAR, "hcall-splpar"},
}; };
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7