Commit 31c6e53a authored by Charles Keepax's avatar Charles Keepax Committed by Mark Brown

ASoC: cs42l43: Use fls to calculate the pre-divider for the PLL

Use fls to calculate the pre-divider and input frequency for the PLL,
this is marginally faster than the previous loop.
Suggested-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://msgid.link/r/20240125103117.2622095-7-ckeepax@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent fe04d163
...@@ -1338,10 +1338,9 @@ static int cs42l43_enable_pll(struct cs42l43_codec *priv) ...@@ -1338,10 +1338,9 @@ static int cs42l43_enable_pll(struct cs42l43_codec *priv)
dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq); dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) { div = fls(freq) -
div++; fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
freq /= 2; freq >>= div;
}
if (div <= CS42L43_PLL_REFCLK_DIV_MASK) { if (div <= CS42L43_PLL_REFCLK_DIV_MASK) {
int i; int i;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment