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Commit 344c2e5a authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/kms/nv50-: use NVIDIA's headers for core or_ctrl() 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 8e650ecb
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Showing with 785 additions and 42 deletions
drivers/gpu/drm/nouveau/dispnv50/dac507d.c
View file @ 344c2e5a
...@@ -23,6 +23,8 @@ ...@@ -23,6 +23,8 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl507d.h>
static int static int
dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
struct nv50_head_atom *asyh) struct nv50_head_atom *asyh)
...@@ -32,15 +34,15 @@ dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -32,15 +34,15 @@ dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
int ret; int ret;
if (asyh) { if (asyh) {
sync |= asyh->or.nvsync << 1; sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync);
sync |= asyh->or.nhsync; sync |= NVVAL(NV507D, DAC_SET_POLARITY, VSYNC, asyh->or.nvsync);
} }
if ((ret = PUSH_WAIT(push, 3))) if ((ret = PUSH_WAIT(push, 3)))
return ret; return ret;
PUSH_NVSQ(push, NV507D, 0x0400 + (or * 0x080), ctrl, PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl,
0x0404 + (or * 0x080), sync); DAC_SET_POLARITY(or), sync);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/dispnv50/dac907d.c
View file @ 344c2e5a
...@@ -23,6 +23,8 @@ ...@@ -23,6 +23,8 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl907d.h>
static int static int
dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl,
struct nv50_head_atom *asyh) struct nv50_head_atom *asyh)
...@@ -33,7 +35,7 @@ dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -33,7 +35,7 @@ dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl,
if ((ret = PUSH_WAIT(push, 2))) if ((ret = PUSH_WAIT(push, 2)))
return ret; return ret;
PUSH_NVSQ(push, NV907D, 0x0180 + (or * 0x020), ctrl); PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/dispnv50/disp.c
View file @ 344c2e5a
...@@ -51,6 +51,11 @@ ...@@ -51,6 +51,11 @@
#include <nvif/timer.h> #include <nvif/timer.h>
#include <nvhw/class/cl507c.h> #include <nvhw/class/cl507c.h>
#include <nvhw/class/cl507d.h>
#include <nvhw/class/cl837d.h>
#include <nvhw/class/cl887d.h>
#include <nvhw/class/cl907d.h>
#include <nvhw/class/cl917d.h>
#include "nouveau_drv.h" #include "nouveau_drv.h"
#include "nouveau_dma.h" #include "nouveau_dma.h"
...@@ -414,8 +419,9 @@ nv50_dac_disable(struct drm_encoder *encoder) ...@@ -414,8 +419,9 @@ nv50_dac_disable(struct drm_encoder *encoder)
{ {
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nv50_core *core = nv50_disp(encoder->dev)->core; struct nv50_core *core = nv50_disp(encoder->dev)->core;
const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
if (nv_encoder->crtc) if (nv_encoder->crtc)
core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
nv_encoder->crtc = NULL; nv_encoder->crtc = NULL;
nv50_outp_release(nv_encoder); nv50_outp_release(nv_encoder);
} }
...@@ -427,10 +433,23 @@ nv50_dac_enable(struct drm_encoder *encoder) ...@@ -427,10 +433,23 @@ nv50_dac_enable(struct drm_encoder *encoder)
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
struct nv50_core *core = nv50_disp(encoder->dev)->core; struct nv50_core *core = nv50_disp(encoder->dev)->core;
u32 ctrl = 0;
switch (nv_crtc->index) {
case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
default:
WARN_ON(1);
break;
}
ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
nv50_outp_acquire(nv_encoder, false); nv50_outp_acquire(nv_encoder, false);
core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
asyh->or.depth = 0; asyh->or.depth = 0;
nv_encoder->crtc = encoder->crtc; nv_encoder->crtc = encoder->crtc;
...@@ -980,10 +999,10 @@ static u8 ...@@ -980,10 +999,10 @@ static u8
nv50_dp_bpc_to_depth(unsigned int bpc) nv50_dp_bpc_to_depth(unsigned int bpc)
{ {
switch (bpc) { switch (bpc) {
case 6: return 0x2; case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
case 8: return 0x5; case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
case 10: case 10:
default: return 0x6; default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
} }
} }
...@@ -1022,9 +1041,9 @@ nv50_msto_enable(struct drm_encoder *encoder) ...@@ -1022,9 +1041,9 @@ nv50_msto_enable(struct drm_encoder *encoder)
nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
if (mstm->outp->link & 1) if (mstm->outp->link & 1)
proto = 0x8; proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
else else
proto = 0x9; proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
mstm->outp->update(mstm->outp, head->base.index, armh, proto, mstm->outp->update(mstm->outp, head->base.index, armh, proto,
nv50_dp_bpc_to_depth(armh->or.bpc)); nv50_dp_bpc_to_depth(armh->or.bpc));
...@@ -1553,10 +1572,10 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, ...@@ -1553,10 +1572,10 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
if (!asyh) { if (!asyh) {
nv_encoder->ctrl &= ~BIT(head); nv_encoder->ctrl &= ~BIT(head);
if (!(nv_encoder->ctrl & 0x0000000f)) if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
nv_encoder->ctrl = 0; nv_encoder->ctrl = 0;
} else { } else {
nv_encoder->ctrl |= proto << 8; nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
nv_encoder->ctrl |= BIT(head); nv_encoder->ctrl |= BIT(head);
asyh->or.depth = depth; asyh->or.depth = depth;
} }
...@@ -1614,8 +1633,8 @@ nv50_sor_enable(struct drm_encoder *encoder) ...@@ -1614,8 +1633,8 @@ nv50_sor_enable(struct drm_encoder *encoder)
struct nouveau_connector *nv_connector; struct nouveau_connector *nv_connector;
struct nvbios *bios = &drm->vbios; struct nvbios *bios = &drm->vbios;
bool hda = false; bool hda = false;
u8 proto = 0xf; u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
u8 depth = 0x0; u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
nv_connector = nouveau_encoder_connector_get(nv_encoder); nv_connector = nouveau_encoder_connector_get(nv_encoder);
nv_encoder->crtc = encoder->crtc; nv_encoder->crtc = encoder->crtc;
...@@ -1629,7 +1648,7 @@ nv50_sor_enable(struct drm_encoder *encoder) ...@@ -1629,7 +1648,7 @@ nv50_sor_enable(struct drm_encoder *encoder)
switch (nv_encoder->dcb->type) { switch (nv_encoder->dcb->type) {
case DCB_OUTPUT_TMDS: case DCB_OUTPUT_TMDS:
if (nv_encoder->link & 1) { if (nv_encoder->link & 1) {
proto = 0x1; proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
/* Only enable dual-link if: /* Only enable dual-link if:
* - Need to (i.e. rate > 165MHz) * - Need to (i.e. rate > 165MHz)
* - DCB says we can * - DCB says we can
...@@ -1639,15 +1658,15 @@ nv50_sor_enable(struct drm_encoder *encoder) ...@@ -1639,15 +1658,15 @@ nv50_sor_enable(struct drm_encoder *encoder)
if (mode->clock >= 165000 && if (mode->clock >= 165000 &&
nv_encoder->dcb->duallink_possible && nv_encoder->dcb->duallink_possible &&
!drm_detect_hdmi_monitor(nv_connector->edid)) !drm_detect_hdmi_monitor(nv_connector->edid))
proto |= 0x4; proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
} else { } else {
proto = 0x2; proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
} }
nv50_hdmi_enable(&nv_encoder->base.base, mode); nv50_hdmi_enable(&nv_encoder->base.base, mode);
break; break;
case DCB_OUTPUT_LVDS: case DCB_OUTPUT_LVDS:
proto = 0x0; proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
if (bios->fp_no_ddc) { if (bios->fp_no_ddc) {
if (bios->fp.dual_link) if (bios->fp.dual_link)
...@@ -1681,9 +1700,9 @@ nv50_sor_enable(struct drm_encoder *encoder) ...@@ -1681,9 +1700,9 @@ nv50_sor_enable(struct drm_encoder *encoder)
depth = nv50_dp_bpc_to_depth(asyh->or.bpc); depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
if (nv_encoder->link & 1) if (nv_encoder->link & 1)
proto = 0x8; proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
else else
proto = 0x9; proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
nv50_audio_enable(encoder, mode); nv50_audio_enable(encoder, mode);
break; break;
...@@ -1818,8 +1837,9 @@ nv50_pior_disable(struct drm_encoder *encoder) ...@@ -1818,8 +1837,9 @@ nv50_pior_disable(struct drm_encoder *encoder)
{ {
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nv50_core *core = nv50_disp(encoder->dev)->core; struct nv50_core *core = nv50_disp(encoder->dev)->core;
const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
if (nv_encoder->crtc) if (nv_encoder->crtc)
core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
nv_encoder->crtc = NULL; nv_encoder->crtc = NULL;
nv50_outp_release(nv_encoder); nv50_outp_release(nv_encoder);
} }
...@@ -1831,29 +1851,36 @@ nv50_pior_enable(struct drm_encoder *encoder) ...@@ -1831,29 +1851,36 @@ nv50_pior_enable(struct drm_encoder *encoder)
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
struct nv50_core *core = nv50_disp(encoder->dev)->core; struct nv50_core *core = nv50_disp(encoder->dev)->core;
u8 owner = 1 << nv_crtc->index; u32 ctrl = 0;
u8 proto;
switch (nv_crtc->index) {
case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
default:
WARN_ON(1);
break;
}
nv50_outp_acquire(nv_encoder, false); nv50_outp_acquire(nv_encoder, false);
switch (asyh->or.bpc) { switch (asyh->or.bpc) {
case 10: asyh->or.depth = 0x6; break; case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
case 8: asyh->or.depth = 0x5; break; case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
case 6: asyh->or.depth = 0x2; break; case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
default: asyh->or.depth = 0x0; break; default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
} }
switch (nv_encoder->dcb->type) { switch (nv_encoder->dcb->type) {
case DCB_OUTPUT_TMDS: case DCB_OUTPUT_TMDS:
case DCB_OUTPUT_DP: case DCB_OUTPUT_DP:
proto = 0x0; ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
break; break;
default: default:
BUG(); BUG();
break; break;
} }
core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
nv_encoder->crtc = encoder->crtc; nv_encoder->crtc = encoder->crtc;
} }
......
drivers/gpu/drm/nouveau/dispnv50/pior507d.c
View file @ 344c2e5a
...@@ -23,6 +23,9 @@ ...@@ -23,6 +23,9 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl507d.h>
#include <nvhw/class/cl837d.h>
static int static int
pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
struct nv50_head_atom *asyh) struct nv50_head_atom *asyh)
...@@ -31,15 +34,15 @@ pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -31,15 +34,15 @@ pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
int ret; int ret;
if (asyh) { if (asyh) {
ctrl |= asyh->or.depth << 16; ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync);
ctrl |= asyh->or.nvsync << 13; ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync);
ctrl |= asyh->or.nhsync << 12; ctrl |= NVVAL(NV837D, PIOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth);
} }
if ((ret = PUSH_WAIT(push, 2))) if ((ret = PUSH_WAIT(push, 2)))
return ret; return ret;
PUSH_NVSQ(push, NV507D, 0x0700 + (or * 0x040), ctrl); PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/dispnv50/sor507d.c
View file @ 344c2e5a
...@@ -23,6 +23,9 @@ ...@@ -23,6 +23,9 @@
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl507d.h>
#include <nvhw/class/cl837d.h>
static int static int
sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
struct nv50_head_atom *asyh) struct nv50_head_atom *asyh)
...@@ -31,15 +34,15 @@ sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -31,15 +34,15 @@ sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl,
int ret; int ret;
if (asyh) { if (asyh) {
ctrl |= asyh->or.depth << 16; ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync);
ctrl |= asyh->or.nvsync << 13; ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync);
ctrl |= asyh->or.nhsync << 12; ctrl |= NVVAL(NV837D, SOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth);
} }
if ((ret = PUSH_WAIT(push, 2))) if ((ret = PUSH_WAIT(push, 2)))
return ret; return ret;
PUSH_NVSQ(push, NV507D, 0x0600 + (or * 0x40), ctrl); PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/dispnv50/sor907d.c
View file @ 344c2e5a
...@@ -24,6 +24,8 @@ ...@@ -24,6 +24,8 @@
#include <nvif/class.h> #include <nvif/class.h>
#include <nvif/push507c.h> #include <nvif/push507c.h>
#include <nvhw/class/cl907d.h>
#include <nouveau_bo.h> #include <nouveau_bo.h>
static int static int
...@@ -36,7 +38,7 @@ sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -36,7 +38,7 @@ sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl,
if ((ret = PUSH_WAIT(push, 2))) if ((ret = PUSH_WAIT(push, 2)))
return ret; return ret;
PUSH_NVSQ(push, NV907D, 0x0200 + (or * 0x20), ctrl); PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/dispnv50/sorc37d.c
View file @ 344c2e5a
...@@ -21,7 +21,9 @@ ...@@ -21,7 +21,9 @@
*/ */
#include "core.h" #include "core.h"
#include <nvif/push507c.h> #include <nvif/pushc37b.h>
#include <nvhw/class/clc37d.h>
static int static int
sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl,
...@@ -33,7 +35,7 @@ sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, ...@@ -33,7 +35,7 @@ sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl,
if ((ret = PUSH_WAIT(push, 2))) if ((ret = PUSH_WAIT(push, 2)))
return ret; return ret;
PUSH_NVSQ(push, NVC37D, 0x0300 + (or * 0x20), ctrl); PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
return 0; return 0;
} }
......
drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h 0 → 100644
View file @ 344c2e5a
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl837d_h_
#define _cl837d_h_
// class methods
#define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV837D_SOR_SET_CONTROL_OWNER 3:0
#define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV837D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#define NV837D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040)
#define NV837D_PIOR_SET_CONTROL_OWNER 3:0
#define NV837D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER 5:4
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV837D_PIOR_SET_CONTROL_PROTOCOL 11:8
#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000)
#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001)
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#endif // _cl837d_h
drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h 0 → 100644
View file @ 344c2e5a
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl887d_h_
#define _cl887d_h_
#define NV887D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040)
#define NV887D_SOR_SET_CONTROL_OWNER 3:0
#define NV887D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER 5:4
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008)
#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009)
#endif // _cl887d_h
drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h 0 → 100644
View file @ 344c2e5a
This diff is collapsed.
drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h 0 → 100644
View file @ 344c2e5a
/*
* Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _cl917d_h_
#define _cl917d_h_
// class methods
#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004)
#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8
#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009)
#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000)
#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001)
#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002)
#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003)
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8
#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001)
#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003)
#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004)
#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001)
#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002)
#endif // _cl917d_h
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