Commit 34f73535 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 49936b5e e75a7bbb
...@@ -45,6 +45,12 @@ Machines ...@@ -45,6 +45,12 @@ Machines
Handheld (IPAQ), available in several varieties Handheld (IPAQ), available in several varieties
HP iPAQ rx3715
S3C2440 based IPAQ, with a number of variations depending on
features shipped.
NAND NAND
---- ----
...@@ -91,6 +97,8 @@ Port Contributors ...@@ -91,6 +97,8 @@ Port Contributors
Roc Wu Roc Wu
Klaus Fetscher Klaus Fetscher
Dimitry Andric Dimitry Andric
Shannon Holland
Document Changes Document Changes
---------------- ----------------
...@@ -99,8 +107,9 @@ Document Changes ...@@ -99,8 +107,9 @@ Document Changes
05 Sep 2004 - BJD - Added Klaus Fetscher to list of contributors 05 Sep 2004 - BJD - Added Klaus Fetscher to list of contributors
25 Oct 2004 - BJD - Added Dimitry Andric to list of contributors 25 Oct 2004 - BJD - Added Dimitry Andric to list of contributors
25 Oct 2004 - BJD - Updated the MTD from the 2.6.9 merge 25 Oct 2004 - BJD - Updated the MTD from the 2.6.9 merge
21 Jan 2005 - BJD - Added rx3715, added Shannon to contributors
Document Author Document Author
--------------- ---------------
Ben Dooks, (c) 2004 Simtec Electronics Ben Dooks, (c) 2004-2005 Simtec Electronics
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/irq.h> #include <asm/arch/irq.h>
#include <asm/arch/mmc.h> #include <asm/arch/mmc.h>
#include <asm/arch/udc.h>
#include <asm/arch/corgi.h> #include <asm/arch/corgi.h>
#include <asm/hardware/scoop.h> #include <asm/hardware/scoop.h>
...@@ -192,6 +193,27 @@ static struct pxamci_platform_data corgi_mci_platform_data = { ...@@ -192,6 +193,27 @@ static struct pxamci_platform_data corgi_mci_platform_data = {
}; };
/*
* USB Device Controller
*/
static void corgi_udc_command(int cmd)
{
switch(cmd) {
case PXA2XX_UDC_CMD_CONNECT:
GPSR(CORGI_GPIO_USB_PULLUP) = GPIO_bit(CORGI_GPIO_USB_PULLUP);
break;
case PXA2XX_UDC_CMD_DISCONNECT:
GPCR(CORGI_GPIO_USB_PULLUP) = GPIO_bit(CORGI_GPIO_USB_PULLUP);
break;
}
}
static struct pxa2xx_udc_mach_info udc_info __initdata = {
/* no connect GPIO; corgi can't tell connection status */
.udc_command = corgi_udc_command,
};
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&corgiscoop_device, &corgiscoop_device,
&corgissp_device, &corgissp_device,
...@@ -221,6 +243,8 @@ static void __init corgi_init(void) ...@@ -221,6 +243,8 @@ static void __init corgi_init(void)
else else
corgi_fb_info.phadadj=-1; corgi_fb_info.phadadj=-1;
pxa_gpio_mode(CORGI_GPIO_USB_PULLUP | GPIO_OUT);
pxa_set_udc_info(&udc_info);
pxa_set_mci_info(&corgi_mci_platform_data); pxa_set_mci_info(&corgi_mci_platform_data);
platform_add_devices(devices, ARRAY_SIZE(devices)); platform_add_devices(devices, ARRAY_SIZE(devices));
......
...@@ -213,6 +213,7 @@ static int corgi_ssp_remove(struct device *dev) ...@@ -213,6 +213,7 @@ static int corgi_ssp_remove(struct device *dev)
static int corgi_ssp_suspend(struct device *dev, u32 state, u32 level) static int corgi_ssp_suspend(struct device *dev, u32 state, u32 level)
{ {
if (level == SUSPEND_POWER_DOWN) { if (level == SUSPEND_POWER_DOWN) {
ssp_flush(&corgi_ssp_dev);
ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state); ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
} }
return 0; return 0;
......
...@@ -498,14 +498,18 @@ ...@@ -498,14 +498,18 @@
#define POCR __REG(0x40500000) /* PCM Out Control Register */ #define POCR __REG(0x40500000) /* PCM Out Control Register */
#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define PICR __REG(0x40500004) /* PCM In Control Register */ #define PICR __REG(0x40500004) /* PCM In Control Register */
#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define MCCR __REG(0x40500008) /* Mic In Control Register */ #define MCCR __REG(0x40500008) /* Mic In Control Register */
#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define GCR __REG(0x4050000C) /* Global Control Register */ #define GCR __REG(0x4050000C) /* Global Control Register */
#define GCR_nDMAEN (1 << 24) /* non DMA Enable */
#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
...@@ -519,12 +523,17 @@ ...@@ -519,12 +523,17 @@
#define POSR __REG(0x40500010) /* PCM Out Status Register */ #define POSR __REG(0x40500010) /* PCM Out Status Register */
#define POSR_FIFOE (1 << 4) /* FIFO error */ #define POSR_FIFOE (1 << 4) /* FIFO error */
#define POSR_FSR (1 << 2) /* FIFO Service Request */
#define PISR __REG(0x40500014) /* PCM In Status Register */ #define PISR __REG(0x40500014) /* PCM In Status Register */
#define PISR_FIFOE (1 << 4) /* FIFO error */ #define PISR_FIFOE (1 << 4) /* FIFO error */
#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
#define PISR_FSR (1 << 2) /* FIFO Service Request */
#define MCSR __REG(0x40500018) /* Mic In Status Register */ #define MCSR __REG(0x40500018) /* Mic In Status Register */
#define MCSR_FIFOE (1 << 4) /* FIFO error */ #define MCSR_FIFOE (1 << 4) /* FIFO error */
#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
#define MCSR_FSR (1 << 2) /* FIFO Service Request */
#define GSR __REG(0x4050001C) /* Global Status Register */ #define GSR __REG(0x4050001C) /* Global Status Register */
#define GSR_CDONE (1 << 19) /* Command Done */ #define GSR_CDONE (1 << 19) /* Command Done */
...@@ -537,9 +546,10 @@ ...@@ -537,9 +546,10 @@
#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
#define GSR_PCR (1 << 8) /* Primary Codec Ready */ #define GSR_PCR (1 << 8) /* Primary Codec Ready */
#define GSR_MINT (1 << 7) /* Mic In Interrupt */ #define GSR_MCINT (1 << 7) /* Mic In Interrupt */
#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
...@@ -552,15 +562,20 @@ ...@@ -552,15 +562,20 @@
#define MOCR __REG(0x40500100) /* Modem Out Control Register */ #define MOCR __REG(0x40500100) /* Modem Out Control Register */
#define MOCR_FEIE (1 << 3) /* FIFO Error */ #define MOCR_FEIE (1 << 3) /* FIFO Error */
#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define MICR __REG(0x40500108) /* Modem In Control Register */ #define MICR __REG(0x40500108) /* Modem In Control Register */
#define MICR_FEIE (1 << 3) /* FIFO Error */ #define MICR_FEIE (1 << 3) /* FIFO Error */
#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
#define MOSR __REG(0x40500110) /* Modem Out Status Register */ #define MOSR __REG(0x40500110) /* Modem Out Status Register */
#define MOSR_FIFOE (1 << 4) /* FIFO error */ #define MOSR_FIFOE (1 << 4) /* FIFO error */
#define MOSR_FSR (1 << 2) /* FIFO Service Request */
#define MISR __REG(0x40500118) /* Modem In Status Register */ #define MISR __REG(0x40500118) /* Modem In Status Register */
#define MISR_FIFOE (1 << 4) /* FIFO error */ #define MISR_FIFOE (1 << 4) /* FIFO error */
#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
#define MISR_FSR (1 << 2) /* FIFO Service Request */
#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
......
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