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Commit 3563b783 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-arm64-for-5.4' of... 

Merge tag 'qcom-arm64-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 Updates for v5.4

* Add Lenovo Miix 630, HP Envy x2, and Asus Novago TP370QL support
* Assorted cleanups for SDM845 nodes
* Add video nodes, cpu coefficients, adsp, csdp, and
  fastrpc nodes for SDM845
* Add coresight for MSM8996, SDM845, and MSM8998
* Misc cleanups on QCS404 and PMS405
* Update memory map for QCS404
* Add wifi rails, update WCSS clocks, and add ADS unit names on QCS404
* Add Longcheer and Samsung Galaxy A3U/A5U support
* Add initial support for SM8150 and PM8150

* tag 'qcom-arm64-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
  arm64: dts: sdm845: Add parent clock for rpmhcc
  arm64: dts: qcom: sm8150: Add apps shared nodes
  arm64: dts: qcom: sm8150: Add reserved-memory regions
  arm64: dts: qcom: sm8150-mtp: Add regulators
  arm64: dts: qcom: sm8150-mtp: Add base dts file
  arm64: dts: qcom: pm8150l: Add base dts file
  arm64: dts: qcom: pm8150b: Add base dts file
  arm64: dts: qcom: pm8150: Add base dts file
  arm64: dts: qcom: sm8150: Add base dts file
  arm64: sdm845: add adsp and cdsp fastrpc nodes
  arm64: dts: sdm845: Add dynamic CPU power coefficients
  arm64: dts: qcom: qcs404: Update memory map to v3
  arm64: dts: qcom: qcs404-evb: Mark WCSS clocks protected
  arm64: dts: qcom: Add device tree for Longcheer L8150
  arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U
  dt-bindings: qcom: Document bindings for new MSM8916 devices
  dt-bindings: vendor-prefixes: Add Longcheer Technology Co., Ltd.
  arm64: dts: qcom: msm8996: Add Venus video codec DT node
  arm64: dts: qcom: Extend AOSS QMP node
  arm64: dts: qcom: msm8996: Add Coresight support
  ...
parents ffcd65a5 1dd70853
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Documentation/devicetree/bindings/arm/qcom.yaml
View file @ 3563b783
......@@ -45,6 +45,7 @@ description: |
mtp
sbc
hk01
qrd
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
......@@ -115,6 +116,13 @@ properties:
- const: qcom,msm8916-mtp
- const: qcom,msm8916
- items:
- enum:
- longcheer,l8150
- samsung,a3u-eur
- samsung,a5u-eur
- const: qcom,msm8916
- items:
- const: qcom,msm8996-mtp
......
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file @ 3563b783
......@@ -537,6 +537,8 @@ patternProperties:
description: Linear Technology Corporation
"^logicpd,.*":
description: Logic PD, Inc.
"^longcheer,.*":
description: Longcheer Technology (Shanghai) Co., Ltd.
"^lsi,.*":
description: LSI Corp. (LSI Logic)
"^lwn,.*":
......
arch/arm64/boot/dts/qcom/Makefile
View file @ 3563b783
......@@ -3,14 +3,21 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916.dtsi"
#include "pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Longcheer L8150";
compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916";
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0";
};
soc {
sdhci@7824000 {
status = "okay";
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
};
sdhci@7864000 {
status = "okay";
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
non-removable;
};
serial@78b0000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
usb@78d9000 {
status = "okay";
dr_mode = "peripheral";
extcon = <&usb_vbus>;
hnp-disable;
srp-disable;
adp-disable;
ulpi {
phy {
extcon = <&usb_vbus>;
v1p8-supply = <&pm8916_l7>;
v3p3-supply = <&pm8916_l13>;
};
};
};
/*
* Attempting to enable these devices causes a "synchronous
* external abort". Suspected cause is that the debug power
* domain is not enabled by default on this device.
* Disable these devices for now to avoid the crash.
*
* See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/
*/
tpiu@820000 { status = "disabled"; };
funnel@821000 { status = "disabled"; };
replicator@824000 { status = "disabled"; };
etf@825000 { status = "disabled"; };
etr@826000 { status = "disabled"; };
funnel@841000 { status = "disabled"; };
debug@850000 { status = "disabled"; };
debug@852000 { status = "disabled"; };
debug@854000 { status = "disabled"; };
debug@856000 { status = "disabled"; };
etm@85c000 { status = "disabled"; };
etm@85d000 { status = "disabled"; };
etm@85e000 { status = "disabled"; };
etm@85f000 { status = "disabled"; };
};
// FIXME: Use extcon device provided by charger driver when available
usb_vbus: usb-vbus {
compatible = "linux,extcon-usb-gpio";
vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_vbus_default>;
};
};
&msmgpio {
usb_vbus_default: usb-vbus-default {
pinmux {
function = "gpio";
pins = "gpio62";
};
pinconf {
pins = "gpio62";
bias-pull-up;
};
};
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
s1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
};
s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
};
l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1287500>;
};
l4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
};
l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0-only
#include "msm8916.dtsi"
#include "pm8916.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
serial0 = &blsp1_uart2;
};
chosen {
stdout-path = "serial0";
};
soc {
sdhci@7824000 {
status = "okay";
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
};
sdhci@7864000 {
status = "okay";
vmmc-supply = <&pm8916_l11>;
vqmmc-supply = <&pm8916_l12>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>;
};
serial@78b0000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
usb@78d9000 {
status = "okay";
extcon = <&muic>, <&muic>;
hnp-disable;
srp-disable;
adp-disable;
ulpi {
phy {
extcon = <&muic>;
v1p8-supply = <&pm8916_l7>;
v3p3-supply = <&pm8916_l13>;
};
};
};
/*
* Attempting to enable these devices causes a "synchronous
* external abort". Suspected cause is that the debug power
* domain is not enabled by default on this device.
* Disable these devices for now to avoid the crash.
*
* See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/
*/
tpiu@820000 { status = "disabled"; };
funnel@821000 { status = "disabled"; };
replicator@824000 { status = "disabled"; };
etf@825000 { status = "disabled"; };
etr@826000 { status = "disabled"; };
funnel@841000 { status = "disabled"; };
debug@850000 { status = "disabled"; };
debug@852000 { status = "disabled"; };
debug@854000 { status = "disabled"; };
debug@856000 { status = "disabled"; };
etm@85c000 { status = "disabled"; };
etm@85d000 { status = "disabled"; };
etm@85e000 { status = "disabled"; };
etm@85f000 { status = "disabled"; };
};
i2c-muic {
compatible = "i2c-gpio";
sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
muic: sm5502@25 {
compatible = "siliconmitus,sm5502-muic";
reg = <0x25>;
interrupt-parent = <&msmgpio>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&muic_int_default>;
};
};
};
&msmgpio {
muic_int_default: muic_int_default {
pinmux {
function = "gpio";
pins = "gpio12";
};
pinconf {
pins = "gpio12";
drive-strength = <2>;
bias-disable;
};
};
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
vdd_l7-supply = <&pm8916_s4>;
s1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
};
s3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1300000>;
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
};
l1 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1287500>;
};
l4 {
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
};
l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l8 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2900000>;
};
l9 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l10 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
};
l11 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l13 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
};
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-a2015-common.dtsi"
/ {
model = "Samsung Galaxy A3U (EUR)";
compatible = "samsung,a3u-eur", "qcom,msm8916";
};
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-samsung-a2015-common.dtsi"
/ {
model = "Samsung Galaxy A5U (EUR)";
compatible = "samsung,a5u-eur", "qcom,msm8916";
};
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 3563b783
......@@ -633,6 +633,474 @@ gcc: clock-controller@300000 {
reg = <0x300000 0x90000>;
};
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
<0x8280000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint =
<&funnel0_in>;
};
};
};
};
tpiu@3020000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x3020000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint =
<&replicator_out1>;
};
};
};
};
funnel@3021000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3021000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in: endpoint {
remote-endpoint =
<&stm_out>;
};
};
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
};
funnel@3022000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3022000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel1_in: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint =
<&merge_funnel_in1>;
};
};
};
};
funnel@3023000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3023000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
funnel2_out: endpoint {
remote-endpoint =
<&merge_funnel_in2>;
};
};
};
};
funnel@3025000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3025000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint =
<&funnel1_out>;
};
};
port@2 {
reg = <2>;
merge_funnel_in2: endpoint {
remote-endpoint =
<&funnel2_out>;
};
};
};
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
};
replicator@3026000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x3026000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
replicator_in: endpoint {
remote-endpoint =
<&etf_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
};
etf@3027000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3027000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
etr@3028000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3028000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out0>;
};
};
};
};
debug@3810000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3810000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
};
etm@3840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3840000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel0_in0>;
};
};
};
};
debug@3910000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3910000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
};
etm@3940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3940000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel0_in1>;
};
};
};
};
funnel@39b0000 { /* APSS Funnel 0 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x39b0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel0_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel0_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
};
out-ports {
port {
apss_funnel0_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in0>;
};
};
};
};
debug@3a10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3a10000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
};
etm@3a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3a40000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel1_in0>;
};
};
};
};
debug@3b10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3b10000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
};
etm@3b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3b40000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel1_in1>;
};
};
};
};
funnel@3bb0000 { /* APSS Funnel 1 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bb0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel1_in0: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@1 {
reg = <1>;
apss_funnel1_in1: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
out-ports {
port {
apss_funnel1_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in1>;
};
};
};
};
funnel@3bc0000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bc0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_merge_funnel_in0: endpoint {
remote-endpoint =
<&apss_funnel0_out>;
};
};
port@1 {
reg = <1>;
apss_merge_funnel_in1: endpoint {
remote-endpoint =
<&apss_funnel1_out>;
};
};
};
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel1_in>;
};
};
};
};
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
reg = <0x6400000 0x90000>;
......@@ -1163,7 +1631,7 @@ dwc3@6a00000 {
};
};
vfe_smmu: arm,smmu@da0000 {
vfe_smmu: iommu@da0000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xda0000 0x10000>;
......@@ -1314,7 +1782,7 @@ ports {
};
};
adreno_smmu: arm,smmu@b40000 {
adreno_smmu: iommu@b40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xb40000 0x10000>;
......@@ -1331,7 +1799,7 @@ adreno_smmu: arm,smmu@b40000 {
power-domains = <&mmcc GPU_GDSC>;
};
mdp_smmu: arm,smmu@d00000 {
mdp_smmu: iommu@d00000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xd00000 0x10000>;
......@@ -1347,7 +1815,7 @@ mdp_smmu: arm,smmu@d00000 {
power-domains = <&mmcc MDSS_GDSC>;
};
lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
lpass_q6_smmu: iommu@1600000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x1600000 0x20000>;
#iommu-cells = <1>;
......@@ -1794,6 +2262,74 @@ hdmi_phy: hdmi-phy@9a0600 {
"ref";
};
};
venus_smmu: arm,smmu-venus@d40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xd40000 0x20000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
<&mmcc SMMU_VIDEO_AXI_CLK>;
clock-names = "iface", "bus";
#iommu-cells = <1>;
status = "okay";
};
video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc VENUS_GDSC>;
clocks = <&mmcc VIDEO_CORE_CLK>,
<&mmcc VIDEO_AHB_CLK>,
<&mmcc VIDEO_AXI_CLK>,
<&mmcc VIDEO_MAXI_CLK>;
clock-names = "core", "iface", "bus", "mbus";
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
status = "okay";
video-decoder {
compatible = "venus-decoder";
clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE0_GDSC>;
};
video-encoder {
compatible = "venus-encoder";
clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE1_GDSC>;
};
};
};
sound: sound {
......
arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */
/dts-v1/;
#include "msm8998-clamshell.dtsi"
/ {
model = "Asus NovaGo TP370QL";
compatible = "asus,novago-tp370ql", "qcom,msm8998";
};
&blsp1_i2c6 {
status = "okay";
touchpad@15 {
compatible = "hid-over-i2c";
interrupt-parent = <&tlmm>;
interrupts = <0x7b IRQ_TYPE_LEVEL_LOW>;
reg = <0x15>;
hid-descr-addr = <0x0001>;
pinctrl-names = "default";
pinctrl-0 = <&touchpad>;
};
keyboard@3a {
compatible = "hid-over-i2c";
interrupt-parent = <&tlmm>;
interrupts = <0x25 IRQ_TYPE_LEVEL_LOW>;
reg = <0x3a>;
hid-descr-addr = <0x0001>;
};
};
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
};
&tlmm {
touchpad: touchpad {
config {
pins = "gpio123";
bias-pull-up;
};
};
};
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */
/*
* Common include for MSM8998 clamshell devices, ie the Lenovo Miix 630,
* Asus NovaGo TP370QL, and HP Envy x2. All three devices are basically the
* same, with differences in peripherals.
*/
#include "msm8998.dtsi"
#include "pm8998.dtsi"
#include "pm8005.dtsi"
/ {
chosen {
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
};
&qusb2phy {
status = "okay";
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&rpm_requests {
pm8998-regulators {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_s13-supply = <&vph_pwr>;
vdd_l1_l27-supply = <&vreg_s7a_1p025>;
vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
vdd_l3_l11-supply = <&vreg_s7a_1p025>;
vdd_l4_l5-supply = <&vreg_s7a_1p025>;
vdd_l6-supply = <&vreg_s5a_2p04>;
vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
vdd_l9-supply = <&vph_pwr>;
vdd_l10_l23_l25-supply = <&vph_pwr>;
vdd_l13_l19_l21-supply = <&vph_pwr>;
vdd_l16_l28-supply = <&vph_pwr>;
vdd_l18_l22-supply = <&vph_pwr>;
vdd_l20_l24-supply = <&vph_pwr>;
vdd_l26-supply = <&vreg_s3a_1p35>;
vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p35: s3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s4a_1p8: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
};
vreg_s5a_2p04: s5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: s7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vreg_l1a_0p875: l1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-allow-set-load;
};
vreg_l2a_1p2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
vreg_l3a_1p0: l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l5a_0p8: l5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l6a_1p8: l6 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <1808000>;
};
vreg_l7a_1p8: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l8a_1p2: l8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l11a_1p0: l11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l13a_2p95: l13 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l14a_1p88: l14 {
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
vreg_15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
vreg_l18a_2p7: l18 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
vreg_l19a_3p0: l19 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
vreg_l20a_2p95: l20 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-allow-set-load;
};
vreg_l21a_2p95: l21 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-allow-set-load;
regulator-system-load = <800000>;
};
vreg_l22a_2p85: l22 {
regulator-min-microvolt = <2864000>;
regulator-max-microvolt = <2864000>;
};
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
};
vreg_l24a_3p075: l24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
};
vreg_l25a_3p3: l25 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3312000>;
};
vreg_l26a_1p2: l26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l28_3p0: l28 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
touchpad: touchpad {
config {
pins = "gpio123";
bias-pull-up; /* pull up */
};
};
};
&sdhc2 {
status = "okay";
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "host"; /* Force to host until we have Type-C hooked up */
};
&usb3phy {
status = "okay";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
};
arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */
/dts-v1/;
#include "msm8998-clamshell.dtsi"
/ {
model = "HP Envy x2";
compatible = "hp,envy-x2", "qcom,msm8998";
};
&blsp1_i2c6 {
status = "okay";
keyboard@3a {
compatible = "hid-over-i2c";
interrupt-parent = <&tlmm>;
interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>;
reg = <0x3a>;
hid-descr-addr = <0x0001>;
pinctrl-names = "default";
pinctrl-0 = <&touchpad>;
};
};
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_LOW>;
};
arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2019, Jeffrey Hugo. All rights reserved. */
/dts-v1/;
#include "msm8998-clamshell.dtsi"
/ {
model = "Lenovo Miix 630";
compatible = "lenovo,miix-630", "qcom,msm8998";
};
&blsp1_i2c6 {
status = "okay";
keyboard@3a {
compatible = "hid-over-i2c";
interrupt-parent = <&tlmm>;
interrupts = <0x79 IRQ_TYPE_LEVEL_LOW>;
reg = <0x3a>;
hid-descr-addr = <0x0001>;
pinctrl-names = "default";
pinctrl-0 = <&touchpad>;
};
};
&sdhc2 {
cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
};
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 3563b783
......@@ -787,14 +787,22 @@ soc: soc {
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
rpm_msg_ram: memory@68000 {
gcc: clock-controller@100000 {
compatible = "qcom,gcc-msm8998";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00100000 0xb0000>;
};
rpm_msg_ram: memory@778000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x778000 0x7000>;
reg = <0x00778000 0x7000>;
};
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x780000 0x621c>;
reg = <0x00780000 0x621c>;
#address-cells = <1>;
#size-cells = <1>;
......@@ -804,47 +812,10 @@ qusb2_hstx_trim: hstx-trim@423a {
};
};
gcc: clock-controller@100000 {
compatible = "qcom,gcc-msm8998";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x100000 0xb0000>;
};
tlmm: pinctrl@3400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x3400000 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x800f000 0x1000>,
<0x8400000 0x1000000>,
<0x9400000 0x1000000>,
<0xa400000 0x220000>,
<0x800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
tsens0: thermal@10ab000 {
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
reg = <0x10ab000 0x1000>, /* TM */
<0x10aa000 0x1000>; /* SROT */
reg = <0x010ab000 0x1000>, /* TM */
<0x010aa000 0x1000>; /* SROT */
#qcom,sensors = <14>;
#thermal-sensor-cells = <1>;
......@@ -852,8 +823,8 @@ tsens0: thermal@10ab000 {
tsens1: thermal@10ae000 {
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
reg = <0x10ae000 0x1000>, /* TM */
<0x10ad000 0x1000>; /* SROT */
reg = <0x010ae000 0x1000>, /* TM */
<0x010ad000 0x1000>; /* SROT */
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
......@@ -943,16 +914,542 @@ pciephy: lane@1c06800 {
};
};
ufshc: ufshc@1da4000 {
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x01da4000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
#reset-cells = <1>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK1>,
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
resets = <&gcc GCC_UFS_BCR>;
reset-names = "rst";
};
ufsphy: phy@1da7000 {
compatible = "qcom,msm8998-qmp-ufs-phy";
reg = <0x01da7000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names =
"ref",
"ref_aux";
clocks =
<&gcc GCC_UFS_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_AUX_CLK>;
reset-names = "ufsphy";
resets = <&ufshc 0>;
ufsphy_lanes: lanes@1da7400 {
reg = <0x01da7400 0x128>,
<0x01da7600 0x1fc>,
<0x01da7c00 0x1dc>,
<0x01da7800 0x128>,
<0x01da7a00 0x1fc>;
#phy-cells = <0>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
reg = <0x01f40000 0x20000>;
};
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8998-apcs-hmss-global";
reg = <0x17911000 0x1000>;
tlmm: pinctrl@3400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x03400000 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
#mbox-cells = <1>;
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x06002000 0x1000>,
<0x16280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel0_in7>;
};
};
};
};
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06041000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
};
funnel@6042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06042000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint =
<&merge_funnel_in1>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel1_in6: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
};
funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x06045000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint =
<&funnel1_out>;
};
};
};
};
replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x06046000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
replicator_out: endpoint {
remote-endpoint = <&etr_in>;
};
};
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&etf_out>;
};
};
};
};
etf@6047000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x06047000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
};
etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x06048000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out>;
};
};
};
};
etm@7840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07840000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel_in0>;
};
};
};
};
etm@7940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07940000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel_in1>;
};
};
};
};
etm@7a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07a40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel_in2>;
};
};
};
};
etm@7b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07b40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel_in3>;
};
};
};
};
funnel@7b60000 { /* APSS Funnel */
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07b60000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
apss_funnel_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel_in0: endpoint {
remote-endpoint =
<&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel_in1: endpoint {
remote-endpoint =
<&etm1_out>;
};
};
port@2 {
reg = <2>;
apss_funnel_in2: endpoint {
remote-endpoint =
<&etm2_out>;
};
};
port@3 {
reg = <3>;
apss_funnel_in3: endpoint {
remote-endpoint =
<&etm3_out>;
};
};
port@4 {
reg = <4>;
apss_funnel_in4: endpoint {
remote-endpoint =
<&etm4_out>;
};
};
port@5 {
reg = <5>;
apss_funnel_in5: endpoint {
remote-endpoint =
<&etm5_out>;
};
};
port@6 {
reg = <6>;
apss_funnel_in6: endpoint {
remote-endpoint =
<&etm6_out>;
};
};
port@7 {
reg = <7>;
apss_funnel_in7: endpoint {
remote-endpoint =
<&etm7_out>;
};
};
};
};
funnel@7b70000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x07b70000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel1_in6>;
};
};
};
in-ports {
port {
apss_merge_funnel_in: endpoint {
remote-endpoint =
<&apss_funnel_out>;
};
};
};
};
etm@7c40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07c40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU4>;
port{
etm4_out: endpoint {
remote-endpoint = <&apss_funnel_in4>;
};
};
};
etm@7d40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07d40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU5>;
port{
etm5_out: endpoint {
remote-endpoint = <&apss_funnel_in5>;
};
};
};
etm@7e40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07e40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU6>;
port{
etm6_out: endpoint {
remote-endpoint = <&apss_funnel_in6>;
};
};
};
etm@7f40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x07f40000 0x1000>;
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU7>;
port{
etm7_out: endpoint {
remote-endpoint = <&apss_funnel_in7>;
};
};
};
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0800f000 0x1000>,
<0x08400000 0x1000000>,
<0x09400000 0x1000000>,
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
usb3: usb@a8f8800 {
......@@ -1044,7 +1541,7 @@ qusb2phy: phy@c012000 {
sdhc2: sdhci@c0a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
......@@ -1149,6 +1646,16 @@ blsp1_i2c6: i2c@c17a000 {
#size-cells = <0>;
};
blsp2_uart1: serial@c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c1b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp2_i2c0: i2c@c1b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c1b5000 0x600>;
......@@ -1239,14 +1746,11 @@ blsp2_i2c5: i2c@c1ba000 {
#size-cells = <0>;
};
blsp2_uart1: serial@c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xc1b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
apcs_glb: mailbox@17911000 {
compatible = "qcom,msm8998-apcs-hmss-global";
reg = <0x17911000 0x1000>;
#mbox-cells = <1>;
};
timer@17920000 {
......@@ -1320,75 +1824,6 @@ intc: interrupt-controller@17a00000 {
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
ufshc: ufshc@1da4000 {
compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x01da4000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
power-domains = <&gcc UFS_GDSC>;
#reset-cells = <1>;
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK1>,
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
resets = <&gcc GCC_UFS_BCR>;
reset-names = "rst";
};
ufsphy: phy@1da7000 {
compatible = "qcom,msm8998-qmp-ufs-phy";
reg = <0x01da7000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-names =
"ref",
"ref_aux";
clocks =
<&gcc GCC_UFS_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_AUX_CLK>;
reset-names = "ufsphy";
resets = <&ufshc 0>;
ufsphy_lanes: lanes@1da7400 {
reg = <0x01da7400 0x128>,
<0x01da7600 0x1fc>,
<0x01da7c00 0x1dc>,
<0x01da7800 0x128>,
<0x01da7a00 0x1fc>;
#phy-cells = <0>;
};
};
};
};
......
arch/arm64/boot/dts/qcom/pm8150.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
pm8150_0: pmic@0 {
compatible = "qcom,pm8150", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
status = "disabled";
};
};
pm8150_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
status = "disabled";
};
pm8150_gpios: gpio@c000 {
compatible = "qcom,pm8150-gpio";
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <0x0 0xc0 0x0 IRQ_TYPE_NONE>,
<0x0 0xc1 0x0 IRQ_TYPE_NONE>,
<0x0 0xc2 0x0 IRQ_TYPE_NONE>,
<0x0 0xc3 0x0 IRQ_TYPE_NONE>,
<0x0 0xc4 0x0 IRQ_TYPE_NONE>,
<0x0 0xc5 0x0 IRQ_TYPE_NONE>,
<0x0 0xc6 0x0 IRQ_TYPE_NONE>,
<0x0 0xc7 0x0 IRQ_TYPE_NONE>,
<0x0 0xc8 0x0 IRQ_TYPE_NONE>,
<0x0 0xc9 0x0 IRQ_TYPE_NONE>,
<0x0 0xca 0x0 IRQ_TYPE_NONE>,
<0x0 0xcb 0x0 IRQ_TYPE_NONE>;
};
};
pmic@1 {
compatible = "qcom,pm8150", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8150b.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@2 {
compatible = "qcom,pm8150b", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
status = "disabled";
};
adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
chg-temp@9 {
reg = <ADC5_CHG_TEMP>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";
};
};
pm8150b_gpios: gpio@c000 {
compatible = "qcom,pm8150b-gpio";
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>,
<0x2 0xc1 0x0 IRQ_TYPE_NONE>,
<0x2 0xc2 0x0 IRQ_TYPE_NONE>,
<0x2 0xc3 0x0 IRQ_TYPE_NONE>,
<0x2 0xc4 0x0 IRQ_TYPE_NONE>,
<0x2 0xc5 0x0 IRQ_TYPE_NONE>,
<0x2 0xc6 0x0 IRQ_TYPE_NONE>,
<0x2 0xc7 0x0 IRQ_TYPE_NONE>,
<0x2 0xc8 0x0 IRQ_TYPE_NONE>,
<0x2 0xc9 0x0 IRQ_TYPE_NONE>,
<0x2 0xca 0x0 IRQ_TYPE_NONE>,
<0x2 0xcb 0x0 IRQ_TYPE_NONE>;
};
};
pmic@3 {
compatible = "qcom,pm8150b", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8150l.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@4 {
compatible = "qcom,pm8150l", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
status = "disabled";
};
adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
ref-gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
};
pm8150l_gpios: gpio@c000 {
compatible = "qcom,pm8150l-gpio";
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>,
<0x4 0xc1 0x0 IRQ_TYPE_NONE>,
<0x4 0xc2 0x0 IRQ_TYPE_NONE>,
<0x4 0xc3 0x0 IRQ_TYPE_NONE>,
<0x4 0xc4 0x0 IRQ_TYPE_NONE>,
<0x4 0xc5 0x0 IRQ_TYPE_NONE>,
<0x4 0xc6 0x0 IRQ_TYPE_NONE>,
<0x4 0xc7 0x0 IRQ_TYPE_NONE>,
<0x4 0xc8 0x0 IRQ_TYPE_NONE>,
<0x4 0xc9 0x0 IRQ_TYPE_NONE>,
<0x4 0xca 0x0 IRQ_TYPE_NONE>,
<0x4 0xcb 0x0 IRQ_TYPE_NONE>;
};
};
pmic@5 {
compatible = "qcom,pm8150l", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8998.dtsi
View file @ 3563b783
......@@ -78,7 +78,7 @@ pm8998_adc: adc@3100 {
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@ADC5_DIE_TEMP {
adc-chan@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};
......
arch/arm64/boot/dts/qcom/pms405.dtsi
View file @ 3563b783
......@@ -88,41 +88,41 @@ pms405_adc: adc@3100 {
#size-cells = <0>;
#io-channel-cells = <1>;
ref_gnd {
ref_gnd@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
};
vref_1p25 {
vref_1p25@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
};
pon_1: vph_pwr {
pon_1: vph_pwr@131 {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
};
die_temp {
die_temp@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
};
pa_therm1: thermistor1 {
pa_therm1: thermistor1@77 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pa_therm3: thermistor3 {
pa_therm3: thermistor3@79 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
xo_therm: xo_temp {
xo_therm: xo_temp@76 {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
......@@ -141,8 +141,6 @@ rtc@6000 {
pms405_1: pms405@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pms405_spmi_regulators: regulators {
compatible = "qcom,pms405-regulators";
......
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file @ 3563b783
......@@ -61,7 +61,9 @@ &gcc {
protected-clocks = <GCC_BIMC_CDSP_CLK>,
<GCC_CDSP_CFG_AHB_CLK>,
<GCC_CDSP_BIMC_CLK_SRC>,
<GCC_CDSP_TBU_CLK>;
<GCC_CDSP_TBU_CLK>,
<141>, /* GCC_WCSS_Q6_AHB_CLK */
<142>; /* GCC_WCSS_Q6_AXIM_CLK */
};
&pms405_spmi_regulators {
......@@ -270,6 +272,9 @@ rclk {
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
vdd-1.8-xo-supply = <&vreg_l5_1p8>;
vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
};
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 3563b783
......@@ -111,8 +111,13 @@ reserved-memory {
#size-cells = <2>;
ranges;
memory@85600000 {
reg = <0 0x85600000 0 0x90000>;
tz_apps_mem: memory@85900000 {
reg = <0 0x85900000 0 0x500000>;
no-map;
};
xbl_mem: memory@85e00000 {
reg = <0 0x85e00000 0 0x100000>;
no-map;
};
......@@ -121,28 +126,33 @@ smem_region: memory@85f00000 {
no-map;
};
memory@86100000 {
tz_mem: memory@86100000 {
reg = <0 0x86100000 0 0x300000>;
no-map;
};
wlan_fw_mem: memory@86400000 {
reg = <0 0x86400000 0 0x1c00000>;
reg = <0 0x86400000 0 0x1100000>;
no-map;
};
adsp_fw_mem: memory@87500000 {
reg = <0 0x87500000 0 0x1a00000>;
no-map;
};
adsp_fw_mem: memory@88000000 {
reg = <0 0x88000000 0 0x1a00000>;
cdsp_fw_mem: memory@88f00000 {
reg = <0 0x88f00000 0 0x600000>;
no-map;
};
cdsp_fw_mem: memory@89a00000 {
reg = <0 0x89a00000 0 0x600000>;
wlan_msa_mem: memory@89500000 {
reg = <0 0x89500000 0 0x100000>;
no-map;
};
wlan_msa_mem: memory@8a000000 {
reg = <0 0x8a000000 0 0x100000>;
uefi_mem: memory@9f800000 {
reg = <0 0x9f800000 0 0x800000>;
no-map;
};
};
......@@ -1077,7 +1087,7 @@ aoss-thermal {
thermal-sensors = <&tsens 0>;
trips {
aoss_alert0: trip-point@0 {
aoss_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
......@@ -1092,7 +1102,7 @@ q6-hvx-thermal {
thermal-sensors = <&tsens 1>;
trips {
q6_hvx_alert0: trip-point@0 {
q6_hvx_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
......@@ -1107,7 +1117,7 @@ lpass-thermal {
thermal-sensors = <&tsens 2>;
trips {
lpass_alert0: trip-point@0 {
lpass_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
......@@ -1122,7 +1132,7 @@ wlan-thermal {
thermal-sensors = <&tsens 3>;
trips {
wlan_alert0: trip-point@0 {
wlan_alert0: trip-point0 {
temperature = <105000>;
hysteresis = <2000>;
type = "hot";
......@@ -1137,12 +1147,12 @@ cluster-thermal {
thermal-sensors = <&tsens 4>;
trips {
cluster_alert0: trip-point@0 {
cluster_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cluster_alert1: trip-point@1 {
cluster_alert1: trip-point1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
......@@ -1171,12 +1181,12 @@ cpu0-thermal {
thermal-sensors = <&tsens 5>;
trips {
cpu0_alert0: trip-point@0 {
cpu0_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu0_alert1: trip-point@1 {
cpu0_alert1: trip-point1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
......@@ -1205,12 +1215,12 @@ cpu1-thermal {
thermal-sensors = <&tsens 6>;
trips {
cpu1_alert0: trip-point@0 {
cpu1_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu1_alert1: trip-point@1 {
cpu1_alert1: trip-point1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
......@@ -1239,12 +1249,12 @@ cpu2-thermal {
thermal-sensors = <&tsens 7>;
trips {
cpu2_alert0: trip-point@0 {
cpu2_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu2_alert1: trip-point@1 {
cpu2_alert1: trip-point1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
......@@ -1273,12 +1283,12 @@ cpu3-thermal {
thermal-sensors = <&tsens 8>;
trips {
cpu3_alert0: trip-point@0 {
cpu3_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu3_alert1: trip-point@1 {
cpu3_alert1: trip-point1 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
......@@ -1307,7 +1317,7 @@ gpu-thermal {
thermal-sensors = <&tsens 9>;
trips {
gpu_alert0: trip-point@0 {
gpu_alert0: trip-point0 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
......
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file @ 3563b783
......@@ -745,7 +745,7 @@ &usb_1_dwc3 {
* All the hardware muxes would allow us to hook things up in different
* ways to some potential benefit for static configurations (you could
* achieve extra USB2 bandwidth by using two different ports for the
* two conenctors or possibly even get USB3 peripheral mode), but in
* two connectors or possibly even get USB3 peripheral mode), but in
* each case you end up forcing to disconnect/reconnect an in-use
* USB session in some cases depending on what you hotplug into the
* other connector. Thus hardcoding this as peripheral makes sense.
......@@ -963,27 +963,27 @@ &pm8005_gpio {
};
&pm8998_adc {
adc-chan@ADC5_AMUX_THM1_100K_PU {
adc-chan@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
label = "sdm_temp";
};
adc-chan@ADC5_AMUX_THM2_100K_PU {
adc-chan@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
label = "quiet_temp";
};
adc-chan@ADC5_AMUX_THM3_100K_PU {
adc-chan@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
label = "lte_temp_1";
};
adc-chan@ADC5_AMUX_THM4_100K_PU {
adc-chan@50 {
reg = <ADC5_AMUX_THM4_100K_PU>;
label = "lte_temp_2";
};
adc-chan@ADC5_AMUX_THM5_100K_PU {
adc-chan@51 {
reg = <ADC5_AMUX_THM5_100K_PU>;
label = "charger_temp";
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 3563b783
......@@ -194,6 +194,7 @@ CPU0: cpu@0 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
......@@ -215,6 +216,7 @@ CPU1: cpu@100 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
next-level-cache = <&L2_100>;
......@@ -233,6 +235,7 @@ CPU2: cpu@200 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
next-level-cache = <&L2_200>;
......@@ -251,6 +254,7 @@ CPU3: cpu@300 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
next-level-cache = <&L2_300>;
......@@ -269,6 +273,7 @@ CPU4: cpu@400 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
......@@ -287,6 +292,7 @@ CPU5: cpu@500 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
......@@ -305,6 +311,7 @@ CPU6: cpu@600 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
......@@ -323,6 +330,7 @@ CPU7: cpu@700 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
......@@ -483,6 +491,25 @@ glink-edge {
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apss_shared 8>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1823 0x0>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1824 0x0>;
};
};
};
};
......@@ -512,6 +539,61 @@ glink-edge {
label = "turing";
qcom,remote-pid = <5>;
mboxes = <&apss_shared 4>;
fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
#address-cells = <1>;
#size-cells = <0>;
compute-cb@1 {
compatible = "qcom,fastrpc-compute-cb";
reg = <1>;
iommus = <&apps_smmu 0x1401 0x30>;
};
compute-cb@2 {
compatible = "qcom,fastrpc-compute-cb";
reg = <2>;
iommus = <&apps_smmu 0x1402 0x30>;
};
compute-cb@3 {
compatible = "qcom,fastrpc-compute-cb";
reg = <3>;
iommus = <&apps_smmu 0x1403 0x30>;
};
compute-cb@4 {
compatible = "qcom,fastrpc-compute-cb";
reg = <4>;
iommus = <&apps_smmu 0x1404 0x30>;
};
compute-cb@5 {
compatible = "qcom,fastrpc-compute-cb";
reg = <5>;
iommus = <&apps_smmu 0x1405 0x30>;
};
compute-cb@6 {
compatible = "qcom,fastrpc-compute-cb";
reg = <6>;
iommus = <&apps_smmu 0x1406 0x30>;
};
compute-cb@7 {
compatible = "qcom,fastrpc-compute-cb";
reg = <7>;
iommus = <&apps_smmu 0x1407 0x30>;
};
compute-cb@8 {
compatible = "qcom,fastrpc-compute-cb";
reg = <8>;
iommus = <&apps_smmu 0x1408 0x30>;
};
};
};
};
......@@ -620,7 +702,7 @@ psci {
method = "smc";
};
soc: soc {
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
......@@ -1275,6 +1357,13 @@ uart15: serial@a9c000 {
};
};
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
......@@ -1815,6 +1904,457 @@ gpucc: clock-controller@5090000 {
clock-names = "xo";
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
<0 0x16280000 0 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint =
<&funnel0_in7>;
};
};
};
};
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06041000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
};
funnel@6043000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06043000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
funnel2_out: endpoint {
remote-endpoint =
<&merge_funnel_in2>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@5 {
reg = <5>;
funnel2_in5: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
};
funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x06045000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint = <&etf_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
port@2 {
reg = <2>;
merge_funnel_in2: endpoint {
remote-endpoint =
<&funnel2_out>;
};
};
};
};
replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0 0x06046000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
replicator_out: endpoint {
remote-endpoint = <&etr_in>;
};
};
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint = <&etf_out>;
};
};
};
};
etf@6047000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06047000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
};
etr@6048000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0 0x06048000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out>;
};
};
};
};
etm@7040000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel_in0>;
};
};
};
};
etm@7140000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel_in1>;
};
};
};
};
etm@7240000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel_in2>;
};
};
};
};
etm@7340000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel_in3>;
};
};
};
};
etm@7440000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&apss_funnel_in4>;
};
};
};
};
etm@7540000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&apss_funnel_in5>;
};
};
};
};
etm@7640000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&apss_funnel_in6>;
};
};
};
};
etm@7740000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&apss_funnel_in7>;
};
};
};
};
funnel@7800000 { /* APSS Funnel */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07800000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
apss_funnel_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel_in0: endpoint {
remote-endpoint =
<&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel_in1: endpoint {
remote-endpoint =
<&etm1_out>;
};
};
port@2 {
reg = <2>;
apss_funnel_in2: endpoint {
remote-endpoint =
<&etm2_out>;
};
};
port@3 {
reg = <3>;
apss_funnel_in3: endpoint {
remote-endpoint =
<&etm3_out>;
};
};
port@4 {
reg = <4>;
apss_funnel_in4: endpoint {
remote-endpoint =
<&etm4_out>;
};
};
port@5 {
reg = <5>;
apss_funnel_in5: endpoint {
remote-endpoint =
<&etm5_out>;
};
};
port@6 {
reg = <6>;
apss_funnel_in6: endpoint {
remote-endpoint =
<&etm6_out>;
};
};
port@7 {
reg = <7>;
apss_funnel_in7: endpoint {
remote-endpoint =
<&etm7_out>;
};
};
};
};
funnel@7810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x07810000 0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel2_in5>;
};
};
};
in-ports {
port {
apss_merge_funnel_in: endpoint {
remote-endpoint =
<&apss_funnel_out>;
};
};
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
......@@ -2027,6 +2567,36 @@ usb_2_dwc3: dwc3@a800000 {
};
};
video-codec@aa00000 {
compatible = "qcom,sdm845-venus";
reg = <0 0x0aa00000 0 0xff000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&videocc VENUS_GDSC>;
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>,
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
clock-names = "core", "iface", "bus";
iommus = <&apps_smmu 0x10a0 0x8>,
<&apps_smmu 0x10b0 0x0>;
memory-region = <&venus_mem>;
video-core0 {
compatible = "venus-decoder";
clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
clock-names = "core", "bus";
power-domains = <&videocc VCODEC0_GDSC>;
};
video-core1 {
compatible = "venus-encoder";
clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
<&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
clock-names = "core", "bus";
power-domains = <&videocc VCODEC1_GDSC>;
};
};
videocc: clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0 0x0ab00000 0 0x10000>;
......@@ -2131,9 +2701,6 @@ dsi0: dsi@ae94000 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
......@@ -2198,9 +2765,6 @@ dsi1: dsi@ae96000 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
......@@ -2411,6 +2975,14 @@ aoss_qmp: qmp@c300000 {
#clock-cells = <0>;
#power-domain-cells = <1>;
cx_cdev: cx {
#cooling-cells = <2>;
};
ebi_cdev: ebi {
#cooling-cells = <2>;
};
};
spmi_bus: spmi@c440000 {
......@@ -2538,6 +3110,8 @@ apps_rsc: rsc@179c0000 {
rpmhcc: clock-controller {
compatible = "qcom,sdm845-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
rpmhpd: power-controller {
......@@ -2718,13 +3292,13 @@ cpu0-thermal {
thermal-sensors = <&tsens0 1>;
trips {
cpu0_alert0: trip-point@0 {
cpu0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_alert1: trip-point@1 {
cpu0_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2762,13 +3336,13 @@ cpu1-thermal {
thermal-sensors = <&tsens0 2>;
trips {
cpu1_alert0: trip-point@0 {
cpu1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_alert1: trip-point@1 {
cpu1_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2806,13 +3380,13 @@ cpu2-thermal {
thermal-sensors = <&tsens0 3>;
trips {
cpu2_alert0: trip-point@0 {
cpu2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_alert1: trip-point@1 {
cpu2_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2850,13 +3424,13 @@ cpu3-thermal {
thermal-sensors = <&tsens0 4>;
trips {
cpu3_alert0: trip-point@0 {
cpu3_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_alert1: trip-point@1 {
cpu3_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2894,13 +3468,13 @@ cpu4-thermal {
thermal-sensors = <&tsens0 7>;
trips {
cpu4_alert0: trip-point@0 {
cpu4_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_alert1: trip-point@1 {
cpu4_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2938,13 +3512,13 @@ cpu5-thermal {
thermal-sensors = <&tsens0 8>;
trips {
cpu5_alert0: trip-point@0 {
cpu5_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_alert1: trip-point@1 {
cpu5_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -2982,13 +3556,13 @@ cpu6-thermal {
thermal-sensors = <&tsens0 9>;
trips {
cpu6_alert0: trip-point@0 {
cpu6_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_alert1: trip-point@1 {
cpu6_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -3026,13 +3600,13 @@ cpu7-thermal {
thermal-sensors = <&tsens0 10>;
trips {
cpu7_alert0: trip-point@0 {
cpu7_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_alert1: trip-point@1 {
cpu7_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
......@@ -3070,7 +3644,7 @@ aoss0-thermal {
thermal-sensors = <&tsens0 0>;
trips {
aoss0_alert0: trip-point@0 {
aoss0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3085,7 +3659,7 @@ cluster0-thermal {
thermal-sensors = <&tsens0 5>;
trips {
cluster0_alert0: trip-point@0 {
cluster0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3105,7 +3679,7 @@ cluster1-thermal {
thermal-sensors = <&tsens0 6>;
trips {
cluster1_alert0: trip-point@0 {
cluster1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3125,7 +3699,7 @@ gpu-thermal-top {
thermal-sensors = <&tsens0 11>;
trips {
gpu1_alert0: trip-point@0 {
gpu1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3140,7 +3714,7 @@ gpu-thermal-bottom {
thermal-sensors = <&tsens0 12>;
trips {
gpu2_alert0: trip-point@0 {
gpu2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3155,7 +3729,7 @@ aoss1-thermal {
thermal-sensors = <&tsens1 0>;
trips {
aoss1_alert0: trip-point@0 {
aoss1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3170,7 +3744,7 @@ q6-modem-thermal {
thermal-sensors = <&tsens1 1>;
trips {
q6_modem_alert0: trip-point@0 {
q6_modem_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3185,7 +3759,7 @@ mem-thermal {
thermal-sensors = <&tsens1 2>;
trips {
mem_alert0: trip-point@0 {
mem_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3200,7 +3774,7 @@ wlan-thermal {
thermal-sensors = <&tsens1 3>;
trips {
wlan_alert0: trip-point@0 {
wlan_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3215,7 +3789,7 @@ q6-hvx-thermal {
thermal-sensors = <&tsens1 4>;
trips {
q6_hvx_alert0: trip-point@0 {
q6_hvx_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3230,7 +3804,7 @@ camera-thermal {
thermal-sensors = <&tsens1 5>;
trips {
camera_alert0: trip-point@0 {
camera_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3245,7 +3819,7 @@ video-thermal {
thermal-sensors = <&tsens1 6>;
trips {
video_alert0: trip-point@0 {
video_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......@@ -3260,7 +3834,7 @@ modem-thermal {
thermal-sensors = <&tsens1 7>;
trips {
modem_alert0: trip-point@0 {
modem_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
......
arch/arm64/boot/dts/qcom/sm8150-mtp.dts 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8150.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
#include "pm8150l.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8150 MTP";
compatible = "qcom,sm8150-mtp";
aliases {
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
/*
* Apparently RPMh does not provide support for PM8150 S4 because it
* is always-on; model it as a fixed regulator.
*/
vreg_s4a_1p8: pm8150-s4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
};
&apps_rsc {
pm8150-rpmh-regulators {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
vdd-l2-l10-supply = <&vreg_bob>;
vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
vdd-l6-l9-supply = <&vreg_s8c_1p3>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
vdd-l13-l16-l17-supply = <&vreg_bob>;
vreg_s5a_2p0: smps5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2000000>;
};
vreg_s6a_0p9: smps6 {
regulator-min-microvolt = <920000>;
regulator-max-microvolt = <1128000>;
};
vdda_wcss_pll:
vreg_l1a_0p75: ldo1 {
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <752000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_pdphy:
vdda_usb_hs_3p1:
vreg_l2a_3p1: ldo2 {
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a_0p8: ldo3 {
regulator-min-microvolt = <480000>;
regulator-max-microvolt = <932000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_usb_hs_core:
vdda_csi_0_0p9:
vdda_csi_1_0p9:
vdda_csi_2_0p9:
vdda_csi_3_0p9:
vdda_dsi_0_0p9:
vdda_dsi_1_0p9:
vdda_dsi_0_pll_0p9:
vdda_dsi_1_pll_0p9:
vdda_pcie_1ln_core:
vdda_pcie_2ln_core:
vdda_pll_hv_cc_ebi01:
vdda_pll_hv_cc_ebi23:
vdda_qrefs_0p875_5:
vdda_sp_sensor:
vdda_ufs_2ln_core_1:
vdda_ufs_2ln_core_2:
vdda_usb_ss_dp_core_1:
vdda_usb_ss_dp_core_2:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vreg_l5a_0p875: ldo5 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a_1p2: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_10:
vreg_l9a_1p2: ldo9 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a_2p5: ldo10 {
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_0p8: ldo11 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_qfprom:
vdd_qfprom_sp:
vdda_apc_cs_1p8:
vdda_gfx_cs_1p8:
vdda_usb_hs_1p8:
vdda_qrefs_vref_1p8:
vddpx_10_a:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a_2p7: ldo13 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a_1p8: ldo14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p7: ldo15 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <1704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a_2p7: ldo16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a_3p0: ldo17 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8150l-rpmh-regulators {
compatible = "qcom,pm8150l-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-l1-l8-supply = <&vreg_s4a_1p8>;
vdd-l2-l3-supply = <&vreg_s8c_1p3>;
vdd-l4-l5-l6-supply = <&vreg_bob>;
vdd-l7-l11-supply = <&vreg_bob>;
vdd-l9-l10-supply = <&vreg_bob>;
vdd-bob-supply = <&vph_pwr>;
vdd-flash-supply = <&vreg_bob>;
vdd-rgb-supply = <&vreg_bob>;
vreg_bob: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <4000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-allow-bypass;
};
vreg_s8c_1p3: smps8 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_wcss_adcdac_1:
vdda_wcss_adcdac_22:
vreg_l2c_1p3: ldo2 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_hv_ebi0:
vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_hv_refgen0:
vdda_qlink_hv_ck:
vreg_l3c_1p2: ldo3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_5:
vreg_l4c_1p8: ldo4 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_6:
vreg_l5c_1p8: ldo5 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l6c_2p9: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p9: ldo9 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_3p3: ldo10 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_3p3: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8009-rpmh-regulators {
compatible = "qcom,pm8009-rpmh-regulators";
qcom,pmic-id = "f";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vreg_bob>;
vdd-l2-supply = <&vreg_s8c_1p3>;
vdd-l5-l6-supply = <&vreg_bob>;
vreg_l2f_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5f_2p85: ldo5 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6f_2p85: ldo6 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <2856000>;
};
};
};
&qupv3_id_1 {
status = "okay";
};
&pon {
pwrkey {
status = "okay";
};
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&tlmm {
gpio-reserved-ranges = <0 4>, <126 4>;
};
&uart2 {
status = "okay";
};
arch/arm64/boot/dts/qcom/sm8150.dtsi 0 → 100644
View file @ 3563b783
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <38400000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo485";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
};
firmware {
scm: scm {
compatible = "qcom,scm-sm8150", "qcom,scm";
#reset-cells = <1>;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: memory@85700000 {
reg = <0x0 0x85700000 0x0 0x600000>;
no-map;
};
xbl_mem: memory@85d00000 {
reg = <0x0 0x85d00000 0x0 0x140000>;
no-map;
};
aop_mem: memory@85f00000 {
reg = <0x0 0x85f00000 0x0 0x20000>;
no-map;
};
aop_cmd_db: memory@85f20000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85f20000 0x0 0x20000>;
no-map;
};
smem_mem: memory@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
tz_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x3900000>;
no-map;
};
rmtfs_mem: memory@89b00000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x89b00000 0x0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
camera_mem: memory@8b700000 {
reg = <0x0 0x8b700000 0x0 0x500000>;
no-map;
};
wlan_mem: memory@8bc00000 {
reg = <0x0 0x8bc00000 0x0 0x180000>;
no-map;
};
npu_mem: memory@8bd80000 {
reg = <0x0 0x8bd80000 0x0 0x80000>;
no-map;
};
adsp_mem: memory@8be00000 {
reg = <0x0 0x8be00000 0x0 0x1a00000>;
no-map;
};
mpss_mem: memory@8d800000 {
reg = <0x0 0x8d800000 0x0 0x9600000>;
no-map;
};
venus_mem: memory@96e00000 {
reg = <0x0 0x96e00000 0x0 0x500000>;
no-map;
};
slpi_mem: memory@97300000 {
reg = <0x0 0x97300000 0x0 0x1400000>;
no-map;
};
ipa_fw_mem: memory@98700000 {
reg = <0x0 0x98700000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: memory@98710000 {
reg = <0x0 0x98710000 0x0 0x5000>;
no-map;
};
gpu_mem: memory@98715000 {
reg = <0x0 0x98715000 0x0 0x2000>;
no-map;
};
spss_mem: memory@98800000 {
reg = <0x0 0x98800000 0x0 0x100000>;
no-map;
};
cdsp_mem: memory@98900000 {
reg = <0x0 0x98900000 0x0 0x1400000>;
no-map;
};
qseecom_mem: memory@9e400000 {
reg = <0x0 0x9e400000 0x0 0x1400000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sm8150";
reg = <0x0 0x00100000 0x0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "bi_tcxo",
"sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 123>,
<&gcc 124>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc 105>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x0 0x01f40000 0x0 0x40000>;
};
tlmm: pinctrl@3100000 {
compatible = "qcom,sm8150-pinctrl";
reg = <0x0 0x03100000 0x0 0x300000>,
<0x0 0x03500000 0x0 0x300000>,
<0x0 0x03900000 0x0 0x300000>,
<0x0 0x03D00000 0x0 0x300000>;
reg-names = "west", "east", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 175>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x0001100>,
<0x0 0x0c600000 0x0 0x2000000>,
<0x0 0x0e600000 0x0 0x0100000>,
<0x0 0x0e700000 0x0 0x00a0000>,
<0x0 0x0c40a000 0x0 0x0026000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sm8150-apss-shared";
reg = <0x0 0x17c00000 0x0 0x1000>;
#mbox-cells = <1>;
};
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
clock-frequency = <19200000>;
frame@17c21000{
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c21000 0x0 0x1000>,
<0x0 0x17c22000 0x0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c23000 0x0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c25000 0x0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c26000 0x0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c29000 0x0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2b000 0x0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2d000 0x0 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
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