Commit 357513c0 authored by Niravkumar L Rabara's avatar Niravkumar L Rabara Committed by Dinh Nguyen

arm64: dts: altera: socfpga_stratix10: move clocks out of soc node

The clocks are not part of the SoC but provided on the board
(external oscillators). Moving them out of soc node.
Signed-off-by: default avatarNiravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 2b59af8c
...@@ -97,28 +97,6 @@ intc: interrupt-controller@fffc1000 { ...@@ -97,28 +97,6 @@ intc: interrupt-controller@fffc1000 {
<0x0 0xfffc6000 0x0 0x2000>; <0x0 0xfffc6000 0x0 0x2000>;
}; };
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
base_fpga_region {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};
clocks { clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -147,6 +125,28 @@ qspi_clk: qspi-clk { ...@@ -147,6 +125,28 @@ qspi_clk: qspi-clk {
}; };
}; };
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
base_fpga_region {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "fpga-region";
fpga-mgr = <&fpga_mgr>;
};
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};
gmac0: ethernet@ff800000 { gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>; reg = <0xff800000 0x2000>;
......
...@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref { ...@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
}; };
soc { soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
eccmgr { eccmgr {
sdmmca-ecc@ff8c8c00 { sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc", compatible = "altr,socfpga-s10-sdmmc-ecc",
...@@ -113,6 +107,10 @@ &mmc { ...@@ -113,6 +107,10 @@ &mmc {
bus-width = <4>; bus-width = <4>;
}; };
&osc1 {
clock-frequency = <25000000>;
};
&uart0 { &uart0 {
status = "okay"; status = "okay";
}; };
......
...@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref { ...@@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
}; };
soc { soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
eccmgr { eccmgr {
sdmmca-ecc@ff8c8c00 { sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc", compatible = "altr,socfpga-s10-sdmmc-ecc",
...@@ -126,6 +120,10 @@ partition@200000 { ...@@ -126,6 +120,10 @@ partition@200000 {
}; };
}; };
&osc1 {
clock-frequency = <25000000>;
};
&uart0 { &uart0 {
status = "okay"; status = "okay";
}; };
......
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