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Commit 370c00f9 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv50/disp: initial implementation of the various channel object classes 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 446b05a0
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Inline Side-by-side
Showing with 601 additions and 112 deletions
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
View file @ 370c00f9
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
#define __NV50_DISP_H__ #define __NV50_DISP_H__
#include <core/parent.h> #include <core/parent.h>
#include <core/namedb.h>
#include <core/ramht.h>
#include <engine/dmaobj.h>
#include <engine/disp.h> #include <engine/disp.h>
struct nv50_disp_priv { struct nv50_disp_priv {
...@@ -20,15 +24,45 @@ struct nv50_disp_priv { ...@@ -20,15 +24,45 @@ struct nv50_disp_priv {
struct nv50_disp_base { struct nv50_disp_base {
struct nouveau_parent base; struct nouveau_parent base;
struct nouveau_ramht *ramht;
u32 chan;
}; };
struct nv50_disp_chan { struct nv50_disp_chan {
struct nouveau_object base; struct nouveau_namedb base;
int chid;
};
int nv50_disp_chan_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, int, void **);
void nv50_disp_chan_destroy(struct nv50_disp_chan *);
u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
#define nv50_disp_chan_init(a) \
nouveau_namedb_init(&(a)->base)
#define nv50_disp_chan_fini(a,b) \
nouveau_namedb_fini(&(a)->base, (b))
int nv50_disp_dmac_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, u32, int, int, void **);
void nv50_disp_dmac_dtor(struct nouveau_object *);
struct nv50_disp_dmac {
struct nv50_disp_chan base;
struct nouveau_dmaobj *pushdma;
u32 push;
};
struct nv50_disp_pioc {
struct nv50_disp_chan base;
}; };
extern struct nouveau_ofuncs nv50_disp_mast_ofuncs; extern struct nouveau_ofuncs nv50_disp_mast_ofuncs;
extern struct nouveau_ofuncs nv50_disp_dmac_ofuncs; extern struct nouveau_ofuncs nv50_disp_sync_ofuncs;
extern struct nouveau_ofuncs nv50_disp_pioc_ofuncs; extern struct nouveau_ofuncs nv50_disp_ovly_ofuncs;
extern struct nouveau_ofuncs nv50_disp_oimm_ofuncs;
extern struct nouveau_ofuncs nv50_disp_curs_ofuncs;
extern struct nouveau_ofuncs nv50_disp_base_ofuncs; extern struct nouveau_ofuncs nv50_disp_base_ofuncs;
extern struct nouveau_oclass nv50_disp_cclass; extern struct nouveau_oclass nv50_disp_cclass;
void nv50_disp_intr(struct nouveau_subdev *); void nv50_disp_intr(struct nouveau_subdev *);
......
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
View file @ 370c00f9
...@@ -25,21 +25,24 @@ ...@@ -25,21 +25,24 @@
#include <engine/software.h> #include <engine/software.h>
#include <engine/disp.h> #include <engine/disp.h>
#include <core/class.h>
#include "nv50.h" #include "nv50.h"
static struct nouveau_oclass static struct nouveau_oclass
nv84_disp_sclass[] = { nv84_disp_sclass[] = {
{ 0x827d, &nv50_disp_mast_ofuncs }, /* master */ { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
{ 0x827c, &nv50_disp_dmac_ofuncs }, /* sync */ { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
{ 0x827e, &nv50_disp_dmac_ofuncs }, /* overlay */ { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
{ 0x827b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
{ 0x827a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv84_disp_base_oclass[] = { nv84_disp_base_oclass[] = {
{ 0x8270, &nv50_disp_base_ofuncs }, { NV84_DISP_CLASS, &nv50_disp_base_ofuncs },
{}
}; };
static int static int
......
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
View file @ 370c00f9
...@@ -25,21 +25,24 @@ ...@@ -25,21 +25,24 @@
#include <engine/software.h> #include <engine/software.h>
#include <engine/disp.h> #include <engine/disp.h>
#include <core/class.h>
#include "nv50.h" #include "nv50.h"
static struct nouveau_oclass static struct nouveau_oclass
nv94_disp_sclass[] = { nv94_disp_sclass[] = {
{ 0x887d, &nv50_disp_mast_ofuncs }, /* master */ { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
{ 0x887c, &nv50_disp_dmac_ofuncs }, /* sync */ { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
{ 0x887e, &nv50_disp_dmac_ofuncs }, /* overlay */ { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
{ 0x887b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
{ 0x887a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv94_disp_base_oclass[] = { nv94_disp_base_oclass[] = {
{ 0x8870, &nv50_disp_base_ofuncs }, { NV94_DISP_CLASS, &nv50_disp_base_ofuncs },
{}
}; };
static int static int
......
drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
View file @ 370c00f9
...@@ -25,21 +25,24 @@ ...@@ -25,21 +25,24 @@
#include <engine/software.h> #include <engine/software.h>
#include <engine/disp.h> #include <engine/disp.h>
#include <core/class.h>
#include "nv50.h" #include "nv50.h"
static struct nouveau_oclass static struct nouveau_oclass
nva0_disp_sclass[] = { nva0_disp_sclass[] = {
{ 0x837d, &nv50_disp_mast_ofuncs }, /* master */ { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
{ 0x837c, &nv50_disp_dmac_ofuncs }, /* sync */ { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
{ 0x837e, &nv50_disp_dmac_ofuncs }, /* overlay */ { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
{ 0x837b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
{ 0x837a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nva0_disp_base_oclass[] = { nva0_disp_base_oclass[] = {
{ 0x8370, &nv50_disp_base_ofuncs }, { NVA0_DISP_CLASS, &nv50_disp_base_ofuncs },
{}
}; };
static int static int
......
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View file @ 370c00f9
...@@ -25,21 +25,24 @@ ...@@ -25,21 +25,24 @@
#include <engine/software.h> #include <engine/software.h>
#include <engine/disp.h> #include <engine/disp.h>
#include <core/class.h>
#include "nv50.h" #include "nv50.h"
static struct nouveau_oclass static struct nouveau_oclass
nva3_disp_sclass[] = { nva3_disp_sclass[] = {
{ 0x857d, &nv50_disp_mast_ofuncs }, /* master */ { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
{ 0x857c, &nv50_disp_dmac_ofuncs }, /* sync */ { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
{ 0x857e, &nv50_disp_dmac_ofuncs }, /* overlay */ { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
{ 0x857b, &nv50_disp_pioc_ofuncs }, /* overlay (pio) */ { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
{ 0x857a, &nv50_disp_pioc_ofuncs }, /* cursor (pio) */ { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nva3_disp_base_oclass[] = { nva3_disp_base_oclass[] = {
{ 0x8570, &nv50_disp_base_ofuncs }, { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs },
{}
}; };
static int static int
......
drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
View file @ 370c00f9
...@@ -48,6 +48,21 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, ...@@ -48,6 +48,21 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
case NV84_CHANNEL_DMA_CLASS: case NV84_CHANNEL_DMA_CLASS:
case NV50_CHANNEL_IND_CLASS: case NV50_CHANNEL_IND_CLASS:
case NV84_CHANNEL_IND_CLASS: case NV84_CHANNEL_IND_CLASS:
case NV50_DISP_MAST_CLASS:
case NV84_DISP_MAST_CLASS:
case NV94_DISP_MAST_CLASS:
case NVA0_DISP_MAST_CLASS:
case NVA3_DISP_MAST_CLASS:
case NV50_DISP_SYNC_CLASS:
case NV84_DISP_SYNC_CLASS:
case NV94_DISP_SYNC_CLASS:
case NVA0_DISP_SYNC_CLASS:
case NVA3_DISP_SYNC_CLASS:
case NV50_DISP_OVLY_CLASS:
case NV84_DISP_OVLY_CLASS:
case NV94_DISP_OVLY_CLASS:
case NVA0_DISP_OVLY_CLASS:
case NVA3_DISP_OVLY_CLASS:
break; break;
default: default:
return -EINVAL; return -EINVAL;
......
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
View file @ 370c00f9
...@@ -45,6 +45,10 @@ nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, ...@@ -45,6 +45,10 @@ nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
switch (nv_mclass(parent->parent)) { switch (nv_mclass(parent->parent)) {
case NVA3_DISP_MAST_CLASS:
case NVA3_DISP_SYNC_CLASS:
case NVA3_DISP_OVLY_CLASS:
break;
default: default:
return -EINVAL; return -EINVAL;
} }
......
drivers/gpu/drm/nouveau/core/include/core/class.h
View file @ 370c00f9
...@@ -153,4 +153,107 @@ struct nve0_channel_ind_class { ...@@ -153,4 +153,107 @@ struct nve0_channel_ind_class {
u32 engine; u32 engine;
}; };
/* 5070: NV50_DISP
* 8270: NV84_DISP
* 8370: NVA0_DISP
* 8870: NV94_DISP
* 8570: NVA3_DISP
*/
#define NV50_DISP_CLASS 0x00005070
#define NV84_DISP_CLASS 0x00008270
#define NVA0_DISP_CLASS 0x00008370
#define NV94_DISP_CLASS 0x00008870
#define NVA3_DISP_CLASS 0x00008570
struct nv50_display_class {
};
/* 507a: NV50_DISP_CURS
* 827a: NV84_DISP_CURS
* 837a: NVA0_DISP_CURS
* 887a: NV94_DISP_CURS
* 857a: NVA3_DISP_CURS
*/
#define NV50_DISP_CURS_CLASS 0x0000507a
#define NV84_DISP_CURS_CLASS 0x0000827a
#define NVA0_DISP_CURS_CLASS 0x0000837a
#define NV94_DISP_CURS_CLASS 0x0000887a
#define NVA3_DISP_CURS_CLASS 0x0000857a
struct nv50_display_curs_class {
u32 head;
};
/* 507b: NV50_DISP_OIMM
* 827b: NV84_DISP_OIMM
* 837b: NVA0_DISP_OIMM
* 887b: NV94_DISP_OIMM
* 857b: NVA3_DISP_OIMM
*/
#define NV50_DISP_OIMM_CLASS 0x0000507b
#define NV84_DISP_OIMM_CLASS 0x0000827b
#define NVA0_DISP_OIMM_CLASS 0x0000837b
#define NV94_DISP_OIMM_CLASS 0x0000887b
#define NVA3_DISP_OIMM_CLASS 0x0000857b
struct nv50_display_oimm_class {
u32 head;
};
/* 507c: NV50_DISP_SYNC
* 827c: NV84_DISP_SYNC
* 837c: NVA0_DISP_SYNC
* 887c: NV94_DISP_SYNC
* 857c: NVA3_DISP_SYNC
*/
#define NV50_DISP_SYNC_CLASS 0x0000507c
#define NV84_DISP_SYNC_CLASS 0x0000827c
#define NVA0_DISP_SYNC_CLASS 0x0000837c
#define NV94_DISP_SYNC_CLASS 0x0000887c
#define NVA3_DISP_SYNC_CLASS 0x0000857c
struct nv50_display_sync_class {
u32 pushbuf;
u32 head;
};
/* 507d: NV50_DISP_MAST
* 827d: NV84_DISP_MAST
* 837d: NVA0_DISP_MAST
* 887d: NV94_DISP_MAST
* 857d: NVA3_DISP_MAST
*/
#define NV50_DISP_MAST_CLASS 0x0000507d
#define NV84_DISP_MAST_CLASS 0x0000827d
#define NVA0_DISP_MAST_CLASS 0x0000837d
#define NV94_DISP_MAST_CLASS 0x0000887d
#define NVA3_DISP_MAST_CLASS 0x0000857d
struct nv50_display_mast_class {
u32 pushbuf;
};
/* 507e: NV50_DISP_OVLY
* 827e: NV84_DISP_OVLY
* 837e: NVA0_DISP_OVLY
* 887e: NV94_DISP_OVLY
* 857e: NVA3_DISP_OVLY
*/
#define NV50_DISP_OVLY_CLASS 0x0000507e
#define NV84_DISP_OVLY_CLASS 0x0000827e
#define NVA0_DISP_OVLY_CLASS 0x0000837e
#define NV94_DISP_OVLY_CLASS 0x0000887e
#define NVA3_DISP_OVLY_CLASS 0x0000857e
struct nv50_display_ovly_class {
u32 pushbuf;
u32 head;
};
#endif #endif
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