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Commit 37eceb69 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'samsung-clk-6.1' of... 

Merge tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driverd updates from Krzysztof Kozlowski:

 - Exynos7885: add FSYS, TREX and MFC clock controllers.
 - Exynos850: add IS and AUD (audio) clock controllers with bindings.
 - ExynosAutov9: add FSYS clock controllers with bindings.
 - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
   controllers, due to duplicated entries.  This is an acceptable ABI
   break: recently developed/added platform so without legacies, acked
   by known users/developers.
 - ExynosAutov9: add few missing Peric 0/1 gates.
 - ExynosAutov9: correct register offsets of few Peric 0/1 clocks.
 - Minor code improvements (use of_device_get_match_data() helper, code
   style).
 - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
   already maintainers that architecture/platform.

* tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
  clk: samsung: exynos850: Implement CMU_MFCMSCL domain
  clk: samsung: exynos850: Implement CMU_IS domain
  clk: samsung: exynos850: Implement CMU_AUD domain
  clk: samsung: exynos850: Style fixes
  clk: samsung: exynosautov9: add fsys1 clock support
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: correct register offsets of peric0/c1
  clk: samsung: exynosautov9: add missing gate clks for peric0/c1
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  clk: samsung: exynos7885: Add TREX clocks
  clk: samsung: exynos7885: Implement CMU_FSYS domain
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
  clk: samsung: exynos-clkout: Use of_device_get_match_data()
parents 568035b0 ef96c458
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Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
View file @ 37eceb69
......@@ -33,10 +33,13 @@ properties:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-apm
- samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-is
- samsung,exynos850-cmu-mfcmscl
- samsung,exynos850-cmu-peri
clocks:
......@@ -88,6 +91,24 @@ allOf:
- const: oscclk
- const: dout_clkcmu_apm_bus
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-aud
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: AUD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_aud
- if:
properties:
compatible:
......@@ -172,6 +193,54 @@ allOf:
- const: dout_hsi_mmc_card
- const: dout_hsi_usb20drd
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-is
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_IS bus clock (from CMU_TOP)
- description: Image Texture Processing core clock (from CMU_TOP)
- description: Visual Recognition Accelerator clock (from CMU_TOP)
- description: Geometric Distortion Correction clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_is_bus
- const: dout_is_itp
- const: dout_is_vra
- const: dout_is_gdc
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-mfcmscl
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: Multi-Format Codec clock (from CMU_TOP)
- description: Memory to Memory Scaler clock (from CMU_TOP)
- description: Multi-Channel Scaler clock (from CMU_TOP)
- description: JPEG codec clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_mfcmscl_mfc
- const: dout_mfcmscl_m2m
- const: dout_mfcmscl_mcsc
- const: dout_mfcmscl_jpeg
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
View file @ 37eceb69
......@@ -35,6 +35,8 @@ properties:
- samsung,exynosautov9-cmu-top
- samsung,exynosautov9-cmu-busmc
- samsung,exynosautov9-cmu-core
- samsung,exynosautov9-cmu-fsys0
- samsung,exynosautov9-cmu-fsys1
- samsung,exynosautov9-cmu-fsys2
- samsung,exynosautov9-cmu-peric0
- samsung,exynosautov9-cmu-peric1
......@@ -107,6 +109,48 @@ allOf:
- const: oscclk
- const: dout_clkcmu_core_bus
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-fsys0
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS0 bus clock (from CMU_TOP)
- description: CMU_FSYS0 pcie clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_fsys0_bus
- const: dout_clkcmu_fsys0_pcie
- if:
properties:
compatible:
contains:
const: samsung,exynosautov9-cmu-fsys1
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_FSYS1 bus clock (from CMU_TOP)
- description: CMU_FSYS1 mmc card clock (from CMU_TOP)
- description: CMU_FSYS1 usb clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_clkcmu_fsys1_bus
- const: dout_clkcmu_fsys1_mmc_card
- const: dout_clkcmu_fsys1_usbdrd
- if:
properties:
compatible:
......
MAINTAINERS
View file @ 37eceb69
......@@ -18022,12 +18022,14 @@ Q: https://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/platform/samsung/exynos4-is/
SAMSUNG SOC CLOCK DRIVERS
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
M: Tomasz Figa <tomasz.figa@gmail.com>
M: Chanwoo Choi <cw00.choi@samsung.com>
R: Alim Akhtar <alim.akhtar@samsung.com>
L: linux-samsung-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
......
drivers/clk/samsung/clk-exynos-clkout.c
View file @ 37eceb69
......@@ -81,19 +81,17 @@ MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)
{
const struct exynos_clkout_variant *variant;
const struct of_device_id *match;
if (!dev->parent) {
dev_err(dev, "not instantiated from MFD\n");
return -EINVAL;
}
match = of_match_device(exynos_clkout_ids, dev->parent);
if (!match) {
variant = of_device_get_match_data(dev->parent);
if (!variant) {
dev_err(dev, "cannot match parent device\n");
return -EINVAL;
}
variant = match->data;
*mux_mask = variant->mux_mask;
......
drivers/clk/samsung/clk-exynos7885.c
View file @ 37eceb69
......@@ -27,6 +27,11 @@
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
......@@ -39,6 +44,11 @@
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c
#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850
#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
......@@ -59,6 +69,11 @@
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050
#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
......@@ -76,6 +91,11 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
......@@ -88,6 +108,11 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_G3D,
CLK_CON_DIV_CLKCMU_FSYS_BUS,
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_SPI0,
CLK_CON_DIV_CLKCMU_PERI_SPI1,
......@@ -108,6 +133,11 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
......@@ -146,6 +176,13 @@ PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */
PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
/* CORE */
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
......@@ -174,6 +211,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
/* FSYS */
MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),
MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),
MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,
CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),
};
static const struct samsung_div_clock top_div_clks[] __initconst = {
......@@ -220,6 +269,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
/* FSYS */
DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",
CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),
DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",
CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),
DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",
CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),
DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",
CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),
DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",
CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),
};
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
......@@ -250,6 +311,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
/* FSYS */
GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",
CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),
GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",
CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),
GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",
CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),
};
static const struct samsung_cmu_info top_cmu_info __initconst = {
......@@ -498,13 +571,20 @@ CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
/* ---- CMU_CORE ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CORE (0x12000000) */
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160
#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170
#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174
static const unsigned long core_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
......@@ -514,6 +594,13 @@ static const unsigned long core_clk_regs[] __initconst = {
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK,
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE,
};
/* List of parent clocks for Muxes in CMU_CORE */
......@@ -545,6 +632,27 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = {
/* GIC (interrupt controller) clock must be always running */
GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
/*
* TREX D and P Core (seems to be related to "bus traffic shaper")
* clocks must always be running
*/
GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core",
"mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core",
"mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core",
"dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21,
CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info core_cmu_info __initconst = {
......@@ -560,6 +668,88 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.clk_name = "dout_core_bus",
};
/* ---- CMU_FSYS ------------------------------------------------------------ */
/* Register Offset definitions for CMU_FSYS (0x13400000) */
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
static const unsigned long fsys_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
};
/* List of parent clocks for Muxes in CMU_FSYS */
PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" };
PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),
MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",
mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",
mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
4, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
"mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
"mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.mux_clks = fsys_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = FSYS_NR_CLK,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.clk_name = "dout_fsys_bus",
};
/* ---- platform_driver ----------------------------------------------------- */
static int __init exynos7885_cmu_probe(struct platform_device *pdev)
......@@ -577,6 +767,9 @@ static const struct of_device_id exynos7885_cmu_of_match[] = {
{
.compatible = "samsung,exynos7885-cmu-core",
.data = &core_cmu_info,
}, {
.compatible = "samsung,exynos7885-cmu-fsys",
.data = &fsys_cmu_info,
}, {
},
};
......
drivers/clk/samsung/clk-exynos850.c
View file @ 37eceb69
......@@ -30,6 +30,7 @@
#define PLL_CON0_PLL_SHARED1 0x0180
#define PLL_CON3_PLL_SHARED1 0x018c
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
#define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
......@@ -38,10 +39,19 @@
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
#define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
#define CLK_CON_DIV_CLKCMU_AUD 0x1810
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
......@@ -50,6 +60,14 @@
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
#define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
#define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
#define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
......@@ -60,6 +78,7 @@
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
#define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
......@@ -68,6 +87,14 @@
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
#define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
......@@ -83,6 +110,7 @@ static const unsigned long top_clk_regs[] __initconst = {
PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
CLK_CON_MUX_MUX_CLKCMU_AUD,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
......@@ -91,10 +119,19 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
CLK_CON_DIV_CLKCMU_APM_BUS,
CLK_CON_DIV_CLKCMU_AUD,
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
......@@ -103,6 +140,14 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_HSI_BUS,
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
CLK_CON_DIV_CLKCMU_IS_BUS,
CLK_CON_DIV_CLKCMU_IS_GDC,
CLK_CON_DIV_CLKCMU_IS_ITP,
CLK_CON_DIV_CLKCMU_IS_VRA,
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_IP,
CLK_CON_DIV_CLKCMU_PERI_UART,
......@@ -113,6 +158,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_PLL_SHARED1_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV4,
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
CLK_CON_GAT_GATE_CLKCMU_AUD,
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
......@@ -121,6 +167,14 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
......@@ -148,6 +202,9 @@ PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
"dout_shared1_div2", "dout_shared0_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
......@@ -167,13 +224,30 @@ PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" };
PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
......@@ -191,6 +265,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
/* AUD */
MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
/* CORE */
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
......@@ -213,6 +291,26 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
/* IS */
MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
/* MFCMSCL */
MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
/* PERI */
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
......@@ -241,6 +339,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
/* AUD */
DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
CLK_CON_DIV_CLKCMU_AUD, 0, 4),
/* CORE */
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
......@@ -263,6 +365,26 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
/* IS */
DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
/* MFCMSCL */
DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
/* PERI */
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
......@@ -287,6 +409,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
/* AUD */
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
/* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
......@@ -299,6 +425,28 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
/* IS */
/* TODO: These clocks have to be always enabled to access CMU_IS regs */
GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
/* MFCMSCL */
/* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
/* PERI */
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
......@@ -463,6 +611,284 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.clk_name = "dout_clkcmu_apm_bus",
};
/* ---- CMU_AUD ------------------------------------------------------------- */
#define PLL_LOCKTIME_PLL_AUD 0x0000
#define PLL_CON0_PLL_AUD 0x0100
#define PLL_CON3_PLL_AUD 0x010c
#define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
#define PLL_CON0_MUX_TICK_USB_USER 0x0610
#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
#define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
#define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
#define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
#define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
#define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
#define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
#define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
#define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
#define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
#define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
#define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
#define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
#define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
#define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
static const unsigned long aud_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_AUD,
PLL_CON0_PLL_AUD,
PLL_CON3_PLL_AUD,
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
PLL_CON0_MUX_TICK_USB_USER,
CLK_CON_MUX_MUX_CLK_AUD_CPU,
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
CLK_CON_MUX_MUX_CLK_AUD_FM,
CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
CLK_CON_DIV_DIV_CLK_AUD_MCLK,
CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
CLK_CON_DIV_DIV_CLK_AUD_BUSD,
CLK_CON_DIV_DIV_CLK_AUD_BUSP,
CLK_CON_DIV_DIV_CLK_AUD_CNT,
CLK_CON_DIV_DIV_CLK_AUD_CPU,
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
CLK_CON_DIV_DIV_CLK_AUD_FM,
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
};
/* List of parent clocks for Muxes in CMU_AUD */
PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
/*
* Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
* for that PLL by default, so set_rate operation would fail.
*/
static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
};
static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
};
static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
PLL_CON0_PLL_AUD, 4, 1),
MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
mout_aud_tick_usb_user_p,
PLL_CON0_MUX_TICK_USB_USER, 4, 1),
MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
};
static const struct samsung_div_clock aud_div_clks[] __initconst = {
DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
"mout_aud_cpu_hch",
CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
/* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
};
static const struct samsung_cmu_info aud_cmu_info __initconst = {
.pll_clks = aud_pll_clks,
.nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
.mux_clks = aud_mux_clks,
.nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
.div_clks = aud_div_clks,
.nr_div_clks = ARRAY_SIZE(aud_div_clks),
.gate_clks = aud_gate_clks,
.nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
.fixed_clks = aud_fixed_clks,
.nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
.nr_clk_ids = AUD_NR_CLK,
.clk_regs = aud_clk_regs,
.nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
.clk_name = "dout_aud",
};
/* ---- CMU_CMGP ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CMGP (0x11c00000) */
......@@ -599,7 +1025,7 @@ static const unsigned long hsi_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
};
/* List of parent clocks for Muxes in CMU_PERI */
/* List of parent clocks for Muxes in CMU_HSI */
PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
......@@ -654,6 +1080,247 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
.clk_name = "dout_hsi_bus",
};
/* ---- CMU_IS -------------------------------------------------------------- */
#define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
#define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
#define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
#define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
#define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
#define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
#define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
#define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
#define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
#define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
#define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
#define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
#define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
#define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
static const unsigned long is_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
CLK_CON_DIV_DIV_CLK_IS_BUSP,
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
CLK_CON_GAT_GOUT_IS_CLK_GDC,
CLK_CON_GAT_GOUT_IS_CLK_IPP,
CLK_CON_GAT_GOUT_IS_CLK_ITP,
CLK_CON_GAT_GOUT_IS_CLK_MCSC,
CLK_CON_GAT_GOUT_IS_CLK_VRA,
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_IS */
PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
static const struct samsung_mux_clock is_mux_clks[] __initconst = {
MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
};
static const struct samsung_div_clock is_div_clks[] __initconst = {
DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
};
static const struct samsung_gate_clock is_gate_clks[] __initconst = {
/* TODO: Should be enabled in IS driver */
GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
"mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
"mout_is_bus_user",
CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
"mout_is_itp_user",
CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info is_cmu_info __initconst = {
.mux_clks = is_mux_clks,
.nr_mux_clks = ARRAY_SIZE(is_mux_clks),
.div_clks = is_div_clks,
.nr_div_clks = ARRAY_SIZE(is_div_clks),
.gate_clks = is_gate_clks,
.nr_gate_clks = ARRAY_SIZE(is_gate_clks),
.nr_clk_ids = IS_NR_CLK,
.clk_regs = is_clk_regs,
.nr_clk_regs = ARRAY_SIZE(is_clk_regs),
.clk_name = "dout_is_bus",
};
/* ---- CMU_MFCMSCL --------------------------------------------------------- */
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
#define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
#define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
#define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
#define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
#define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
#define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
#define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
#define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
static const unsigned long mfcmscl_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_MFCMSCL */
PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
mout_mfcmscl_mfc_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
mout_mfcmscl_m2m_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
mout_mfcmscl_mcsc_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
mout_mfcmscl_jpeg_user_p,
PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
};
static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
};
static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
/* TODO: Should be enabled in MFC driver */
GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
"mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
"mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
"mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
"mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
21, 0, 0),
GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
"dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
21, 0, 0),
};
static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
.mux_clks = mfcmscl_mux_clks,
.nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
.div_clks = mfcmscl_div_clks,
.nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
.gate_clks = mfcmscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
.nr_clk_ids = MFCMSCL_NR_CLK,
.clk_regs = mfcmscl_clk_regs,
.nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
.clk_name = "dout_mfcmscl_mfc",
};
/* ---- CMU_PERI ------------------------------------------------------------ */
/* Register Offset definitions for CMU_PERI (0x10030000) */
......@@ -963,7 +1630,7 @@ static const unsigned long dpu_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_CORE */
/* List of parent clocks for Muxes in CMU_DPU */
PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
......@@ -1027,12 +1694,21 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
{
.compatible = "samsung,exynos850-cmu-apm",
.data = &apm_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-aud",
.data = &aud_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-cmgp",
.data = &cmgp_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-hsi",
.data = &hsi_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-is",
.data = &is_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-mfcmscl",
.data = &mfcmscl_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-core",
.data = &core_cmu_info,
......
drivers/clk/samsung/clk-exynosautov9.c
View file @ 37eceb69
......@@ -1067,6 +1067,373 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.clk_name = "dout_clkcmu_core_bus",
};
/* ---- CMU_FSYS0 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17700000) */
#define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
#define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
#define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
static const unsigned long fsys0_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER,
PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
};
/* List of parent clocks for Muxes in CMU_FSYS0 */
PNAME(mout_fsys0_bus_user_p) = { "oscclk", "dout_clkcmu_fsys0_bus" };
PNAME(mout_fsys0_pcie_user_p) = { "oscclk", "dout_clkcmu_fsys0_pcie" };
static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS0_BUS_USER, "mout_fsys0_bus_user",
mout_fsys0_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 4, 1),
MUX(CLK_MOUT_FSYS0_PCIE_USER, "mout_fsys0_pcie_user",
mout_fsys0_pcie_user_p, PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER, 4, 1),
};
static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
GATE(CLK_GOUT_FSYS0_BUS_PCLK, "gout_fsys0_bus_pclk",
"mout_fsys0_bus_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
/* Gen3 2L0 */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK,
"gout_fsys0_pcie_gen3_2l0_x1_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK,
"gout_fsys0_pcie_gen3_2l0_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l0_x1_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l0_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK,
"gout_fsys0_pcie_gen3a_2l0_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK,
"gout_fsys0_pcie_gen3b_2l0_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK,
21, 0, 0),
/* Gen3 2L1 */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK,
"gout_fsys0_pcie_gen3_2l1_x1_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK,
"gout_fsys0_pcie_gen3_2l1_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l1_x1_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_2l1_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK,
"gout_fsys0_pcie_gen3a_2l1_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK,
"gout_fsys0_pcie_gen3b_2l1_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK,
21, 0, 0),
/* Gen3 4L */
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK,
"gout_fsys0_pcie_gen3_4l_x2_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK,
"gout_fsys0_pcie_gen3_4l_x4_refclk", "mout_fsys0_pcie_user",
CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK,
"gout_fsys0_pcie_gen3_4l_x2_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_dbi_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_mstr_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK,
"gout_fsys0_pcie_gen3_4l_x4_slv_aclk", "mout_fsys0_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK,
"gout_fsys0_pcie_gen3a_4l_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK,
"gout_fsys0_pcie_gen3b_4l_clk", "mout_fsys0_pcie_user",
CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK,
21, 0, 0),
};
static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.mux_clks = fsys0_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
.gate_clks = fsys0_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
.nr_clk_ids = FSYS0_NR_CLK,
.clk_regs = fsys0_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
.clk_name = "dout_clkcmu_fsys0_bus",
};
/* ---- CMU_FSYS1 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
#define PLL_LOCKTIME_PLL_MMC 0x0000
#define PLL_CON0_PLL_MMC 0x0100
#define PLL_CON3_PLL_MMC 0x010c
#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
static const unsigned long fsys1_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
};
static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
};
/* List of parent clocks for Muxes in CMU_FSYS1 */
PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
PNAME(mout_fsys1_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user",
"mout_fsys1_mmc_pll" };
static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
MUX(CLK_MOUT_FSYS1_MMC_PLL, "mout_fsys1_mmc_pll", mout_fsys1_mmc_pll_p,
PLL_CON0_PLL_MMC, 4, 1),
MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
4, 1),
MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
4, 1),
MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
0, 1),
};
static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
"mout_fsys1_mmc_card",
CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
};
static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
"dout_fsys1_mmc_card",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
"dout_fsys1_mmc_card",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
21, 0, 0),
GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
"mout_fsys1_usbdrd_user",
CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
21, 0, 0),
};
static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.pll_clks = fsys1_pll_clks,
.nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
.mux_clks = fsys1_mux_clks,
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
.div_clks = fsys1_div_clks,
.nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
.gate_clks = fsys1_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
.nr_clk_ids = FSYS1_NR_CLK,
.clk_regs = fsys1_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
.clk_name = "dout_clkcmu_fsys1_bus",
};
/* ---- CMU_FSYS2 ---------------------------------------------------------- */
/* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
......@@ -1170,9 +1537,9 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
......@@ -1330,6 +1697,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
......@@ -1418,14 +1789,14 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
......@@ -1463,9 +1834,9 @@ static const unsigned long peric1_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
......@@ -1581,6 +1952,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
......@@ -1701,6 +2076,12 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-core",
.data = &core_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys0",
.data = &fsys0_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys1",
.data = &fsys1_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-fsys2",
.data = &fsys2_cmu_info,
......
include/dt-bindings/clock/exynos850.h
View file @ 37eceb69
......@@ -58,7 +58,34 @@
#define CLK_MOUT_CLKCMU_APM_BUS 46
#define CLK_DOUT_CLKCMU_APM_BUS 47
#define CLK_GOUT_CLKCMU_APM_BUS 48
#define TOP_NR_CLK 49
#define CLK_MOUT_AUD 49
#define CLK_GOUT_AUD 50
#define CLK_DOUT_AUD 51
#define CLK_MOUT_IS_BUS 52
#define CLK_MOUT_IS_ITP 53
#define CLK_MOUT_IS_VRA 54
#define CLK_MOUT_IS_GDC 55
#define CLK_GOUT_IS_BUS 56
#define CLK_GOUT_IS_ITP 57
#define CLK_GOUT_IS_VRA 58
#define CLK_GOUT_IS_GDC 59
#define CLK_DOUT_IS_BUS 60
#define CLK_DOUT_IS_ITP 61
#define CLK_DOUT_IS_VRA 62
#define CLK_DOUT_IS_GDC 63
#define CLK_MOUT_MFCMSCL_MFC 64
#define CLK_MOUT_MFCMSCL_M2M 65
#define CLK_MOUT_MFCMSCL_MCSC 66
#define CLK_MOUT_MFCMSCL_JPEG 67
#define CLK_GOUT_MFCMSCL_MFC 68
#define CLK_GOUT_MFCMSCL_M2M 69
#define CLK_GOUT_MFCMSCL_MCSC 70
#define CLK_GOUT_MFCMSCL_JPEG 71
#define CLK_DOUT_MFCMSCL_MFC 72
#define CLK_DOUT_MFCMSCL_M2M 73
#define CLK_DOUT_MFCMSCL_MCSC 74
#define CLK_DOUT_MFCMSCL_JPEG 75
#define TOP_NR_CLK 76
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
......@@ -87,6 +114,69 @@
#define CLK_GOUT_SYSREG_APM_PCLK 24
#define APM_NR_CLK 25
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
#define CLK_DOUT_AUD_BUSD 2
#define CLK_DOUT_AUD_BUSP 3
#define CLK_DOUT_AUD_CNT 4
#define CLK_DOUT_AUD_CPU 5
#define CLK_DOUT_AUD_CPU_ACLK 6
#define CLK_DOUT_AUD_CPU_PCLKDBG 7
#define CLK_DOUT_AUD_FM 8
#define CLK_DOUT_AUD_FM_SPDY 9
#define CLK_DOUT_AUD_MCLK 10
#define CLK_DOUT_AUD_UAIF0 11
#define CLK_DOUT_AUD_UAIF1 12
#define CLK_DOUT_AUD_UAIF2 13
#define CLK_DOUT_AUD_UAIF3 14
#define CLK_DOUT_AUD_UAIF4 15
#define CLK_DOUT_AUD_UAIF5 16
#define CLK_DOUT_AUD_UAIF6 17
#define CLK_FOUT_AUD_PLL 18
#define CLK_GOUT_AUD_ABOX_ACLK 19
#define CLK_GOUT_AUD_ASB_CCLK 20
#define CLK_GOUT_AUD_CA32_CCLK 21
#define CLK_GOUT_AUD_CNT_BCLK 22
#define CLK_GOUT_AUD_CODEC_MCLK 23
#define CLK_GOUT_AUD_DAP_CCLK 24
#define CLK_GOUT_AUD_GPIO_PCLK 25
#define CLK_GOUT_AUD_PPMU_ACLK 26
#define CLK_GOUT_AUD_PPMU_PCLK 27
#define CLK_GOUT_AUD_SPDY_BCLK 28
#define CLK_GOUT_AUD_SYSMMU_CLK 29
#define CLK_GOUT_AUD_SYSREG_PCLK 30
#define CLK_GOUT_AUD_TZPC_PCLK 31
#define CLK_GOUT_AUD_UAIF0_BCLK 32
#define CLK_GOUT_AUD_UAIF1_BCLK 33
#define CLK_GOUT_AUD_UAIF2_BCLK 34
#define CLK_GOUT_AUD_UAIF3_BCLK 35
#define CLK_GOUT_AUD_UAIF4_BCLK 36
#define CLK_GOUT_AUD_UAIF5_BCLK 37
#define CLK_GOUT_AUD_UAIF6_BCLK 38
#define CLK_GOUT_AUD_WDT_PCLK 39
#define CLK_MOUT_AUD_CPU 40
#define CLK_MOUT_AUD_CPU_HCH 41
#define CLK_MOUT_AUD_CPU_USER 42
#define CLK_MOUT_AUD_FM 43
#define CLK_MOUT_AUD_PLL 44
#define CLK_MOUT_AUD_TICK_USB_USER 45
#define CLK_MOUT_AUD_UAIF0 46
#define CLK_MOUT_AUD_UAIF1 47
#define CLK_MOUT_AUD_UAIF2 48
#define CLK_MOUT_AUD_UAIF3 49
#define CLK_MOUT_AUD_UAIF4 50
#define CLK_MOUT_AUD_UAIF5 51
#define CLK_MOUT_AUD_UAIF6 52
#define IOCLK_AUDIOCDCLK0 53
#define IOCLK_AUDIOCDCLK1 54
#define IOCLK_AUDIOCDCLK2 55
#define IOCLK_AUDIOCDCLK3 56
#define IOCLK_AUDIOCDCLK4 57
#define IOCLK_AUDIOCDCLK5 58
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
#define AUD_NR_CLK 61
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
#define CLK_MOUT_CMGP_ADC 2
......@@ -121,6 +211,50 @@
#define CLK_GOUT_SYSREG_HSI_PCLK 13
#define HSI_NR_CLK 14
/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1
#define CLK_MOUT_IS_ITP_USER 2
#define CLK_MOUT_IS_VRA_USER 3
#define CLK_MOUT_IS_GDC_USER 4
#define CLK_DOUT_IS_BUSP 5
#define CLK_GOUT_IS_CMU_IS_PCLK 6
#define CLK_GOUT_IS_CSIS0_ACLK 7
#define CLK_GOUT_IS_CSIS1_ACLK 8
#define CLK_GOUT_IS_CSIS2_ACLK 9
#define CLK_GOUT_IS_TZPC_PCLK 10
#define CLK_GOUT_IS_CSIS_DMA_CLK 11
#define CLK_GOUT_IS_GDC_CLK 12
#define CLK_GOUT_IS_IPP_CLK 13
#define CLK_GOUT_IS_ITP_CLK 14
#define CLK_GOUT_IS_MCSC_CLK 15
#define CLK_GOUT_IS_VRA_CLK 16
#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
#define CLK_GOUT_IS_SYSREG_PCLK 23
#define IS_NR_CLK 24
/* CMU_MFCMSCL */
#define CLK_MOUT_MFCMSCL_MFC_USER 1
#define CLK_MOUT_MFCMSCL_M2M_USER 2
#define CLK_MOUT_MFCMSCL_MCSC_USER 3
#define CLK_MOUT_MFCMSCL_JPEG_USER 4
#define CLK_DOUT_MFCMSCL_BUSP 5
#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
#define MFCMSCL_NR_CLK 16
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
#define CLK_MOUT_PERI_UART_USER 2
......
include/dt-bindings/clock/samsung,exynosautov9.h
View file @ 37eceb69
......@@ -185,6 +185,74 @@
#define CORE_NR_CLK 6
/* CMU_FSYS0 */
#define CLK_MOUT_FSYS0_BUS_USER 1
#define CLK_MOUT_FSYS0_PCIE_USER 2
#define CLK_GOUT_FSYS0_BUS_PCLK 3
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12
#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13
#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22
#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23
#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24
#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33
#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34
#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35
#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36
#define FSYS0_NR_CLK 37
/* CMU_FSYS1 */
#define FOUT_MMC_PLL 1
#define CLK_MOUT_FSYS1_BUS_USER 2
#define CLK_MOUT_FSYS1_MMC_PLL 3
#define CLK_MOUT_FSYS1_MMC_CARD_USER 4
#define CLK_MOUT_FSYS1_USBDRD_USER 5
#define CLK_MOUT_FSYS1_MMC_CARD 6
#define CLK_DOUT_FSYS1_MMC_CARD 7
#define CLK_GOUT_FSYS1_PCLK 8
#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9
#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10
#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11
#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12
#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13
#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14
#define CLK_GOUT_FSYS1_USB20_0_ACLK 15
#define CLK_GOUT_FSYS1_USB20_1_ACLK 16
#define CLK_GOUT_FSYS1_USB30_0_ACLK 17
#define CLK_GOUT_FSYS1_USB30_1_ACLK 18
#define FSYS1_NR_CLK 19
/* CMU_FSYS2 */
#define CLK_MOUT_FSYS2_BUS_USER 1
#define CLK_MOUT_FSYS2_UFS_EMBD_USER 2
......@@ -226,21 +294,21 @@
#define CLK_GOUT_PERIC0_IPCLK_8 28
#define CLK_GOUT_PERIC0_IPCLK_9 29
#define CLK_GOUT_PERIC0_IPCLK_10 30
#define CLK_GOUT_PERIC0_IPCLK_11 30
#define CLK_GOUT_PERIC0_PCLK_0 31
#define CLK_GOUT_PERIC0_PCLK_1 32
#define CLK_GOUT_PERIC0_PCLK_2 33
#define CLK_GOUT_PERIC0_PCLK_3 34
#define CLK_GOUT_PERIC0_PCLK_4 35
#define CLK_GOUT_PERIC0_PCLK_5 36
#define CLK_GOUT_PERIC0_PCLK_6 37
#define CLK_GOUT_PERIC0_PCLK_7 38
#define CLK_GOUT_PERIC0_PCLK_8 39
#define CLK_GOUT_PERIC0_PCLK_9 40
#define CLK_GOUT_PERIC0_PCLK_10 41
#define CLK_GOUT_PERIC0_PCLK_11 42
#define PERIC0_NR_CLK 43
#define CLK_GOUT_PERIC0_IPCLK_11 31
#define CLK_GOUT_PERIC0_PCLK_0 32
#define CLK_GOUT_PERIC0_PCLK_1 33
#define CLK_GOUT_PERIC0_PCLK_2 34
#define CLK_GOUT_PERIC0_PCLK_3 35
#define CLK_GOUT_PERIC0_PCLK_4 36
#define CLK_GOUT_PERIC0_PCLK_5 37
#define CLK_GOUT_PERIC0_PCLK_6 38
#define CLK_GOUT_PERIC0_PCLK_7 39
#define CLK_GOUT_PERIC0_PCLK_8 40
#define CLK_GOUT_PERIC0_PCLK_9 41
#define CLK_GOUT_PERIC0_PCLK_10 42
#define CLK_GOUT_PERIC0_PCLK_11 43
#define PERIC0_NR_CLK 44
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
......@@ -272,21 +340,21 @@
#define CLK_GOUT_PERIC1_IPCLK_8 28
#define CLK_GOUT_PERIC1_IPCLK_9 29
#define CLK_GOUT_PERIC1_IPCLK_10 30
#define CLK_GOUT_PERIC1_IPCLK_11 30
#define CLK_GOUT_PERIC1_PCLK_0 31
#define CLK_GOUT_PERIC1_PCLK_1 32
#define CLK_GOUT_PERIC1_PCLK_2 33
#define CLK_GOUT_PERIC1_PCLK_3 34
#define CLK_GOUT_PERIC1_PCLK_4 35
#define CLK_GOUT_PERIC1_PCLK_5 36
#define CLK_GOUT_PERIC1_PCLK_6 37
#define CLK_GOUT_PERIC1_PCLK_7 38
#define CLK_GOUT_PERIC1_PCLK_8 39
#define CLK_GOUT_PERIC1_PCLK_9 40
#define CLK_GOUT_PERIC1_PCLK_10 41
#define CLK_GOUT_PERIC1_PCLK_11 42
#define PERIC1_NR_CLK 43
#define CLK_GOUT_PERIC1_IPCLK_11 31
#define CLK_GOUT_PERIC1_PCLK_0 32
#define CLK_GOUT_PERIC1_PCLK_1 33
#define CLK_GOUT_PERIC1_PCLK_2 34
#define CLK_GOUT_PERIC1_PCLK_3 35
#define CLK_GOUT_PERIC1_PCLK_4 36
#define CLK_GOUT_PERIC1_PCLK_5 37
#define CLK_GOUT_PERIC1_PCLK_6 38
#define CLK_GOUT_PERIC1_PCLK_7 39
#define CLK_GOUT_PERIC1_PCLK_8 40
#define CLK_GOUT_PERIC1_PCLK_9 41
#define CLK_GOUT_PERIC1_PCLK_10 42
#define CLK_GOUT_PERIC1_PCLK_11 43
#define PERIC1_NR_CLK 44
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
......
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