Commit 388d3335 authored by Nat Gurumoorthy's avatar Nat Gurumoorthy Committed by David S. Miller

tg3: Initialize REG_BASE_ADDR at PCI config offset 120 to 0

The new tg3 driver leaves REG_BASE_ADDR (PCI config offset 120)
uninitialized. From power on reset this register may have garbage in it. The
Register Base Address register defines the device local address of a
register. The data pointed to by this location is read or written using
the Register Data register (PCI config offset 128). When REG_BASE_ADDR has
garbage any read or write of Register Data Register (PCI 128) will cause the
PCI bus to lock up. The TCO watchdog will fire and bring down the system.
Signed-off-by: default avatarNat Gurumoorthy <natg@google.com>
Acked-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bbd37626
...@@ -16503,6 +16503,9 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) ...@@ -16503,6 +16503,9 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
/* Clear this out for sanity. */ /* Clear this out for sanity. */
tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
/* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
tw32(TG3PCI_REG_BASE_ADDR, 0);
pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
&pci_state_reg); &pci_state_reg);
if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
......
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