Commit 39bccfd1 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman

powerpc/32: replace MTMSRD() by mtmsr

On PPC32, MTMSRD() is simply defined as mtmsr.

Replace MTMSRD(reg) by mtmsr reg in files dedicated to PPC32,
this makes the code less obscure.
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/22469e78230edea3dbd0c79a555d73124f6c6d93.1576916812.git.christophe.leroy@c-s.fr
parent 414f5043
...@@ -397,7 +397,7 @@ ret_from_syscall: ...@@ -397,7 +397,7 @@ ret_from_syscall:
LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */ LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */
/* Note: We don't bother telling lockdep about it */ /* Note: We don't bother telling lockdep about it */
SYNC SYNC
MTMSRD(r10) mtmsr r10
lwz r9,TI_FLAGS(r2) lwz r9,TI_FLAGS(r2)
li r8,-MAX_ERRNO li r8,-MAX_ERRNO
andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
...@@ -554,7 +554,7 @@ syscall_exit_work: ...@@ -554,7 +554,7 @@ syscall_exit_work:
*/ */
ori r10,r10,MSR_EE ori r10,r10,MSR_EE
SYNC SYNC
MTMSRD(r10) mtmsr r10
/* Save NVGPRS if they're not saved already */ /* Save NVGPRS if they're not saved already */
lwz r4,_TRAP(r1) lwz r4,_TRAP(r1)
...@@ -697,7 +697,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE) ...@@ -697,7 +697,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE)
and. r0,r0,r11 /* FP or altivec or SPE enabled? */ and. r0,r0,r11 /* FP or altivec or SPE enabled? */
beq+ 1f beq+ 1f
andc r11,r11,r0 andc r11,r11,r0
MTMSRD(r11) mtmsr r11
isync isync
1: stw r11,_MSR(r1) 1: stw r11,_MSR(r1)
mfcr r10 mfcr r10
...@@ -831,7 +831,7 @@ ret_from_except: ...@@ -831,7 +831,7 @@ ret_from_except:
/* Note: We don't bother telling lockdep about it */ /* Note: We don't bother telling lockdep about it */
LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
SYNC /* Some chip revs have problems here... */ SYNC /* Some chip revs have problems here... */
MTMSRD(r10) /* disable interrupts */ mtmsr r10 /* disable interrupts */
lwz r3,_MSR(r1) /* Returning to user mode? */ lwz r3,_MSR(r1) /* Returning to user mode? */
andi. r0,r3,MSR_PR andi. r0,r3,MSR_PR
...@@ -998,7 +998,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) ...@@ -998,7 +998,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
*/ */
LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI) LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
SYNC SYNC
MTMSRD(r10) /* clear the RI bit */ mtmsr r10 /* clear the RI bit */
.globl exc_exit_restart .globl exc_exit_restart
exc_exit_restart: exc_exit_restart:
lwz r12,_NIP(r1) lwz r12,_NIP(r1)
...@@ -1234,7 +1234,7 @@ do_resched: /* r10 contains MSR_KERNEL here */ ...@@ -1234,7 +1234,7 @@ do_resched: /* r10 contains MSR_KERNEL here */
#endif #endif
ori r10,r10,MSR_EE ori r10,r10,MSR_EE
SYNC SYNC
MTMSRD(r10) /* hard-enable interrupts */ mtmsr r10 /* hard-enable interrupts */
bl schedule bl schedule
recheck: recheck:
/* Note: And we don't tell it we are disabling them again /* Note: And we don't tell it we are disabling them again
...@@ -1243,7 +1243,7 @@ recheck: ...@@ -1243,7 +1243,7 @@ recheck:
*/ */
LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
SYNC SYNC
MTMSRD(r10) /* disable interrupts */ mtmsr r10 /* disable interrupts */
lwz r9,TI_FLAGS(r2) lwz r9,TI_FLAGS(r2)
andi. r0,r9,_TIF_NEED_RESCHED andi. r0,r9,_TIF_NEED_RESCHED
bne- do_resched bne- do_resched
...@@ -1252,7 +1252,7 @@ recheck: ...@@ -1252,7 +1252,7 @@ recheck:
do_user_signal: /* r10 contains MSR_KERNEL here */ do_user_signal: /* r10 contains MSR_KERNEL here */
ori r10,r10,MSR_EE ori r10,r10,MSR_EE
SYNC SYNC
MTMSRD(r10) /* hard-enable interrupts */ mtmsr r10 /* hard-enable interrupts */
/* save r13-r31 in the exception frame, if not already done */ /* save r13-r31 in the exception frame, if not already done */
lwz r3,_TRAP(r1) lwz r3,_TRAP(r1)
andi. r0,r3,1 andi. r0,r3,1
...@@ -1341,7 +1341,7 @@ _GLOBAL(enter_rtas) ...@@ -1341,7 +1341,7 @@ _GLOBAL(enter_rtas)
stw r9,8(r1) stw r9,8(r1)
LOAD_REG_IMMEDIATE(r0,MSR_KERNEL) LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
SYNC /* disable interrupts so SRR0/1 */ SYNC /* disable interrupts so SRR0/1 */
MTMSRD(r0) /* don't get trashed */ mtmsr r0 /* don't get trashed */
li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
mtlr r6 mtlr r6
stw r7, THREAD + RTAS_SP(r2) stw r7, THREAD + RTAS_SP(r2)
......
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
#else #else
li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */ li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR) /* can take exceptions */
MTMSRD(r10) /* (except for mach check in rtas) */ mtmsr r10 /* (except for mach check in rtas) */
#endif #endif
stw r0,GPR0(r11) stw r0,GPR0(r11)
lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
...@@ -80,7 +80,7 @@ ...@@ -80,7 +80,7 @@
rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */
#else #else
LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */ LOAD_REG_IMMEDIATE(r10, MSR_KERNEL & ~(MSR_IR|MSR_DR)) /* can take exceptions */
MTMSRD(r10) /* (except for mach check in rtas) */ mtmsr r10 /* (except for mach check in rtas) */
#endif #endif
lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ lis r10,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
stw r2,GPR2(r11) stw r2,GPR2(r11)
......
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