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Kirill Smelkov
linux
Commits
3a020b4d
Commit
3a020b4d
authored
Aug 20, 2015
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/nouveau/disp: switch to new-style timer macros
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
6ed5c168
Changes
9
Show whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
127 additions
and
34 deletions
+127
-34
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
+16
-4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
+29
-9
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
+10
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
+10
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
+33
-10
drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
+8
-2
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
+4
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
+4
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
+13
-3
No files found.
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
View file @
3a020b4d
...
...
@@ -54,9 +54,15 @@ nv50_dac_power(NV50_DISP_MTHD_V1)
}
else
return
ret
;
nv_wait
(
disp
,
0x61a004
+
doff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61a004
+
doff
)
&
0x80000000
))
break
;
);
nvkm_mask
(
device
,
0x61a004
+
doff
,
0xc000007f
,
0x80000000
|
stat
);
nv_wait
(
disp
,
0x61a004
+
doff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61a004
+
doff
)
&
0x80000000
))
break
;
);
return
0
;
}
...
...
@@ -82,7 +88,10 @@ nv50_dac_sense(NV50_DISP_MTHD_V1)
return
ret
;
nvkm_mask
(
device
,
0x61a004
+
doff
,
0x807f0000
,
0x80150000
);
nv_wait
(
disp
,
0x61a004
+
doff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61a004
+
doff
)
&
0x80000000
))
break
;
);
nvkm_wr32
(
device
,
0x61a00c
+
doff
,
0x00100000
|
loadval
);
mdelay
(
9
);
...
...
@@ -90,7 +99,10 @@ nv50_dac_sense(NV50_DISP_MTHD_V1)
loadval
=
nvkm_mask
(
device
,
0x61a00c
+
doff
,
0xffffffff
,
0x00000000
);
nvkm_mask
(
device
,
0x61a004
+
doff
,
0x807f0000
,
0x80550000
);
nv_wait
(
disp
,
0x61a004
+
doff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61a004
+
doff
)
&
0x80000000
))
break
;
);
nv_debug
(
disp
,
"DAC%d sense: 0x%08x
\n
"
,
outp
->
or
,
loadval
);
if
(
!
(
loadval
&
0x80000000
))
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c
View file @
3a020b4d
...
...
@@ -115,7 +115,10 @@ gf110_disp_dmac_init(struct nvkm_object *object)
nvkm_wr32
(
device
,
0x610490
+
(
chid
*
0x0010
),
0x00000013
);
/* wait for it to go inactive */
if
(
!
nv_wait
(
disp
,
0x610490
+
(
chid
*
0x10
),
0x80000000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
))
&
0x80000000
))
break
;
)
<
0
)
{
nv_error
(
dmac
,
"init: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
)));
return
-
EBUSY
;
...
...
@@ -135,7 +138,10 @@ gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend)
/* deactivate channel */
nvkm_mask
(
device
,
0x610490
+
(
chid
*
0x0010
),
0x00001010
,
0x00001000
);
nvkm_mask
(
device
,
0x610490
+
(
chid
*
0x0010
),
0x00000003
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610490
+
(
chid
*
0x10
),
0x001e0000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
))
&
0x001e0000
))
break
;
)
<
0
)
{
nv_error
(
dmac
,
"fini: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
)));
if
(
suspend
)
...
...
@@ -317,7 +323,10 @@ gf110_disp_core_init(struct nvkm_object *object)
nvkm_wr32
(
device
,
0x610490
,
0x01000013
);
/* wait for it to go inactive */
if
(
!
nv_wait
(
disp
,
0x610490
,
0x80000000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610490
)
&
0x80000000
))
break
;
)
<
0
)
{
nv_error
(
mast
,
"init: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
));
return
-
EBUSY
;
}
...
...
@@ -335,7 +344,10 @@ gf110_disp_core_fini(struct nvkm_object *object, bool suspend)
/* deactivate channel */
nvkm_mask
(
device
,
0x610490
,
0x00000010
,
0x00000000
);
nvkm_mask
(
device
,
0x610490
,
0x00000003
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610490
,
0x001e0000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610490
)
&
0x001e0000
))
break
;
)
<
0
)
{
nv_error
(
mast
,
"fini: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
));
if
(
suspend
)
return
-
EBUSY
;
...
...
@@ -560,7 +572,11 @@ gf110_disp_pioc_init(struct nvkm_object *object)
/* activate channel */
nvkm_wr32
(
device
,
0x610490
+
(
chid
*
0x10
),
0x00000001
);
if
(
!
nv_wait
(
disp
,
0x610490
+
(
chid
*
0x10
),
0x00030000
,
0x00010000
))
{
if
(
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
));
if
((
tmp
&
0x00030000
)
==
0x00010000
)
break
;
)
<
0
)
{
nv_error
(
pioc
,
"init: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
)));
return
-
EBUSY
;
...
...
@@ -578,7 +594,10 @@ gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend)
int
chid
=
pioc
->
base
.
chid
;
nvkm_mask
(
device
,
0x610490
+
(
chid
*
0x10
),
0x00000001
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610490
+
(
chid
*
0x10
),
0x00030000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
))
&
0x00030000
))
break
;
)
<
0
)
{
nv_error
(
pioc
,
"timeout: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610490
+
(
chid
*
0x10
)));
if
(
suspend
)
...
...
@@ -707,11 +726,12 @@ gf110_disp_main_init(struct nvkm_object *object)
if
(
nvkm_rd32
(
device
,
0x6100ac
)
&
0x00000100
)
{
nvkm_wr32
(
device
,
0x6100ac
,
0x00000100
);
nvkm_mask
(
device
,
0x6194e8
,
0x00000001
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x6194e8
,
0x00000002
,
0x00000000
))
{
nv_error
(
disp
,
"timeout acquiring display
\n
"
);
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x6194e8
)
&
0x00000002
))
break
;
)
<
0
)
return
-
EBUSY
;
}
}
/* point at display engine memory area (hash table, objects) */
nvkm_wr32
(
device
,
0x610010
,
(
nv_gpuobj
(
object
->
parent
)
->
addr
>>
8
)
|
9
);
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c
View file @
3a020b4d
...
...
@@ -54,7 +54,11 @@ gf110_hda_eld(NV50_DISP_MTHD_V1)
if
(
size
&&
args
->
v0
.
data
[
0
])
{
if
(
outp
->
info
.
type
==
DCB_OUTPUT_DP
)
{
nvkm_mask
(
device
,
0x616618
+
hoff
,
0x8000000c
,
0x80000001
);
nv_wait
(
disp
,
0x616618
+
hoff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x616618
+
hoff
);
if
(
!
(
tmp
&
0x80000000
))
break
;
);
}
nvkm_mask
(
device
,
0x616548
+
hoff
,
0x00000070
,
0x00000000
);
for
(
i
=
0
;
i
<
size
;
i
++
)
...
...
@@ -65,7 +69,11 @@ gf110_hda_eld(NV50_DISP_MTHD_V1)
}
else
{
if
(
outp
->
info
.
type
==
DCB_OUTPUT_DP
)
{
nvkm_mask
(
device
,
0x616618
+
hoff
,
0x80000001
,
0x80000000
);
nv_wait
(
disp
,
0x616618
+
hoff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x616618
+
hoff
);
if
(
!
(
tmp
&
0x80000000
))
break
;
);
}
nvkm_mask
(
device
,
0x10ec10
+
soff
,
0x80000003
,
0x80000000
|
!!
size
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c
View file @
3a020b4d
...
...
@@ -51,7 +51,11 @@ gt215_hda_eld(NV50_DISP_MTHD_V1)
if
(
size
&&
args
->
v0
.
data
[
0
])
{
if
(
outp
->
info
.
type
==
DCB_OUTPUT_DP
)
{
nvkm_mask
(
device
,
0x61c1e0
+
soff
,
0x8000000d
,
0x80000001
);
nv_wait
(
disp
,
0x61c1e0
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x61c1e0
+
soff
);
if
(
!
(
tmp
&
0x80000000
))
break
;
);
}
for
(
i
=
0
;
i
<
size
;
i
++
)
nvkm_wr32
(
device
,
0x61c440
+
soff
,
(
i
<<
8
)
|
args
->
v0
.
data
[
0
]);
...
...
@@ -61,7 +65,11 @@ gt215_hda_eld(NV50_DISP_MTHD_V1)
}
else
{
if
(
outp
->
info
.
type
==
DCB_OUTPUT_DP
)
{
nvkm_mask
(
device
,
0x61c1e0
+
soff
,
0x80000001
,
0x80000000
);
nv_wait
(
disp
,
0x61c1e0
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x61c1e0
+
soff
);
if
(
!
(
tmp
&
0x80000000
))
break
;
);
}
nvkm_mask
(
device
,
0x61c448
+
soff
,
0x80000003
,
0x80000000
|
!!
size
);
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View file @
3a020b4d
...
...
@@ -279,7 +279,10 @@ nv50_disp_dmac_init(struct nvkm_object *object)
nvkm_wr32
(
device
,
0x610200
+
(
chid
*
0x0010
),
0x00000013
);
/* wait for it to go inactive */
if
(
!
nv_wait
(
disp
,
0x610200
+
(
chid
*
0x10
),
0x80000000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
))
&
0x80000000
))
break
;
)
<
0
)
{
nv_error
(
dmac
,
"init timeout, 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
)));
return
-
EBUSY
;
...
...
@@ -299,7 +302,10 @@ nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend)
/* deactivate channel */
nvkm_mask
(
device
,
0x610200
+
(
chid
*
0x0010
),
0x00001010
,
0x00001000
);
nvkm_mask
(
device
,
0x610200
+
(
chid
*
0x0010
),
0x00000003
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610200
+
(
chid
*
0x10
),
0x001e0000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
))
&
0x001e0000
))
break
;
)
<
0
)
{
nv_error
(
dmac
,
"fini timeout, 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
)));
if
(
suspend
)
...
...
@@ -547,7 +553,10 @@ nv50_disp_core_init(struct nvkm_object *object)
nvkm_wr32
(
device
,
0x610200
,
0x01000013
);
/* wait for it to go inactive */
if
(
!
nv_wait
(
disp
,
0x610200
,
0x80000000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
)
&
0x80000000
))
break
;
)
<
0
)
{
nv_error
(
mast
,
"init: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
));
return
-
EBUSY
;
}
...
...
@@ -565,7 +574,10 @@ nv50_disp_core_fini(struct nvkm_object *object, bool suspend)
/* deactivate channel */
nvkm_mask
(
device
,
0x610200
,
0x00000010
,
0x00000000
);
nvkm_mask
(
device
,
0x610200
,
0x00000003
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610200
,
0x001e0000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
)
&
0x001e0000
))
break
;
)
<
0
)
{
nv_error
(
mast
,
"fini: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
));
if
(
suspend
)
return
-
EBUSY
;
...
...
@@ -819,14 +831,21 @@ nv50_disp_pioc_init(struct nvkm_object *object)
return
ret
;
nvkm_wr32
(
device
,
0x610200
+
(
chid
*
0x10
),
0x00002000
);
if
(
!
nv_wait
(
disp
,
0x610200
+
(
chid
*
0x10
),
0x00000000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
))
&
0x00030000
))
break
;
)
<
0
)
{
nv_error
(
pioc
,
"timeout0: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
)));
return
-
EBUSY
;
}
nvkm_wr32
(
device
,
0x610200
+
(
chid
*
0x10
),
0x00000001
);
if
(
!
nv_wait
(
disp
,
0x610200
+
(
chid
*
0x10
),
0x00030000
,
0x00010000
))
{
if
(
nvkm_msec
(
device
,
2000
,
u32
tmp
=
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
));
if
((
tmp
&
0x00030000
)
==
0x00010000
)
break
;
)
<
0
)
{
nv_error
(
pioc
,
"timeout1: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
)));
return
-
EBUSY
;
...
...
@@ -844,7 +863,10 @@ nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend)
int
chid
=
pioc
->
base
.
chid
;
nvkm_mask
(
device
,
0x610200
+
(
chid
*
0x10
),
0x00000001
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x610200
+
(
chid
*
0x10
),
0x00030000
,
0x00000000
))
{
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
))
&
0x00030000
))
break
;
)
<
0
)
{
nv_error
(
pioc
,
"timeout: 0x%08x
\n
"
,
nvkm_rd32
(
device
,
0x610200
+
(
chid
*
0x10
)));
if
(
suspend
)
...
...
@@ -1192,11 +1214,12 @@ nv50_disp_main_init(struct nvkm_object *object)
if
(
nvkm_rd32
(
device
,
0x610024
)
&
0x00000100
)
{
nvkm_wr32
(
device
,
0x610024
,
0x00000100
);
nvkm_mask
(
device
,
0x6194e8
,
0x00000001
,
0x00000000
);
if
(
!
nv_wait
(
disp
,
0x6194e8
,
0x00000002
,
0x00000000
))
{
nv_error
(
disp
,
"timeout acquiring display
\n
"
);
if
(
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x6194e8
)
&
0x00000002
))
break
;
)
<
0
)
return
-
EBUSY
;
}
}
/* point at display engine memory area (hash table, objects) */
nvkm_wr32
(
device
,
0x610010
,
(
nv_gpuobj
(
base
->
ramht
)
->
addr
>>
8
)
|
9
);
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
View file @
3a020b4d
...
...
@@ -163,9 +163,15 @@ nv50_pior_power(NV50_DISP_MTHD_V1)
}
else
return
ret
;
nv_wait
(
disp
,
0x61e004
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61e004
+
soff
)
&
0x80000000
))
break
;
);
nvkm_mask
(
device
,
0x61e004
+
soff
,
0x80000101
,
0x80000000
|
ctrl
);
nv_wait
(
disp
,
0x61e004
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61e004
+
soff
)
&
0x80000000
))
break
;
);
disp
->
pior
.
type
[
outp
->
or
]
=
type
;
return
0
;
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
View file @
3a020b4d
...
...
@@ -75,7 +75,10 @@ g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
nvkm_mask
(
device
,
0x61c130
+
loff
,
0x0000000f
,
mask
);
nvkm_mask
(
device
,
0x61c034
+
soff
,
0x80000000
,
0x80000000
);
nv_wait
(
disp
,
0x61c034
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61c034
+
soff
)
&
0x80000000
))
break
;
);
return
0
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c
View file @
3a020b4d
...
...
@@ -85,7 +85,10 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
nvkm_mask
(
device
,
0x61c130
+
loff
,
0x0000000f
,
mask
);
nvkm_mask
(
device
,
0x61c034
+
soff
,
0x80000000
,
0x80000000
);
nv_wait
(
disp
,
0x61c034
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61c034
+
soff
)
&
0x80000000
))
break
;
);
return
0
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c
View file @
3a020b4d
...
...
@@ -49,9 +49,19 @@ nv50_sor_power(NV50_DISP_MTHD_V1)
}
else
return
ret
;
nv_wait
(
disp
,
0x61c004
+
soff
,
0x80000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61c004
+
soff
)
&
0x80000000
))
break
;
);
nvkm_mask
(
device
,
0x61c004
+
soff
,
0x80000001
,
0x80000000
|
stat
);
nv_wait
(
disp
,
0x61c004
+
soff
,
0x80000000
,
0x00000000
);
nv_wait
(
disp
,
0x61c030
+
soff
,
0x10000000
,
0x00000000
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61c004
+
soff
)
&
0x80000000
))
break
;
);
nvkm_msec
(
device
,
2000
,
if
(
!
(
nvkm_rd32
(
device
,
0x61c030
+
soff
)
&
0x10000000
))
break
;
);
return
0
;
}
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