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Commit 3ad349a5 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] NEC DDB update 

This updates the support for NEC's DDB series of evaluation boards.
parent 320bcfc9
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arch/mips/ddb5074/nile4.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/nile4.c -- NEC Vrc-5074 Nile 4 support routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/nile4.h>
/*
* Physical Device Address Registers
*
* Note: 32 bit addressing only!
*/
void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int visible)
{
u32 maskbits;
u32 widthbits;
if (pdar > NILE4_BOOTCS || (pdar & 7)) {
printk("nile4_set_pdar: invalid pdar %d\n", pdar);
return;
}
if (pdar == NILE4_INTCS && size != 0x00200000) {
printk("nile4_set_pdar: INTCS size must be 2 MB\n");
return;
}
switch (size) {
#if 0 /* We don't support 4 GB yet */
case 0x100000000: /* 4 GB */
maskbits = 4;
break;
#endif
case 0x80000000: /* 2 GB */
maskbits = 5;
break;
case 0x40000000: /* 1 GB */
maskbits = 6;
break;
case 0x20000000: /* 512 MB */
maskbits = 7;
break;
case 0x10000000: /* 256 MB */
maskbits = 8;
break;
case 0x08000000: /* 128 MB */
maskbits = 9;
break;
case 0x04000000: /* 64 MB */
maskbits = 10;
break;
case 0x02000000: /* 32 MB */
maskbits = 11;
break;
case 0x01000000: /* 16 MB */
maskbits = 12;
break;
case 0x00800000: /* 8 MB */
maskbits = 13;
break;
case 0x00400000: /* 4 MB */
maskbits = 14;
break;
case 0x00200000: /* 2 MB */
maskbits = 15;
break;
case 0: /* OFF */
maskbits = 0;
break;
default:
printk("nile4_set_pdar: unsupported size %p\n", (void *) size);
return;
}
switch (width) {
case 8:
widthbits = 0;
break;
case 16:
widthbits = 1;
break;
case 32:
widthbits = 2;
break;
case 64:
widthbits = 3;
break;
default:
printk("nile4_set_pdar: unsupported width %d\n", width);
return;
}
nile4_out32(pdar, maskbits | (on_memory_bus ? 0x10 : 0) |
(visible ? 0x20 : 0) | (widthbits << 6) |
(phys & 0xffe00000));
nile4_out32(pdar + 4, 0);
/*
* When programming a PDAR, the register should be read immediately
* after writing it. This ensures that address decoders are properly
* configured.
*/
nile4_in32(pdar);
nile4_in32(pdar + 4);
}
/*
* PCI Master Registers
*
* Note: 32 bit addressing only!
*/
void nile4_set_pmr(u32 pmr, u32 type, u32 addr)
{
if (pmr != NILE4_PCIINIT0 && pmr != NILE4_PCIINIT1) {
printk("nile4_set_pmr: invalid pmr %d\n", pmr);
return;
}
switch (type) {
case NILE4_PCICMD_IACK: /* PCI Interrupt Acknowledge */
case NILE4_PCICMD_IO: /* PCI I/O Space */
case NILE4_PCICMD_MEM: /* PCI Memory Space */
case NILE4_PCICMD_CFG: /* PCI Configuration Space */
break;
default:
printk("nile4_set_pmr: invalid type %d\n", type);
return;
}
nile4_out32(pmr, (type << 1) | 0x10 | (addr & 0xffe00000));
nile4_out32(pmr + 4, 0);
}
/*
* Interrupt Programming
*/
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t &= ~(7 << (nile4_irq * 4));
t |= cpu_irq << (nile4_irq * 4);
nile4_out32(offset, t);
}
void nile4_map_irq_all(int cpu_irq)
{
u32 all, t;
all = cpu_irq;
all |= all << 4;
all |= all << 8;
all |= all << 16;
t = nile4_in32(NILE4_INTCTRL);
t &= 0x88888888;
t |= all;
nile4_out32(NILE4_INTCTRL, t);
t = nile4_in32(NILE4_INTCTRL + 4);
t &= 0x88888888;
t |= all;
nile4_out32(NILE4_INTCTRL + 4, t);
}
void nile4_enable_irq(int nile4_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t |= 8 << (nile4_irq * 4);
nile4_out32(offset, t);
}
void nile4_disable_irq(int nile4_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t &= ~(8 << (nile4_irq * 4));
nile4_out32(offset, t);
}
void nile4_disable_irq_all(void)
{
nile4_out32(NILE4_INTCTRL, 0);
nile4_out32(NILE4_INTCTRL + 4, 0);
}
u16 nile4_get_irq_stat(int cpu_irq)
{
return nile4_in16(NILE4_INTSTAT0 + cpu_irq * 2);
}
void nile4_enable_irq_output(int cpu_irq)
{
u32 t;
t = nile4_in32(NILE4_INTSTAT1 + 4);
t |= 1 << (16 + cpu_irq);
nile4_out32(NILE4_INTSTAT1, t);
}
void nile4_disable_irq_output(int cpu_irq)
{
u32 t;
t = nile4_in32(NILE4_INTSTAT1 + 4);
t &= ~(1 << (16 + cpu_irq));
nile4_out32(NILE4_INTSTAT1, t);
}
void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
u32 t;
t = nile4_in32(NILE4_INTPPES);
if (high)
t &= ~(1 << (pci_irq * 2));
else
t |= 1 << (pci_irq * 2);
nile4_out32(NILE4_INTPPES, t);
}
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
u32 t;
t = nile4_in32(NILE4_INTPPES);
if (level)
t |= 2 << (pci_irq * 2);
else
t &= ~(2 << (pci_irq * 2));
nile4_out32(NILE4_INTPPES, t);
}
void nile4_clear_irq(int nile4_irq)
{
nile4_out32(NILE4_INTCLR, 1 << nile4_irq);
}
void nile4_clear_irq_mask(u32 mask)
{
nile4_out32(NILE4_INTCLR, mask);
}
u8 nile4_i8259_iack(void)
{
u8 irq;
/* Set window 0 for interrupt acknowledge */
nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IACK, 0);
irq = *(volatile u8 *) NILE4_PCI_IACK_BASE;
/* Set window 0 for PCI I/O space */
nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
return irq;
}
#if 0
void nile4_dump_irq_status(void)
{
printk("CPUSTAT = %p:%p\n", (void *) nile4_in32(NILE4_CPUSTAT + 4),
(void *) nile4_in32(NILE4_CPUSTAT));
printk("INTCTRL = %p:%p\n", (void *) nile4_in32(NILE4_INTCTRL + 4),
(void *) nile4_in32(NILE4_INTCTRL));
printk("INTSTAT0 = %p:%p\n",
(void *) nile4_in32(NILE4_INTSTAT0 + 4),
(void *) nile4_in32(NILE4_INTSTAT0));
printk("INTSTAT1 = %p:%p\n",
(void *) nile4_in32(NILE4_INTSTAT1 + 4),
(void *) nile4_in32(NILE4_INTSTAT1));
printk("INTCLR = %p:%p\n", (void *) nile4_in32(NILE4_INTCLR + 4),
(void *) nile4_in32(NILE4_INTCLR));
printk("INTPPES = %p:%p\n", (void *) nile4_in32(NILE4_INTPPES + 4),
(void *) nile4_in32(NILE4_INTPPES));
}
#endif
arch/mips/ddb5074/pci.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/pci.c -- NEC DDB Vrc-5074 PCI access routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Albert Dorofeev <albert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <asm/nile4.h>
static u32 nile4_pre_pci_access0(int slot_num)
{
u32 pci_addr = 0;
u32 virt_addr = NILE4_PCI_CFG_BASE;
/* Set window 1 address 8000000 - 64 bit - 2 MB (PCI config space) */
nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x00200000, 64, 0,
0);
if (slot_num > 2)
pci_addr = 0x00040000 << slot_num;
else
virt_addr += 0x00040000 << slot_num;
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr);
return virt_addr;
}
static void nile4_post_pci_access0(void)
{
/*
* Set window 1 back to address 8000000 - 64 bit - 128 MB
* (PCI IO space)
*/
nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE),
0x08000000, 64, 1, 1);
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
}
static int nile4_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 * val)
{
int status, slot_num, func_num;
u32 result, base;
switch (size) {
case 4:
/*
* For starters let's do configuration cycle 0 only
* (one bus only)
*/
if (bus->number)
return PCIBIOS_FUNC_NOT_SUPPORTED;
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
if (slot_num == 5) {
/*
* This is Nile 4 and it will crash if we access it
* like other devices
*/
*val = nile4_in32(NILE4_PCI_BASE + where);
return PCIBIOS_SUCCESSFUL;
}
base = nile4_pre_pci_access0(slot_num);
*val = *((volatile u32 *) (base + (func_num << 8) +
(where & 0xfc)));
nile4_post_pci_access0();
return PCIBIOS_SUCCESSFUL;
case 2:
status = nile4_pci_read(bus, devfn, where, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 2)
result >>= 16;
*val = (u16)(result & 0xffff);
break;
case 1:
status = nile4_pci_read(bus, devfn, where, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 1)
result >>= 8;
if (where & 2)
result >>= 16;
*val = (u8)(result & 0xff);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int nile4_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
int status, slot_num, func_num, shift = 0;
u32 result, base;
switch (size) {
case 4:
/*
* For starters let's do configuration cycle 0 only
* (one bus only)
*/
if (bus->number)
return PCIBIOS_FUNC_NOT_SUPPORTED;
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
if (slot_num == 5) {
/*
* This is Nile 4 and it will crash if we access
* it like other devices
*/
nile4_out32(NILE4_PCI_BASE + where, val);
return PCIBIOS_SUCCESSFUL;
}
base = nile4_pre_pci_access0(slot_num);
*((volatile u32 *) (base + (func_num << 8) +
(where & 0xfc))) = val;
nile4_post_pci_access0();
return PCIBIOS_SUCCESSFUL;
case 2:
status = nile4_pci_read(bus, devfn, where, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 2)
shift += 16;
result &= ~(0xffff << shift);
result |= (u16)(val << shift);
break;
case 1:
status = nile4_pci_read(bus, devfn, where, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 2)
shift += 16;
if (where & 1)
shift += 8;
result &= ~(0xff << shift);
result |= (u8)(val << shift);
break;
}
return nile4_pci_write(bus, devfn, where, 4, result);
}
struct pci_ops nile4_pci_ops = {
.read = nile4_pci_read,
.write = nile4_pci_write,
};
struct {
struct resource ram;
struct resource flash;
struct resource isa_io;
struct resource pci_io;
struct resource isa_mem;
struct resource pci_mem;
struct resource nile4;
struct resource boot;
} ddb5074_resources = {
{ "RAM", 0x00000000, 0x03ffffff,
IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64},
{ "Flash ROM", 0x04000000, 0x043fffff},
{ "Nile4 ISA I/O", 0x06000000, 0x060fffff},
{ "Nile4 PCI I/O", 0x06100000, 0x07ffffff},
{ "Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM},
{ "Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM},
{ "Nile4 ctrl", 0x1fa00000, 0x1fbfffff,
IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64},
{ "Boot ROM", 0x1fc00000, 0x1fffffff}
};
static void __init ddb5074_pci_fixup(void)
{
struct pci_dev *dev = NULL;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
if (dev->vendor == PCI_VENDOR_ID_NEC &&
dev->device == PCI_DEVICE_ID_NEC_NILE4) {
/*
* The first 64-bit PCI base register should point to
* the Nile4 control registers. Unfortunately this
* isn't the case, so we fix it ourselves. This allows
* the serial driver to find the UART.
*/
dev->resource[0] = ddb5074_resources.nile4;
request_resource(&iomem_resource,
&dev->resource[0]);
/*
* The second 64-bit PCI base register points to the
* first memory bank. Unfortunately the address is
* wrong, so we fix it (again).
*/
dev->resource[2] = ddb5074_resources.ram;
request_resource(&iomem_resource,
&dev->resource[2]);
} else if (dev->vendor == PCI_VENDOR_ID_AL
&& dev->device == PCI_DEVICE_ID_AL_M7101) {
/*
* It's nice to have the LEDs on the GPIO pins
* available for debugging
*/
extern struct pci_dev *pci_pmu;
u8 t8;
pci_pmu = dev; /* for LEDs D2 and D3 */
/* Program the lines for LEDs D2 and D3 to output */
nile4_pci_read_config_byte(dev, 0x7d, &t8);
t8 |= 0xc0;
nile4_pci_write_config_byte(dev, 0x7d, t8);
/* Turn LEDs D2 and D3 off */
nile4_pci_read_config_byte(dev, 0x7e, &t8);
t8 |= 0xc0;
nile4_pci_write_config_byte(dev, 0x7e, t8);
}
}
}
static void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev = NULL;
int slot_num;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
slot_num = PCI_SLOT(dev->devfn);
switch (slot_num) {
case 0:
dev->irq = nile4_to_irq(NILE4_INT_INTE);
break;
case 1:
dev->irq = nile4_to_irq(NILE4_INT_INTA);
break;
case 2: /* slot 1 */
dev->irq = nile4_to_irq(NILE4_INT_INTA);
break;
case 3: /* slot 2 */
dev->irq = nile4_to_irq(NILE4_INT_INTB);
break;
case 4: /* slot 3 */
dev->irq = nile4_to_irq(NILE4_INT_INTC);
break;
case 5:
/*
* Fixup so the serial driver can use the UART
*/
dev->irq = nile4_to_irq(NILE4_INT_UART);
break;
case 13:
dev->irq = nile4_to_irq(NILE4_INT_INTE);
break;
default:
break;
}
}
}
void __init pcibios_init(void)
{
printk("PCI: Probing PCI hardware\n");
ioport_resource.end = 0x1ffffff; /* 32 MB */
iomem_resource.end = 0x1fffffff; /* 512 MB */
/* `ram' and `nile4' are requested through the Nile4 pci_dev */
request_resource(&iomem_resource, &ddb5074_resources.flash);
request_resource(&iomem_resource, &ddb5074_resources.isa_io);
request_resource(&iomem_resource, &ddb5074_resources.pci_io);
request_resource(&iomem_resource, &ddb5074_resources.isa_mem);
request_resource(&iomem_resource, &ddb5074_resources.pci_mem);
request_resource(&iomem_resource, &ddb5074_resources.boot);
pci_scan_bus(0, &nile4_pci_ops, NULL);
ddb5074_pci_fixup();
pci_assign_unassigned_resources();
pcibios_fixup_irqs();
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
bus->resource[1] = &ddb5074_resources.pci_mem;
}
char *pcibios_setup(char *str)
{
return str;
}
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
int pcibios_enable_resources(struct pci_dev *dev)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
/*
* Don't touch the Nile 4
*/
if (dev->vendor == PCI_VENDOR_ID_NEC &&
dev->device == PCI_DEVICE_ID_NEC_NILE4) return 0;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx = 0; idx < 6; idx++) {
r = &dev->resource[idx];
if (!r->start && r->end) {
printk(KERN_ERR "PCI: Device %s not available because "
"of resource collisions\n", dev->slot_name);
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
if (cmd != old_cmd) {
printk("PCI: Enabling device %s (%04x -> %04x)\n",
dev->slot_name, old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
}
int pcibios_enable_device(struct pci_dev *dev)
{
return pcibios_enable_resources(dev);
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
struct pci_dev *dev = data;
if (res->flags & IORESOURCE_IO) {
unsigned long start = res->start;
/* We need to avoid collisions with `mirrored' VGA ports
and other strange ISA hardware, so we always want the
addresses kilobyte aligned. */
if (size > 0x100) {
printk(KERN_ERR "PCI: I/O Region %s/%d too large"
" (%ld bytes)\n", dev->slot_name,
dev->resource - res, size);
}
start = (start + 1024 - 1) & ~(1024 - 1);
res->start = start;
}
}
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
struct pci_fixup pcibios_fixups[] = { };
arch/mips/ddb5074/prom.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/prom.c -- NEC DDB Vrc-5074 PROM routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
void __init prom_init(const char *s)
{
int i = 0;
if (s != (void *) -1)
while (*s && i < sizeof(arcs_cmdline) - 1)
arcs_cmdline[i++] = *s++;
arcs_cmdline[i] = '\0';
mips_machgroup = MACH_GROUP_NEC_DDB;
mips_machtype = MACH_NEC_DDB5074;
/* 64 MB non-upgradable */
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
arch/mips/ddb5476/Makefile deleted 100644 → 0
View file @ 320bcfc9
#
# Makefile for the NEC DDB Vrc-5074 specific kernel interface routines
# under Linux.
#
EXTRA_AFLAGS := $(CFLAGS)
obj-y += setup.o irq.o time.o prom.o pci.o \
int-handler.o nile4.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
arch/mips/ddb5476/int-handler.S deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/int-handler.S -- NEC DDB Vrc-5074 interrupt handler
*
* Based on arch/mips/sgi/kernel/indyIRQ.S
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/*
* A lot of complication here is taken away because:
*
* 1) We handle one interrupt and return, sitting in a loop and moving across
* all the pending IRQ bits in the cause register is _NOT_ the answer, the
* common case is one pending IRQ so optimize in that direction.
*
* 2) We need not check against bits in the status register IRQ mask, that
* would make this routine slow as hell.
*
* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
* between like BSD spl() brain-damage.
*
* Furthermore, the IRQs on the INDY look basically (barring software IRQs
* which we don't use at all) like:
*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 Local IRQ level zero
* 3 Local IRQ level one
* 4 8254 Timer zero
* 5 8254 Timer one
* 6 Bus Error
* 7 R4k timer (what we use)
*
* We handle the IRQ according to _our_ priority which is:
*
* Highest ---- R4k Timer
* Local IRQ zero
* Local IRQ one
* Bus Error
* 8254 Timer zero
* Lowest ---- 8254 Timer one
*
* then we just return, if multiple IRQs are pending then we will just take
* another exception, big deal.
*/
.text
.set noreorder
.set noat
.align 5
NESTED(ddbIRQ, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 s1, CP0_CAUSE # get irq mask
#if 1
mfc0 t2,CP0_STATUS # get enabled interrupts
and s0, s1, t2 # isolate allowed ones
#endif
/* First we check for r4k counter/timer IRQ. */
andi a0, s0, CAUSEF_IP7 # cpu timer */
bnez a0, cpu_timer_irq
andi a0, s0, CAUSEF_IP2 # delay slot, check local level zero
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP3 # delay slot, check local level one
/* Wheee, local level zero interrupt. */
jal ddb_local0_irqdispatch
move a0, sp # delay slot
j ret_from_irq
nop # delay slot
1:
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP6 # delay slot, check bus error
/* Wheee, local level one interrupt. */
move a0, sp
jal ddb_local1_irqdispatch
nop
j ret_from_irq
nop
1:
beq a0, zero, 1f
nop
/* Wheee, an asynchronous bus error... */
move a0, sp
jal ddb_buserror_irq
nop
j ret_from_irq
nop
1:
/* Here by mistake? This is possible, what can happen
* is that by the time we take the exception the IRQ
* pin goes low, so just leave if this is the case.
*/
andi a0, s0, (CAUSEF_IP4 | CAUSEF_IP5)
beq a0, zero, 1f
/* Must be one of the 8254 timers... */
move a0, sp
jal ddb_8254timer_irq
nop
1:
/* phamtom interrupt */
move a0, s1
jal ddb_phantom_irq
nop
j ret_from_irq
nop
cpu_timer_irq:
li a0, 0
move a1, sp
jal do_IRQ
/* jal ll_timer_interrupt */
nop
j ret_from_irq
nop
END(ddbIRQ)
arch/mips/ddb5476/nile4.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/nile4.c -- NEC Vrc-5074 Nile 4 support routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/nile4.h>
/*
* Physical Device Address Registers
*
* Note: 32 bit addressing only!
*/
void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int visible)
{
u32 maskbits;
u32 widthbits;
if (pdar > NILE4_BOOTCS || (pdar & 7)) {
printk("nile4_set_pdar: invalid pdar %d\n", pdar);
return;
}
if (pdar == NILE4_INTCS && size != 0x00200000) {
printk("nile4_set_pdar: INTCS size must be 2 MB\n");
return;
}
switch (size) {
#if 0 /* We don't support 4 GB yet */
case 0x100000000: /* 4 GB */
maskbits = 4;
break;
#endif
case 0x80000000: /* 2 GB */
maskbits = 5;
break;
case 0x40000000: /* 1 GB */
maskbits = 6;
break;
case 0x20000000: /* 512 MB */
maskbits = 7;
break;
case 0x10000000: /* 256 MB */
maskbits = 8;
break;
case 0x08000000: /* 128 MB */
maskbits = 9;
break;
case 0x04000000: /* 64 MB */
maskbits = 10;
break;
case 0x02000000: /* 32 MB */
maskbits = 11;
break;
case 0x01000000: /* 16 MB */
maskbits = 12;
break;
case 0x00800000: /* 8 MB */
maskbits = 13;
break;
case 0x00400000: /* 4 MB */
maskbits = 14;
break;
case 0x00200000: /* 2 MB */
maskbits = 15;
break;
case 0: /* OFF */
maskbits = 0;
break;
default:
printk("nile4_set_pdar: unsupported size %p\n",
(void *) size);
return;
}
switch (width) {
case 8:
widthbits = 0;
break;
case 16:
widthbits = 1;
break;
case 32:
widthbits = 2;
break;
case 64:
widthbits = 3;
break;
default:
printk("nile4_set_pdar: unsupported width %d\n", width);
return;
}
nile4_out32(pdar, maskbits | (on_memory_bus ? 0x10 : 0) |
(visible ? 0x20 : 0) | (widthbits << 6) |
(phys & 0xffe00000));
nile4_out32(pdar + 4, 0);
/*
* When programming a PDAR, the register should be read immediately
* after writing it. This ensures that address decoders are properly
* configured.
*/
nile4_in32(pdar);
nile4_in32(pdar + 4);
}
/*
* PCI Master Registers
*
* Note: 32 bit addressing only!
*/
void nile4_set_pmr(u32 pmr, u32 type, u32 addr)
{
if (pmr != NILE4_PCIINIT0 && pmr != NILE4_PCIINIT1) {
printk("nile4_set_pmr: invalid pmr %d\n", pmr);
return;
}
switch (type) {
case NILE4_PCICMD_IACK: /* PCI Interrupt Acknowledge */
case NILE4_PCICMD_IO: /* PCI I/O Space */
case NILE4_PCICMD_MEM: /* PCI Memory Space */
case NILE4_PCICMD_CFG: /* PCI Configuration Space */
break;
default:
printk("nile4_set_pmr: invalid type %d\n", type);
return;
}
nile4_out32(pmr, (type << 1) | 0x10 | (addr & 0xffe00000));
nile4_out32(pmr + 4, 0);
}
/*
* Interrupt Programming
*/
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t &= ~(7 << (nile4_irq * 4));
t |= cpu_irq << (nile4_irq * 4);
nile4_out32(offset, t);
}
void nile4_map_irq_all(int cpu_irq)
{
u32 all, t;
all = cpu_irq;
all |= all << 4;
all |= all << 8;
all |= all << 16;
t = nile4_in32(NILE4_INTCTRL);
t &= 0x88888888;
t |= all;
nile4_out32(NILE4_INTCTRL, t);
t = nile4_in32(NILE4_INTCTRL + 4);
t &= 0x88888888;
t |= all;
nile4_out32(NILE4_INTCTRL + 4, t);
}
void nile4_enable_irq(int nile4_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t |= 8 << (nile4_irq * 4);
nile4_out32(offset, t);
}
void nile4_disable_irq(int nile4_irq)
{
u32 offset, t;
offset = NILE4_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = nile4_in32(offset);
t &= ~(8 << (nile4_irq * 4));
nile4_out32(offset, t);
}
void nile4_disable_irq_all(void)
{
nile4_out32(NILE4_INTCTRL, 0);
nile4_out32(NILE4_INTCTRL + 4, 0);
}
u16 nile4_get_irq_stat(int cpu_irq)
{
return nile4_in16(NILE4_INTSTAT0 + cpu_irq * 2);
}
void nile4_enable_irq_output(int cpu_irq)
{
u32 t;
t = nile4_in32(NILE4_INTSTAT1 + 4);
t |= 1 << (16 + cpu_irq);
nile4_out32(NILE4_INTSTAT1, t);
}
void nile4_disable_irq_output(int cpu_irq)
{
u32 t;
t = nile4_in32(NILE4_INTSTAT1 + 4);
t &= ~(1 << (16 + cpu_irq));
nile4_out32(NILE4_INTSTAT1, t);
}
void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
u32 t;
t = nile4_in32(NILE4_INTPPES);
if (high)
t &= ~(1 << (pci_irq * 2));
else
t |= 1 << (pci_irq * 2);
nile4_out32(NILE4_INTPPES, t);
}
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
u32 t;
t = nile4_in32(NILE4_INTPPES);
if (level)
t |= 2 << (pci_irq * 2);
else
t &= ~(2 << (pci_irq * 2));
nile4_out32(NILE4_INTPPES, t);
}
void nile4_clear_irq(int nile4_irq)
{
nile4_out32(NILE4_INTCLR, 1 << nile4_irq);
}
void nile4_clear_irq_mask(u32 mask)
{
nile4_out32(NILE4_INTCLR, mask);
}
u8 nile4_i8259_iack(void)
{
u8 irq;
/* Set window 0 for interrupt acknowledge */
nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IACK, 0);
irq = *(volatile u8 *) NILE4_PCI_IACK_BASE;
/* Set window 0 for PCI I/O space */
nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
return irq;
}
#if 0
void nile4_dump_irq_status(void)
{
printk("CPUSTAT = %p:%p\n", (void *) nile4_in32(NILE4_CPUSTAT + 4),
(void *) nile4_in32(NILE4_CPUSTAT));
printk("INTCTRL = %p:%p\n", (void *) nile4_in32(NILE4_INTCTRL + 4),
(void *) nile4_in32(NILE4_INTCTRL));
printk("INTSTAT0 = %p:%p\n",
(void *) nile4_in32(NILE4_INTSTAT0 + 4),
(void *) nile4_in32(NILE4_INTSTAT0));
printk("INTSTAT1 = %p:%p\n",
(void *) nile4_in32(NILE4_INTSTAT1 + 4),
(void *) nile4_in32(NILE4_INTSTAT1));
printk("INTCLR = %p:%p\n", (void *) nile4_in32(NILE4_INTCLR + 4),
(void *) nile4_in32(NILE4_INTCLR));
printk("INTPPES = %p:%p\n", (void *) nile4_in32(NILE4_INTPPES + 4),
(void *) nile4_in32(NILE4_INTPPES));
}
#endif
arch/mips/ddb5476/pci.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5476/pci.c -- NEC DDB Vrc-5074 PCI access routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Albert Dorofeev <albert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <asm-mips/nile4.h>
static u32 nile4_pre_pci_access0(int slot_num)
{
u32 pci_addr = 0;
u32 virt_addr = NILE4_PCI_CFG_BASE;
/* work around the bug for Vrc5476 */
if (slot_num == 13)
return NILE4_BASE + NILE4_PCI_BASE;
/* Set window 1 address 08000000 - 32 bit - 128 MB (PCI config space) */
nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x08000000, 32, 0,
0);
// [jsun] we start scanning from addr:10,
// with 128M we can go up to addr:26 (slot 16)
if (slot_num <= 16) {
virt_addr += 0x00000400 << slot_num;
} else {
/* for high slot, we have to set higher PCI base addr */
pci_addr = 0x00000400 << slot_num;
}
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr);
return virt_addr;
}
static void nile4_post_pci_access0(void)
{
/*
* Set window 1 back to address 08000000 - 32 bit - 128 MB
* (PCI IO space)
*/
nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE),
0x08000000, 32, 1, 1);
// nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000);
}
static int nile4_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 * val)
{
int status, slot_num, func_num;
u32 result, base, addr;
if(size == 4) {
/* Do we need to generate type 1 configure transaction? */
if (bus->number) {
/* FIXME - not working yet */
return PCIBIOS_FUNC_NOT_SUPPORTED;
/*
* the largest type 1 configuration addr is 16M,
* < 256M config space
*/
slot_num = 0;
addr = (bus->number << 16) | (devfn < 8) | where | 1;
} else {
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
addr = (func_num << 8) + where;
}
base = nile4_pre_pci_access0(slot_num);
*val = *(volatile u32 *) (base + addr);
nile4_post_pci_access0();
return PCIBIOS_SUCCESSFUL;
}
status = nile4_pci_read(bus, devfn, where & ~3, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
switch (size) {
case 1:
if (where & 1)
result >>= 8;
if (where & 2)
result >>= 16;
*val = (u8)(result & 0xff);
break;
case 2:
if (where & 2)
result >>= 16;
*val = (u16)(result & 0xffff);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int nile4_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
int status, slot_num, func_num, shift = 0;
u32 result, base, addr;
status = nile4_pci_read(bus, devfn, where & ~3, 4, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
switch (size) {
case 1:
if (where & 2)
shift += 16;
if (where & 1)
shift += 8;
result &= ~(0xff << shift);
result |= val << shift;
break;
case 2:
if (where & 2)
shift += 16;
result &= ~(0xffff << shift);
result |= val << shift;
break;
case 4:
/* Do we need to generate type 1 configure transaction? */
if (bus->number) {
/* FIXME - not working yet */
return PCIBIOS_FUNC_NOT_SUPPORTED;
/* the largest type 1 configuration addr is 16M,
* < 256M config space */
slot_num = 0;
addr = (bus->number << 16) | (devfn < 8) |
where | 1;
} else {
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
addr = (func_num << 8) + where;
}
base = nile4_pre_pci_access0(slot_num);
*(volatile u32 *) (base + addr) = val;
nile4_post_pci_access0();
return PCIBIOS_SUCCESSFUL;
}
return nile4_pci_write(bus, devfn, where & ~3, 4, result);
}
struct pci_ops nile4_pci_ops = {
.read = nile4_pci_read,
.write = nile4_pci_write,
};
struct {
struct resource ram;
struct resource flash;
struct resource isa_io;
struct resource pci_io;
struct resource isa_mem;
struct resource pci_mem;
struct resource nile4;
struct resource boot;
} ddb5476_resources = {
// { "RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 },
{
"RAM", 0x00000000, 0x03ffffff, IORESOURCE_MEM}, {
"Flash ROM", 0x04000000, 0x043fffff}, {
"Nile4 ISA I/O", 0x06000000, 0x060fffff}, {
"Nile4 PCI I/O", 0x06100000, 0x07ffffff}, {
"Nile4 ISA mem", 0x08000000, 0x08ffffff, IORESOURCE_MEM}, {
"Nile4 PCI mem", 0x09000000, 0x0fffffff, IORESOURCE_MEM},
// { "Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM | PCI_BASE_ADDRESS_MEM_TYPE_64 },
{
"Nile4 ctrl", 0x1fa00000, 0x1fbfffff, IORESOURCE_MEM}, {
"Boot ROM", 0x1fc00000, 0x1fffffff}
};
struct resource M5229_resources[5] = {
{"M5229 BAR0", 0x1f0, 0x1f3, IORESOURCE_IO},
{"M5229 BAR1", 0x3f4, 0x3f7, IORESOURCE_IO},
{"M5229 BAR2", 0x170, 0x173, IORESOURCE_IO},
{"M5229 BAR3", 0x374, 0x377, IORESOURCE_IO},
{"M5229 BAR4", 0xf000, 0xf00f, IORESOURCE_IO}
};
static void __init ddb5476_pci_fixup(void)
{
struct pci_dev *dev = NULL;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
if (dev->vendor == PCI_VENDOR_ID_NEC &&
dev->device == PCI_DEVICE_ID_NEC_VRC5476) {
/*
* The first 64-bit PCI base register should point to
* the Nile4 control registers. Unfortunately this
* isn't the case, so we fix it ourselves. This allows
* the serial driver to find the UART.
*/
dev->resource[0] = ddb5476_resources.nile4;
request_resource(&iomem_resource,
&dev->resource[0]);
/*
* The second 64-bit PCI base register points to the
* first memory bank. Unfortunately the address is
* wrong, so we fix it (again).
*/
/* [jsun] We cannot request the resource anymore,
* because kernel/setup.c has already reserved "System
* RAM" resource at the same spot.
* The fundamental problem here is that PCI host
* controller should not put system RAM mapping in BAR
* and make subject to PCI resource assignement.
* Current fix is a total hack. We set parent to 1 so
* so that PCI resource assignement code is fooled to
* think the resource is assigned, and will not attempt
* to mess with it.
*/
dev->resource[2] = ddb5476_resources.ram;
if (request_resource(&iomem_resource,
&dev->resource[2]) ) {
dev->resource[2].parent = 0x1;
}
} else if (dev->vendor == PCI_VENDOR_ID_AL
&& dev->device == PCI_DEVICE_ID_AL_M7101) {
/*
* It's nice to have the LEDs on the GPIO pins
* available for debugging
*/
extern struct pci_dev *pci_pmu;
u8 t8;
pci_pmu = dev; /* for LEDs D2 and D3 */
/* Program the lines for LEDs D2 and D3 to output */
nile4_pci_read(dev->bus, dev->devfn, 0x7d, 1, &t8);
t8 |= 0xc0;
nile4_pci_write(dev->bus, dev->devfn, 0x7d, 1, t8);
/* Turn LEDs D2 and D3 off */
nile4_pci_read(dev->bus, dev->devfn, 0x7e, 1, &t8);
t8 |= 0xc0;
nile4_pci_write(dev->bus, dev->devfn, 0x7e, 1, t8);
} else if (dev->vendor == PCI_VENDOR_ID_AL &&
dev->device == 0x5229) {
int i;
for (i = 0; i < 5; i++) {
dev->resource[i] = M5229_resources[i];
request_resource(&ioport_resource,
&dev->resource[i]);
}
}
}
}
static void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev = NULL;
int slot_num;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
slot_num = PCI_SLOT(dev->devfn);
switch (slot_num) {
case 3: /* re-programmed to USB */
dev->irq = 9; /* hard-coded; see irq.c */
break;
case 4: /* re-programmed to PMU */
dev->irq = 10; /* hard-coded; see irq.c */
break;
case 6: /* on-board pci-pci bridge */
dev->irq = 0xff;
break;
case 7: /* on-board ether */
dev->irq = nile4_to_irq(NILE4_INT_INTB);
break;
case 8: /* ISA-PCI bridge */
dev->irq = nile4_to_irq(NILE4_INT_INTC);
break;
case 9: /* ext slot #3 */
dev->irq = nile4_to_irq(NILE4_INT_INTD);
break;
case 10: /* ext slot #4 */
dev->irq = nile4_to_irq(NILE4_INT_INTA);
break;
case 13: /* Vrc5476 */
dev->irq = 0xff;
break;
case 14: /* HD controller, M5229 */
dev->irq = 14;
break;
default:
printk
("JSUN : in pcibios_fixup_irqs - unkown slot %d\n",
slot_num);
panic
("JSUN : in pcibios_fixup_irqs - unkown slot.\n");
}
}
}
void __init pcibios_init(void)
{
printk("PCI: Emulate bios initialization \n");
/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
*(long *) (NILE4_BASE + NILE4_BAR0) = 0x8;
printk("PCI: Probing PCI hardware\n");
ioport_resource.end = 0x1ffffff; /* 32 MB */
iomem_resource.end = 0x1fffffff; /* 512 MB */
/* `ram' and `nile4' are requested through the Nile4 pci_dev */
request_resource(&iomem_resource, &ddb5476_resources.flash);
request_resource(&iomem_resource, &ddb5476_resources.isa_io);
request_resource(&iomem_resource, &ddb5476_resources.pci_io);
request_resource(&iomem_resource, &ddb5476_resources.isa_mem);
request_resource(&iomem_resource, &ddb5476_resources.pci_mem);
request_resource(&iomem_resource, &ddb5476_resources.boot);
pci_scan_bus(0, &nile4_pci_ops, NULL);
ddb5476_pci_fixup();
pci_assign_unassigned_resources();
pcibios_fixup_irqs();
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
/* [jsun] we don't know how to fix sub-buses yet */
if (bus->number == 0) {
bus->resource[1] = &ddb5476_resources.pci_mem;
}
}
char *pcibios_setup(char *str)
{
return str;
}
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
#if 0 /* original DDB5074 code */
void __devinit
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
struct resource *res)
{
/*
* our caller figure out range by going through the dev structures.
* I guess this is the place to fix things up if the bus is using a
* different view of the addressing space.
*/
if (bus->number == 0) {
ranges->io_start -= bus->resource[0]->start;
ranges->io_end -= bus->resource[0]->start;
ranges->mem_start -= bus->resource[1]->start;
ranges->mem_end -= bus->resource[1]->start;
}
}
#endif
int pcibios_enable_resources(struct pci_dev *dev)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
/*
* Don't touch the Nile 4
*/
if (dev->vendor == PCI_VENDOR_ID_NEC &&
dev->device == PCI_DEVICE_ID_NEC_VRC5476) return 0;
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx = 0; idx < 6; idx++) {
r = &dev->resource[idx];
if (!r->start && r->end) {
printk(KERN_ERR "PCI: Device %s not available because "
"of resource collisions\n", dev->slot_name);
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
if (cmd != old_cmd) {
printk("PCI: Enabling device %s (%04x -> %04x)\n",
dev->slot_name, old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
}
int pcibios_enable_device(struct pci_dev *dev)
{
return pcibios_enable_resources(dev);
}
void pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
struct pci_dev *dev = data;
if (res->flags & IORESOURCE_IO) {
unsigned long start = res->start;
/* We need to avoid collisions with `mirrored' VGA ports
and other strange ISA hardware, so we always want the
addresses kilobyte aligned. */
if (size > 0x100) {
printk(KERN_ERR "PCI: I/O Region %s/%d too large"
" (%ld bytes)\n", dev->slot_name,
dev->resource - res, size);
}
start = (start + 1024 - 1) & ~(1024 - 1);
res->start = start;
}
}
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
struct pci_fixup pcibios_fixups[] = { {0} };
arch/mips/ddb5476/prom.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5476/prom.c -- NEC DDB Vrc-5476 PROM routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Jun Sun - modified for DDB5476.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
/* [jsun@junsun.net] PMON passes arguments in C main() style */
void __init prom_init(int argc, const char **arg)
{
int i;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
mips_machgroup = MACH_GROUP_NEC_DDB;
mips_machtype = MACH_NEC_DDB5476;
/* 64 MB non-upgradable */
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
arch/mips/ddb5476/time.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/mips/ddb5074/time.c -- Timer routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/init.h>
#include <asm/mc146818rtc.h>
static unsigned char ddb_rtc_read_data(unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
return inb_p(RTC_PORT(1));
}
static void ddb_rtc_write_data(unsigned char data, unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
outb_p(data, RTC_PORT(1));
}
static int ddb_rtc_bcd_mode(void)
{
return 1;
}
struct rtc_ops ddb_rtc_ops = {
ddb_rtc_read_data,
ddb_rtc_write_data,
ddb_rtc_bcd_mode
};
arch/mips/ddb5xxx/common/Makefile
View file @ 3ad349a5
......@@ -2,4 +2,4 @@
# Makefile for the common code of NEC DDB-Vrc5xxx board
#
obj-y += irq.o irq_cpu.o nile4.o prom.o pci.o pci_auto.o rtc_ds1386.o
obj-y += irq.o nile4.o prom.o rtc_ds1386.o
arch/mips/ddb5xxx/common/irq.c
View file @ 3ad349a5
......@@ -13,12 +13,13 @@
*/
#include <linux/config.h>
#include <linux/init.h>
#include <asm/irq.h>
void (*irq_setup)(void);
void __init init_IRQ(void)
{
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
extern void breakpoint(void);
extern void set_debug_traps(void);
......@@ -26,6 +27,8 @@ void __init init_IRQ(void)
set_debug_traps();
breakpoint();
#endif
/* set up default irq controller */
init_generic_irq();
/* invoke board-specific irq setup */
irq_setup();
......
arch/mips/ddb5xxx/common/irq_cpu.c deleted 100644 → 0
View file @ 320bcfc9
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/ddb5xxx/common/irq_cpu.c
* This file define the irq handler for MIPS CPU interrupts.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
/*
* Almost all MIPS CPUs define 8 interrupt sources. They are typically
* level triggered (i.e., cannot be cleared from CPU; must be cleared from
* device). The first two are software interrupts. The last one is
* usually cpu timer interrupt if coutner register is present.
*
* This file exports one global function:
* mips_cpu_irq_init(u32 irq_base);
*/
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/mipsregs.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
#include <asm/ddb5xxx/debug.h>
static int mips_cpu_irq_base=-1;
static void
mips_cpu_irq_enable(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static void
mips_cpu_irq_disable(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
static unsigned int mips_cpu_irq_startup(unsigned int irq)
{
mips_cpu_irq_enable(irq);
return 0;
}
#define mips_cpu_irq_shutdown mips_cpu_irq_disable
static void
mips_cpu_irq_ack(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
/* although we attemp to clear the IP bit in cause reigster, I think
* usually it is cleared by device (irq source)
*/
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
/* I am not fully convinced that I should disable irq here */
}
static void
mips_cpu_irq_end(unsigned int irq)
{
MIPS_ASSERT(mips_cpu_irq_base != -1);
MIPS_ASSERT(irq >= mips_cpu_irq_base);
MIPS_ASSERT(irq < mips_cpu_irq_base+8);
/* I am not fully convinced that I should enable irq here */
}
static hw_irq_controller mips_cpu_irq_controller = {
"CPU_irq",
mips_cpu_irq_startup,
mips_cpu_irq_shutdown,
mips_cpu_irq_enable,
mips_cpu_irq_disable,
mips_cpu_irq_ack,
mips_cpu_irq_end,
NULL /* no affinity stuff for UP */
};
void
mips_cpu_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< irq_base+8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &mips_cpu_irq_controller;
}
mips_cpu_irq_base = irq_base;
}
arch/mips/ddb5xxx/common/nile4.c
View file @ 3ad349a5
/***********************************************************************
/*
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
......@@ -12,19 +12,14 @@
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/ddb5xxx/debug.h>
u32
ddb_calc_pdar(u32 phys, u32 size, int width,
ddb_calc_pdar(u32 phys, u32 size, int width,
int on_memory_bus, int pci_visible)
{
u32 maskbits;
......@@ -73,7 +68,7 @@ ddb_calc_pdar(u32 phys, u32 size, int width,
maskbits = 0;
break;
default:
panic("nile4_set_pdar: unsupported size %p\n", (void *) size);
panic("nile4_set_pdar: unsupported size %p", (void *) size);
}
switch (width) {
case 8:
......@@ -89,7 +84,7 @@ ddb_calc_pdar(u32 phys, u32 size, int width,
widthbits = 3;
break;
default:
panic("nile4_set_pdar: unsupported width %d\n", width);
panic("nile4_set_pdar: unsupported width %d", width);
}
return maskbits | (on_memory_bus ? 0x10 : 0) |
......@@ -128,7 +123,7 @@ void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options)
case DDB_PCICMD_CFG: /* PCI Configuration Space */
break;
default:
panic("nile4_set_pmr: invalid type %d\n", type);
panic("nile4_set_pmr: invalid type %d", type);
}
ddb_out32(pmr, (type << 1) | (addr & 0xffe00000) | options );
ddb_out32(pmr + 4, 0);
......
arch/mips/ddb5xxx/common/pci.c deleted 100644 → 0
View file @ 320bcfc9
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/ddb5xxx/common/pci.c
* Common PCI routines for DDB5xxx - as a matter of fact, meant for all
* MIPS machines.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
/*
* This file contains common PCI routines meant to be shared for
* all MIPS machines.
*
* Strategies:
*
* . We rely on pci_auto.c file to assign PCI resources (MEM and IO)
* TODO: this should be optional for some machines where they do have
* a real "pcibios" that does resource assignment.
*
* . We then use pci_scan_bus() to "discover" all the resources for
* later use by Linux.
*
* . We finally reply on a board supplied function, pcibios_fixup_irq(), to
* to assign the interrupts. We may use setup-irq.c under drivers/pci
* later.
*
* . Specifically, we will *NOT* use pci_assign_unassigned_resources(),
* because we assume all PCI devices should have the resources correctly
* assigned and recorded.
*
* Limitations:
*
* . We "collapse" all IO and MEM spaces in sub-buses under a top-level bus
* into a contiguous range.
*
* . In the case of Memory space, the rnage is 1:1 mapping with CPU physical
* address space.
*
* . In the case of IO space, it starts from 0, and the beginning address
* is mapped to KSEG0ADDR(mips_io_port) in the CPU physical address.
*
* . These are the current MIPS limitations (by ioremap, etc). In the
* future, we may remove them.
*
* Credits:
* Most of the code are derived from the pci routines from PPC and Alpha,
* which were mostly writtne by
* Cort Dougan, cort@fsmlabs.com
* Matt Porter, mporter@mvista.com
* Dave Rusling david.rusling@reo.mts.dec.com
* David Mosberger davidm@cs.arizona.edu
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/ddb5xxx/pci.h>
#include <asm/ddb5xxx/debug.h>
struct pci_fixup pcibios_fixups[] = { {0} };
extern int pciauto_assign_resources(int busno, struct pci_channel * hose);
void __init pcibios_init(void)
{
struct pci_channel *p;
struct pci_bus *bus;
int busno;
/* assign resources */
busno=0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
busno = pciauto_assign_resources(busno, p) + 1;
}
/* scan the buses */
busno = 0;
for (p= mips_pci_channels; p->pci_ops != NULL; p++) {
bus = pci_scan_bus(busno, p->pci_ops, p);
busno = bus->subordinate+1;
}
/* fixup irqs (board specific routines) */
pcibios_fixup_irqs();
/*
* should we do a fixup of ioport_resource and iomem_resource
* based on mips_pci_channels?
* Let us wait and see if this is a common need and whether there
* are exceptions. Until then, each board should adjust them
* perhaps in their setup() function.
*/
}
int pcibios_enable_device(struct pci_dev *dev)
{
/* pciauto_assign_resources() will enable all devices found */
return 0;
}
unsigned long __init
pci_bridge_check_io(struct pci_dev *bridge)
{
u16 io;
pci_read_config_word(bridge, PCI_IO_BASE, &io);
if (!io) {
pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
pci_read_config_word(bridge, PCI_IO_BASE, &io);
pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
}
if (io)
return IORESOURCE_IO;
printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
bridge->name);
return 0;
}
void __init pcibios_fixup_bus(struct pci_bus *bus)
{
/* Propogate hose info into the subordinate devices. */
struct pci_channel *hose = bus->sysdata;
struct pci_dev *dev = bus->self;
if (!dev) {
/* Root bus */
bus->resource[0] = hose->io_resource;
bus->resource[1] = hose->mem_resource;
} else {
/* This is a bridge. Do not care how it's initialized,
just link its resources to the bus ones */
int i;
for(i=0; i<3; i++) {
bus->resource[i] =
&dev->resource[PCI_BRIDGE_RESOURCES+i];
bus->resource[i]->name = bus->name;
}
bus->resource[0]->flags |= pci_bridge_check_io(dev);
bus->resource[1]->flags |= IORESOURCE_MEM;
/* For now, propagate hose limits to the bus;
we'll adjust them later. */
bus->resource[0]->end = hose->io_resource->end;
bus->resource[1]->end = hose->mem_resource->end;
/* Turn off downstream PF memory address range by default */
bus->resource[2]->start = 1024*1024;
bus->resource[2]->end = bus->resource[2]->start - 1;
}
}
char *pcibios_setup(char *str)
{
return str;
}
void
pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
/* this should not be called */
MIPS_ASSERT(1 == 0);
}
arch/mips/ddb5xxx/common/pci_auto.c deleted 100644 → 0
View file @ 320bcfc9
/*
* arch/ppc/kernel/pci_auto.c
*
* PCI autoconfiguration library
*
* Author: Matt Porter <mporter@mvista.com>
*
* Copyright 2000, 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* Modified for MIPS by Jun Sun, jsun@mvista.com
*
* . Simplify the interface between pci_auto and the rest: a single function.
* . Assign resources from low address to upper address.
* . change most int to u32.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/ddb5xxx/pci.h>
#include <asm/ddb5xxx/debug.h>
#define DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
/* These are used for config access before all the PCI probing
has been done. */
int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val);
int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val);
int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val);
int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val);
static u32 pciauto_lower_iospc;
static u32 pciauto_upper_iospc;
static u32 pciauto_lower_memspc;
static u32 pciauto_upper_memspc;
void __init
pciauto_setup_bars(struct pci_channel *hose,
int current_bus,
int pci_devfn)
{
u32 bar_response, bar_size, bar_value;
u32 bar, addr_mask, bar_nr = 0;
u32 * upper_limit;
u32 * lower_limit;
int found_mem64 = 0;
DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4)
{
/* Tickle the BAR and get the response */
early_write_config_dword(hose,
current_bus,
pci_devfn,
bar,
0xffffffff);
early_read_config_dword(hose,
current_bus,
pci_devfn,
bar,
&bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE)
{
addr_mask = PCI_BASE_ADDRESS_IO_MASK;
upper_limit = &pciauto_upper_iospc;
lower_limit = &pciauto_lower_iospc;
DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
}
else
{
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
found_mem64 = 1;
addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
upper_limit = &pciauto_upper_memspc;
lower_limit = &pciauto_lower_memspc;
DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
}
/* Calculate requested size */
bar_size = ~(bar_response & addr_mask) + 1;
/* Allocate a base address */
bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
MIPS_ASSERT(bar_value + bar_size <= *upper_limit);
/* Write it out and update our limit */
early_write_config_dword(hose,
current_bus,
pci_devfn,
bar,
bar_value);
*lower_limit = bar_value + bar_size;
/*
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
if (found_mem64)
{
bar += 4;
early_write_config_dword(hose,
current_bus,
pci_devfn,
bar,
0x00000000);
}
bar_nr++;
DBG("size=0x%x, address=0x%x\n",
bar_size, bar_value);
}
}
void __init
pciauto_prescan_setup_bridge(struct pci_channel *hose,
int current_bus,
int pci_devfn,
int sub_bus)
{
int cmdstat;
/* Configure bus number registers */
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_PRIMARY_BUS,
current_bus);
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_SECONDARY_BUS,
sub_bus + 1);
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_SUBORDINATE_BUS,
0xff);
/* Round memory allocator to 1MB boundary */
pciauto_upper_memspc &= ~(0x100000 - 1);
/* Round I/O allocator to 4KB boundary */
pciauto_upper_iospc &= ~(0x1000 - 1);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_MEMORY_LIMIT,
((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_IO_LIMIT,
((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_IO_LIMIT_UPPER16,
((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
/* We don't support prefetchable memory for now, so disable */
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_PREF_MEMORY_BASE,
0x1000);
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_PREF_MEMORY_LIMIT,
0x1000);
/* Enable memory and I/O accesses, enable bus master */
early_read_config_dword(hose,
current_bus,
pci_devfn,
PCI_COMMAND,
&cmdstat);
early_write_config_dword(hose,
current_bus,
pci_devfn,
PCI_COMMAND,
cmdstat |
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
}
void __init
pciauto_postscan_setup_bridge(struct pci_channel *hose,
int current_bus,
int pci_devfn,
int sub_bus)
{
/* Configure bus number registers */
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_SUBORDINATE_BUS,
sub_bus);
/* Round memory allocator to 1MB boundary */
pciauto_upper_memspc &= ~(0x100000 - 1);
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_MEMORY_BASE,
pciauto_upper_memspc >> 16);
/* Round I/O allocator to 4KB boundary */
pciauto_upper_iospc &= ~(0x1000 - 1);
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_IO_BASE,
(pciauto_upper_iospc & 0x0000f000) >> 8);
early_write_config_word(hose,
current_bus,
pci_devfn,
PCI_IO_BASE_UPPER16,
pciauto_upper_iospc >> 16);
}
#define PCIAUTO_IDE_MODE_MASK 0x05
int __init
pciauto_bus_scan(struct pci_channel *hose, int current_bus)
{
int sub_bus;
u32 pci_devfn, pci_class, cmdstat, found_multi=0;
unsigned short vid;
unsigned char header_type;
sub_bus = current_bus;
for (pci_devfn=0; pci_devfn<0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn) && !found_multi)
continue;
early_read_config_byte(hose,
current_bus,
pci_devfn,
PCI_HEADER_TYPE,
&header_type);
if (!PCI_FUNC(pci_devfn))
found_multi = header_type & 0x80;
early_read_config_word(hose,
current_bus,
pci_devfn,
PCI_VENDOR_ID,
&vid);
if (vid == 0xffff) continue;
early_read_config_dword(hose,
current_bus,
pci_devfn,
PCI_CLASS_REVISION, &pci_class);
if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
pciauto_prescan_setup_bridge(hose,
current_bus,
pci_devfn,
sub_bus);
sub_bus = pciauto_bus_scan(hose, sub_bus+1);
pciauto_postscan_setup_bridge(hose,
current_bus,
pci_devfn,
sub_bus);
} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
unsigned char prg_iface;
early_read_config_byte(hose,
current_bus,
pci_devfn,
PCI_CLASS_PROG,
&prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
continue;
}
}
/*
* Found a peripheral, enable some standard
* settings
*/
early_read_config_dword(hose,
current_bus,
pci_devfn,
PCI_COMMAND,
&cmdstat);
early_write_config_dword(hose,
current_bus,
pci_devfn,
PCI_COMMAND,
cmdstat |
PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
early_write_config_byte(hose,
current_bus,
pci_devfn,
PCI_LATENCY_TIMER,
0x80);
/* Allocate PCI I/O and/or memory space */
pciauto_setup_bars(hose,
current_bus,
pci_devfn);
}
return sub_bus;
}
int __init
pciauto_assign_resources(int busno, struct pci_channel *hose)
{
/* setup resource limits */
pciauto_lower_iospc = hose->io_resource->start;
pciauto_upper_iospc = hose->io_resource->end + 1;
pciauto_lower_memspc = hose->mem_resource->start;
pciauto_upper_memspc = hose->mem_resource->end + 1;
return pciauto_bus_scan(hose, busno);
}
/*
* These functions are used early on before PCI scanning is done
* and all of the pci_dev and pci_bus structures have been created.
*/
static struct pci_dev *
fake_pci_dev(struct pci_channel *hose, int busnr, int devfn)
{
static struct pci_dev dev;
static struct pci_bus bus;
dev.bus = &bus;
dev.sysdata = hose;
dev.devfn = devfn;
bus.number = busnr;
bus.ops = hose->pci_ops;
return &dev;
}
#define EARLY_PCI_OP(rw, size, type) \
int early_##rw##_config_##size(struct pci_channel *hose, int bus, \
int devfn, int offset, type value) \
{ \
return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
offset, value); \
}
EARLY_PCI_OP(read, byte, u8 *)
EARLY_PCI_OP(read, word, u16 *)
EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
arch/mips/ddb5xxx/common/prom.c
View file @ 3ad349a5
......@@ -22,8 +22,21 @@
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/debug.h>
char arcs_cmdline[COMMAND_LINE_SIZE];
char arcs_cmdline[CL_SIZE];
const char *get_system_type(void)
{
switch (mips_machtype) {
case MACH_NEC_DDB5074: return "NEC DDB Vrc-5074";
case MACH_NEC_DDB5476: return "NEC DDB Vrc-5476";
case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477";
case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper";
case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII";
default: return "Unknown NEC board";
}
}
/* [jsun@junsun.net] PMON passes arguments in C main() style */
void __init prom_init(int argc, const char **arg)
......@@ -40,19 +53,91 @@ void __init prom_init(int argc, const char **arg)
strcat(arcs_cmdline, " ");
}
/* by default all these boards use dhcp/nfs root fs */
strcat(arcs_cmdline, "ip=bootp");
mips_machgroup = MACH_GROUP_NEC_DDB;
#if defined(CONFIG_DDB5074)
mips_machtype = MACH_NEC_DDB5074;
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
#elif defined(CONFIG_DDB5476)
mips_machtype = MACH_NEC_DDB5476;
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
#elif defined(CONFIG_DDB5477)
mips_machtype = MACH_NEC_DDB5477;
ddb5477_runtime_detection();
add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
#endif
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
}
#if defined(CONFIG_DDB5477)
#define DEFAULT_LCS1_BASE 0x19000000
#define TESTVAL1 'K'
#define TESTVAL2 'S'
int board_ram_size;
void ddb5477_runtime_detection(void)
{
volatile char *test_offset;
char saved_test_byte;
/* Determine if this is a DDB5477 board, or a BSB-VR0300
base board. We can tell by checking for the location of
the NVRAM. It lives at the beginning of LCS1 on the DDB5477,
and the beginning of LCS1 on the BSB-VR0300 is flash memory.
The first 2K of the NVRAM are reserved, so don't we'll poke
around just after that.
*/
/* We can only use the PCI bus to distinquish between
the Rockhopper and RockhopperII backplanes and this must
wait until ddb5477_board_init() in setup.c after the 5477
is initialized. So, until then handle
both Rockhopper and RockhopperII backplanes as Rockhopper 1
*/
test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800);
saved_test_byte = *test_offset;
*test_offset = TESTVAL1;
if (*test_offset != TESTVAL1) {
/* We couldn't set our test value, so it must not be NVRAM,
so it's a BSB_VR0300 */
mips_machtype = MACH_NEC_ROCKHOPPER;
} else {
/* We may have gotten lucky, and the TESTVAL1 was already
stored at the test location, so we must check a second
test value */
*test_offset = TESTVAL2;
if (*test_offset != TESTVAL2) {
/* OK, we couldn't set this value either, so it must
definately be a BSB_VR0300 */
mips_machtype = MACH_NEC_ROCKHOPPER;
} else {
/* We could change the value twice, so it must be
NVRAM, so it's a DDB_VRC5477 */
mips_machtype = MACH_NEC_DDB5477;
}
}
/* Restore the original byte */
*test_offset = saved_test_byte;
/* before we know a better way, we will trust PMON for getting
* RAM size
*/
board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf));
db_run(printk("DDB run-time detection : %s, %d MB RAM\n",
mips_machtype == MACH_NEC_DDB5477 ?
"DDB5477" : "Rockhopper",
board_ram_size >> 20));
/* we can't handle ram size > 128 MB */
db_assert(board_ram_size <= (128 << 20));
}
#endif
arch/mips/ddb5xxx/common/rtc_ds1386.c
View file @ 3ad349a5
......@@ -25,7 +25,8 @@
#include <asm/time.h>
#include <asm/addrspace.h>
#include <asm/ddb5xxx/debug.h>
#include <asm/mc146818rtc.h>
#include <asm/debug.h>
#define EPOCH 2000
......@@ -36,7 +37,7 @@ static unsigned long rtc_base;
static unsigned long
rtc_ds1386_get_time(void)
{
{
u8 byte;
u8 temp;
unsigned int year, month, day, hour, minute, second;
......@@ -73,7 +74,7 @@ rtc_ds1386_get_time(void)
return mktime(year, month, day, hour, minute, second);
}
static int
static int
rtc_ds1386_set_time(unsigned long t)
{
struct rtc_time tm;
......@@ -89,6 +90,7 @@ rtc_ds1386_set_time(unsigned long t)
/* convert */
to_tm(t, &tm);
/* check each field one by one */
year = BIN2BCD(tm.tm_year - EPOCH);
if (year != READ_RTC(0xA)) {
......@@ -96,7 +98,7 @@ rtc_ds1386_set_time(unsigned long t)
}
temp = READ_RTC(0x9);
month = BIN2BCD(tm.tm_mon);
month = BIN2BCD(tm.tm_mon+1); /* tm_mon starts from 0 to 11 */
if (month != (temp & 0x1f)) {
WRITE_RTC( 0x9,
(month & 0x1f) | (temp & ~0x1f) );
......@@ -131,7 +133,7 @@ rtc_ds1386_set_time(unsigned long t)
if (second != READ_RTC(0x1)) {
WRITE_RTC(0x1, second);
}
return 0;
}
......@@ -139,10 +141,10 @@ void
rtc_ds1386_init(unsigned long base)
{
unsigned char byte;
/* remember the base */
rtc_base = base;
MIPS_ASSERT((rtc_base & 0xe0000000) == KSEG1);
db_assert((rtc_base & 0xe0000000) == KSEG1);
/* turn on RTC if it is not on */
byte = READ_RTC(0x9);
......
arch/mips/ddb5074/Makefile → arch/mips/ddb5xxx/ddb5074/Makefile
View file @ 3ad349a5
......@@ -3,6 +3,6 @@
# under Linux.
#
EXTRA_AFLAGS := $(CFLAGS)
obj-y += setup.o irq.o int-handler.o nile4_pic.o time.o
obj-y := setup.o irq.o time.o prom.o pci.o int-handler.o nile4.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/ddb5074/irq.c → arch/mips/ddb5xxx/ddb5074/irq.c
View file @ 3ad349a5
......@@ -6,32 +6,25 @@
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/ptrace.h>
#include <asm/nile4.h>
#include <asm/ddb5074.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/ddb5xxx/ddb5074.h>
extern void __init i8259_init(void);
extern void i8259_disable_irq(unsigned int irq_nr);
extern void i8259_enable_irq(unsigned int irq_nr);
extern asmlinkage void ddbIRQ(void);
extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs);
extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
void no_action(int cpl, void *dev_id, struct pt_regs *regs)
{
}
static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
......@@ -60,9 +53,9 @@ static void m1543_irq_setup(void)
*
* IRQ1 - keyboard (default set by M1543)
* IRQ3 - reserved for UART B (default set by M1543) (note that
* the schematics for the DDB Vrc-5074 board seem to
* indicate that IRQ3 is connected to the DS1386
* watchdog timer interrupt output so we might have
* the schematics for the DDB Vrc-5074 board seem to
* indicate that IRQ3 is connected to the DS1386
* watchdog timer interrupt output so we might have
* a conflict)
* IRQ4 - reserved for UART A (default set by M1543)
* IRQ5 - parallel (default set by M1543)
......@@ -71,7 +64,7 @@ static void m1543_irq_setup(void)
*/
/*
* Assing mouse interrupt to IRQ12
* Assing mouse interrupt to IRQ12
*/
/* Enter configuration mode */
......@@ -86,111 +79,44 @@ static void m1543_irq_setup(void)
outb(0x72, M1543_PNP_INDEX);
outb(0x0c, M1543_PNP_DATA);
/* Leave configration mode */
outb(0xbb, M1543_PNP_CONFIG);
/* Initialize the 8259 PIC in the M1543 */
i8259_init();
/* Enable the interrupt cascade */
nile4_enable_irq(NILE4_INT_INTE);
request_region(M1543_PNP_CONFIG, 2, "M1543 config");
request_region(M1543_INT1_MASTER_ELCR, 2, "pic ELCR");
}
static void nile4_irq_setup(void)
{
int i;
/* Map all interrupts to CPU int #0 */
nile4_map_irq_all(0);
/* PCI INTA#-E# must be level triggered */
nile4_set_pci_irq_level_or_edge(0, 1);
nile4_set_pci_irq_level_or_edge(1, 1);
nile4_set_pci_irq_level_or_edge(2, 1);
nile4_set_pci_irq_level_or_edge(3, 1);
nile4_set_pci_irq_level_or_edge(4, 1);
/* PCI INTA#-D# must be active low, INTE# must be active high */
nile4_set_pci_irq_polarity(0, 0);
nile4_set_pci_irq_polarity(1, 0);
nile4_set_pci_irq_polarity(2, 0);
nile4_set_pci_irq_polarity(3, 0);
nile4_set_pci_irq_polarity(4, 1);
outb(0x30, M1543_PNP_INDEX);
printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
for (i = 0; i < 16; i++)
nile4_clear_irq(i);
/* Enable CPU int #0 */
nile4_enable_irq_output(0);
request_mem_region(NILE4_BASE, NILE4_SIZE, "Nile 4");
}
/*
* IRQ2 is cascade interrupt to second interrupt controller
*/
static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
outb(0x70, M1543_PNP_INDEX);
printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
/* Leave configration mode */
outb(0xbb, M1543_PNP_CONFIG);
void disable_irq(unsigned int irq_nr)
{
if (is_i8259_irq(irq_nr))
i8259_disable_irq(irq_nr);
else
nile4_disable_irq(irq_to_nile4(irq_nr));
}
void enable_irq(unsigned int irq_nr)
{
if (is_i8259_irq(irq_nr))
i8259_enable_irq(irq_nr);
else
nile4_enable_irq(irq_to_nile4(irq_nr));
}
int table[16] = { 0, };
void ddb_local0_irqdispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
#if 1
volatile static int nesting = 0;
if (nesting++ == 0)
ddb5074_led_d3(1);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
mask = nile4_get_irq_stat(0);
nile4_clear_irq_mask(mask);
/* Handle the timer interrupt first */
#if 0
if (mask & (1 << NILE4_INT_GPT)) {
nile4_disable_irq(NILE4_INT_GPT);
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
nile4_enable_irq(NILE4_INT_GPT);
mask &= ~(1 << NILE4_INT_GPT);
}
#endif
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
if (mask & 1) {
nile4_disable_irq(nile4_irq);
if (nile4_irq == NILE4_INT_INTE) {
int i8259_irq = nile4_i8259_iack();
i8259_do_irq(i8259_irq, regs);
int i8259_irq;
nile4_clear_irq(NILE4_INT_INTE);
i8259_irq = nile4_i8259_iack();
do_IRQ(i8259_irq, regs);
} else
do_IRQ(nile4_to_irq(nile4_irq), regs);
nile4_enable_irq(nile4_irq);
}
#if 1
if (--nesting == 0)
ddb5074_led_d3(0);
ddb5074_led_hex(nesting < 16 ? nesting : 15);
#endif
}
void ddb_local1_irqdispatch(void)
......@@ -210,17 +136,33 @@ void ddb_8254timer_irq(void)
void __init ddb_irq_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
if (remote_debug)
set_debug_traps();
breakpoint(); /* you may move this line to whereever you want :-) */
#endif
request_region(0x20, 0x20, "pic1");
request_region(0xa0, 0x20, "pic2");
i8259_setup_irq(2, &irq2);
nile4_irq_setup();
m1543_irq_setup();
/* setup cascade interrupts */
setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
set_except_vector(0, ddbIRQ);
nile4_irq_setup(NILE4_IRQ_BASE);
m1543_irq_setup();
init_i8259_irqs();
printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
printk("enabling 8259 cascade\n");
ddb5074_led_hex(0);
/* Enable the interrupt cascade */
nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
}
arch/mips/ddb5xxx/ddb5074/nile4_pic.c 0 → 100644
View file @ 3ad349a5
/*
* arch/mips/ddb5476/nile4.c --
* low-level PIC code for NEC Vrc-5476 (Nile 4)
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/addrspace.h>
#include <asm/ddb5xxx/ddb5xxx.h>
static int irq_base;
/*
* Interrupt Programming
*/
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(7 << (nile4_irq * 4));
t |= cpu_irq << (nile4_irq * 4);
ddb_out32(offset, t);
}
void nile4_map_irq_all(int cpu_irq)
{
u32 all, t;
all = cpu_irq;
all |= all << 4;
all |= all << 8;
all |= all << 16;
t = ddb_in32(DDB_INTCTRL);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL, t);
t = ddb_in32(DDB_INTCTRL + 4);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL + 4, t);
}
void nile4_enable_irq(unsigned int nile4_irq)
{
u32 offset, t;
nile4_irq-=irq_base;
ddb5074_led_hex(8);
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
ddb5074_led_hex(9);
t = ddb_in32(offset);
ddb5074_led_hex(0xa);
t |= 8 << (nile4_irq * 4);
ddb_out32(offset, t);
ddb5074_led_hex(0xb);
}
void nile4_disable_irq(unsigned int nile4_irq)
{
u32 offset, t;
nile4_irq-=irq_base;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(8 << (nile4_irq * 4));
ddb_out32(offset, t);
}
void nile4_disable_irq_all(void)
{
ddb_out32(DDB_INTCTRL, 0);
ddb_out32(DDB_INTCTRL + 4, 0);
}
u16 nile4_get_irq_stat(int cpu_irq)
{
return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
}
void nile4_enable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t |= 1 << (16 + cpu_irq);
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_disable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t &= ~(1 << (16 + cpu_irq));
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (high)
t &= ~(1 << (pci_irq * 2));
else
t |= 1 << (pci_irq * 2);
ddb_out32(DDB_INTPPES, t);
}
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (level)
t |= 2 << (pci_irq * 2);
else
t &= ~(2 << (pci_irq * 2));
ddb_out32(DDB_INTPPES, t);
}
void nile4_clear_irq(int nile4_irq)
{
nile4_irq-=irq_base;
ddb_out32(DDB_INTCLR, 1 << nile4_irq);
}
void nile4_clear_irq_mask(u32 mask)
{
ddb_out32(DDB_INTCLR, mask);
}
u8 nile4_i8259_iack(void)
{
u8 irq;
u32 reg;
/* Set window 0 for interrupt acknowledge */
reg = ddb_in32(DDB_PCIINIT0);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
/* restore window 0 for PCI I/O space */
// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_out32(DDB_PCIINIT0, reg);
/* i8269.c set the base vector to be 0x0 */
return irq ;
}
static unsigned int nile4_irq_startup(unsigned int irq) {
nile4_enable_irq(irq);
return 0;
}
static void nile4_ack_irq(unsigned int irq) {
ddb5074_led_hex(4);
nile4_clear_irq(irq);
ddb5074_led_hex(2);
nile4_disable_irq(irq);
ddb5074_led_hex(0);
}
static void nile4_irq_end(unsigned int irq) {
ddb5074_led_hex(3);
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
ddb5074_led_hex(5);
nile4_enable_irq(irq);
ddb5074_led_hex(7);
}
ddb5074_led_hex(1);
}
#define nile4_irq_shutdown nile4_disable_irq
static hw_irq_controller nile4_irq_controller = {
"nile4",
nile4_irq_startup,
nile4_irq_shutdown,
nile4_enable_irq,
nile4_disable_irq,
nile4_ack_irq,
nile4_irq_end,
NULL
};
void nile4_irq_setup(u32 base) {
int i;
extern irq_desc_t irq_desc[];
irq_base=base;
/* Map all interrupts to CPU int #0 */
nile4_map_irq_all(0);
/* PCI INTA#-E# must be level triggered */
nile4_set_pci_irq_level_or_edge(0, 1);
nile4_set_pci_irq_level_or_edge(1, 1);
nile4_set_pci_irq_level_or_edge(2, 1);
nile4_set_pci_irq_level_or_edge(3, 1);
nile4_set_pci_irq_level_or_edge(4, 1);
/* PCI INTA#-D# must be active low, INTE# must be active high */
nile4_set_pci_irq_polarity(0, 0);
nile4_set_pci_irq_polarity(1, 0);
nile4_set_pci_irq_polarity(2, 0);
nile4_set_pci_irq_polarity(3, 0);
nile4_set_pci_irq_polarity(4, 1);
for (i = 0; i < 16; i++) {
nile4_clear_irq(i);
nile4_disable_irq(i);
}
/* Enable CPU int #0 */
nile4_enable_irq_output(0);
for (i= base; i< base + NUM_NILE4_INTERRUPTS; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &nile4_irq_controller;
}
}
#if defined(CONFIG_RUNTIME_DEBUG)
void nile4_dump_irq_status(void)
{
printk(KERN_DEBUG "
CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
(void *) ddb_in32(DDB_CPUSTAT));
printk(KERN_DEBUG "
INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
(void *) ddb_in32(DDB_INTCTRL));
printk(KERN_DEBUG
"INTSTAT0 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT0 + 4),
(void *) ddb_in32(DDB_INTSTAT0));
printk(KERN_DEBUG
"INTSTAT1 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT1 + 4),
(void *) ddb_in32(DDB_INTSTAT1));
printk(KERN_DEBUG
"INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
(void *) ddb_in32(DDB_INTCLR));
printk(KERN_DEBUG
"INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
(void *) ddb_in32(DDB_INTPPES));
}
#endif
arch/mips/ddb5074/setup.c → arch/mips/ddb5xxx/ddb5074/setup.c
View file @ 3ad349a5
......@@ -13,21 +13,23 @@
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/pc_keyb.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/keyboard.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/time.h>
#include <asm/nile4.h>
#include <asm/ddb5074.h>
#include <asm/ddb5xxx/ddb5074.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
#endif
......@@ -37,6 +39,7 @@ extern void console_setup(char *);
#endif
extern struct ide_ops std_ide_ops;
extern struct kbd_ops std_kbd_ops;
extern struct rtc_ops ddb_rtc_ops;
static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
......@@ -72,11 +75,11 @@ static void ddb_machine_power_off(void)
}
extern void ddb_irq_setup(void);
extern void rtc_ds1386_init(unsigned long base);
void (*board_time_init) (struct irqaction * irq);
extern void (*board_timer_setup) (struct irqaction * irq);
static void __init ddb_time_init(struct irqaction *irq)
static void __init ddb_timer_init(struct irqaction *irq)
{
/* set the clock to 1 Hz */
nile4_out32(NILE4_T2CTRL, 1000000);
......@@ -85,26 +88,32 @@ static void __init ddb_time_init(struct irqaction *irq)
/* reset timer */
nile4_out32(NILE4_T2CNTR, 0);
/* enable interrupt */
nile4_enable_irq(NILE4_INT_GPT);
i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
change_cp0_status(ST0_IM,
setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
nile4_enable_irq(nile4_to_irq(NILE4_INT_GPT));
change_c0_status(ST0_IM,
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
}
static void __init ddb_time_init(void)
{
/* we have ds1396 RTC chip */
rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
}
void __init ddb_setup(void)
{
extern int panic_timeout;
irq_setup = ddb_irq_setup;
mips_io_port_base = NILE4_PCI_IO_BASE;
set_io_port_base(NILE4_PCI_IO_BASE);
isa_slot_offset = NILE4_PCI_MEM_BASE;
request_region(0x00, 0x20, "dma1");
request_region(0x40, 0x20, "timer");
request_region(0x70, 0x10, "rtc");
request_region(0x80, 0x10, "dma page reg");
request_region(0xc0, 0x20, "dma2");
board_timer_setup = ddb_timer_init;
board_time_init = ddb_time_init;
_machine_restart = ddb_machine_restart;
_machine_halt = ddb_machine_halt;
_machine_power_off = ddb_machine_power_off;
......@@ -112,8 +121,18 @@ void __init ddb_setup(void)
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
#endif
rtc_ops = &ddb_rtc_ops;
ddb_out32(DDB_BAR0, 0);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, 0x10);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE , 0x10);
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
/* Reboot on panic */
panic_timeout = 180;
}
......
arch/mips/ddb5074/time.c → arch/mips/ddb5xxx/ddb5074/time.c
View file @ 3ad349a5
......@@ -3,21 +3,22 @@
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
*/
#include <linux/init.h>
#include <asm/mc146818rtc.h>
#include <asm/ddb5xxx/ddb5074.h>
#include <asm/ddb5xxx/ddb5xxx.h>
static unsigned char ddb_rtc_read_data(unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
return inb_p(RTC_PORT(1));
return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
}
static void ddb_rtc_write_data(unsigned char data, unsigned long addr)
{
outb_p(addr, RTC_PORT(0));
outb_p(data, RTC_PORT(1));
*(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr)=data;
}
static int ddb_rtc_bcd_mode(void)
......
arch/mips/ddb5xxx/ddb5476/Makefile 0 → 100644
View file @ 3ad349a5
#
# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
# under Linux.
#
obj-y += setup.o irq.o int-handler.o nile4_pic.o vrc5476_irq.o
obj-$(CONFIG_KGDB) += dbg_io.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/ddb5476/dbg_io.c → arch/mips/ddb5xxx/ddb5476/dbg_io.c
View file @ 3ad349a5
/*
* kgdb io functions for DDB5476. We use the second serial port.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/* ======================= CONFIG ======================== */
#include <linux/config.h>
/* [jsun] we use the second serial port for kdb */
#define BASE 0xa60002f8
#define MAX_BAUD 115200
/* distance in bytes between two serial registers */
#define REG_OFFSET 1
#if (defined(CONFIG_DDB5476) && defined(CONFIG_REMOTE_DEBUG))
/*
* 0 - kgdb does serial init
* 1 - kgdb skip serial init
*/
static int remoteDebugInitialized = 0;
/*
* the default baud rate *if* kgdb does serial init
*/
#define BAUD_DEFAULT UART16550_BAUD_38400
/* --- CONFIG --- */
/* ======================= END OF CONFIG ======================== */
/* we need uint32 uint8 */
/* #include "types.h" */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
......@@ -34,33 +58,23 @@ typedef unsigned int uint32;
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE 0xa60002f8
#define MAX_BAUD 115200
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE 1
#define OFS_INTR_ID 2
#define OFS_DATA_FORMAT 3
#define OFS_LINE_CONTROL 3
#define OFS_MODEM_CONTROL 4
#define OFS_RS232_OUTPUT 4
#define OFS_LINE_STATUS 5
#define OFS_MODEM_STATUS 6
#define OFS_RS232_INPUT 6
#define OFS_SCRATCH_PAD 7
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB 0
#define OFS_DIVISOR_MSB 1
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
......@@ -69,57 +83,54 @@ typedef unsigned int uint32;
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_9600,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/ddb5xxx/ddb5476/int-handler.S 0 → 100644
View file @ 3ad349a5
/*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* First-level interrupt dispatcher for ddb5476
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/ddb5xxx/ddb5476.h>
/*
* first level interrupt dispatcher for ocelot board -
* We check for the timer first, then check PCI ints A and D.
* Then check for serial IRQ and fall through.
*/
.align 5
NESTED(ddb5476_handle_int, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
.set noreorder
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cpu_ip7
andi t1, t0, STATUSF_IP2 /* vrc5476 & i8259 */
bnez t1, ll_cpu_ip2
andi t1, t0, STATUSF_IP3
bnez t1, ll_cpu_ip3
andi t1, t0, STATUSF_IP4
bnez t1, ll_cpu_ip4
andi t1, t0, STATUSF_IP5
bnez t1, ll_cpu_ip5
andi t1, t0, STATUSF_IP6
bnez t1, ll_cpu_ip6
andi t1, t0, STATUSF_IP0 /* software int 0 */
bnez t1, ll_cpu_ip0
andi t1, t0, STATUSF_IP1 /* software int 1 */
bnez t1, ll_cpu_ip1
nop
.set reorder
/* wrong alarm or masked ... */
// j spurious_interrupt
move a0, sp
jal vrc5476_irq_dispatch
j ret_from_irq
nop
.align 5
ll_cpu_ip0:
li a0, CPU_IRQ_BASE + 0
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip1:
li a0, CPU_IRQ_BASE + 1
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip2: /* jump to second-level dispatching */
move a0, sp
jal vrc5476_irq_dispatch
j ret_from_irq
ll_cpu_ip3:
li a0, CPU_IRQ_BASE + 3
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip4:
li a0, CPU_IRQ_BASE + 4
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip5:
li a0, CPU_IRQ_BASE + 5
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip6:
li a0, CPU_IRQ_BASE + 6
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip7:
li a0, CPU_IRQ_BASE + 7
move a1, sp
jal do_IRQ
j ret_from_irq
END(ddb5476_handle_int)
arch/mips/ddb5476/irq.c → arch/mips/ddb5xxx/ddb5476/irq.c
View file @ 3ad349a5
......@@ -3,33 +3,22 @@
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Re-write the whole thing to use new irq.c file.
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/nile4.h>
extern void __init i8259_init(void);
extern void i8259_disable_irq(unsigned int irq_nr);
extern void i8259_enable_irq(unsigned int irq_nr);
extern asmlinkage void ddbIRQ(void);
extern asmlinkage void i8259_do_irq(int irq, struct pt_regs *regs);
extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
void no_action(int cpl, void *dev_id, struct pt_regs *regs)
{
}
#include <asm/ddb5xxx/ddb5xxx.h>
#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
......@@ -48,16 +37,6 @@ void no_action(int cpl, void *dev_id, struct pt_regs *regs)
#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
static struct {
struct resource m1543_config;
struct resource pic_elcr;
} m1543_ioport = {
{ "M1543 config", M1543_PNP_CONFIG, M1543_PNP_CONFIG + 1,
IORESOURCE_BUSY},
{ "pic ELCR", M1543_INT1_MASTER_ELCR, M1543_INT1_MASTER_ELCR + 1,
IORESOURCE_BUSY}
};
static void m1543_irq_setup(void)
{
/*
......@@ -67,9 +46,9 @@ static void m1543_irq_setup(void)
*
* IRQ1 - keyboard (default set by M1543)
* IRQ3 - reserved for UART B (default set by M1543) (note that
* the schematics for the DDB Vrc-5476 board seem to
* indicate that IRQ3 is connected to the DS1386
* watchdog timer interrupt output so we might have
* the schematics for the DDB Vrc-5476 board seem to
* indicate that IRQ3 is connected to the DS1386
* watchdog timer interrupt output so we might have
* a conflict)
* IRQ4 - reserved for UART A (default set by M1543)
* IRQ5 - parallel (default set by M1543)
......@@ -81,7 +60,7 @@ static void m1543_irq_setup(void)
*/
/*
* Assing mouse interrupt to IRQ12
* Assing mouse interrupt to IRQ12
*/
/* Enter configuration mode */
......@@ -98,27 +77,13 @@ static void m1543_irq_setup(void)
/* Leave configration mode */
outb(0xbb, M1543_PNP_CONFIG);
/* Initialize the 8259 PIC in the M1543 */
i8259_init();
/* Enable the interrupt cascade from M1543 */
nile4_enable_irq(NILE4_INT_INTC);
/* request io ports */
if (request_resource(&ioport_resource, &m1543_ioport.m1543_config)
|| request_resource(&ioport_resource, &m1543_ioport.pic_elcr)) {
printk("m1543_irq_setup : requesting io ports failed.\n");
for (;;);
}
}
static void nile4_irq_setup(void)
{
int i;
/* Map all interrupts to CPU int #0 */
/* Map all interrupts to CPU int #0 (IP2) */
nile4_map_irq_all(0);
/* PCI INTA#-E# must be level triggered */
......@@ -142,110 +107,37 @@ static void nile4_irq_setup(void)
/* memory resource acquire in ddb_setup */
}
static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
static struct irqaction irq_error = { no_action, 0, 0, "error", NULL, NULL };
/*
* IRQ2 is cascade interrupt to second interrupt controller
*/
static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL };
void disable_irq(unsigned int irq_nr)
{
if (is_i8259_irq(irq_nr))
i8259_disable_irq(irq_nr);
else
nile4_disable_irq(irq_to_nile4(irq_nr));
}
void enable_irq(unsigned int irq_nr)
{
if (is_i8259_irq(irq_nr))
i8259_enable_irq(irq_nr);
else
nile4_enable_irq(irq_to_nile4(irq_nr));
}
int table[16] = { 0, };
void ddb_local0_irqdispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
#if 0
volatile static int nesting = 0;
if (nesting++ == 0)
ddb5476_led_d3(1);
ddb5476_led_hex(nesting < 16 ? nesting : 15);
#endif
mask = nile4_get_irq_stat(0);
nile4_clear_irq_mask(mask);
/* Handle the timer interrupt first */
if (mask & (1 << NILE4_INT_GPT)) {
nile4_disable_irq(NILE4_INT_GPT);
do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
nile4_enable_irq(NILE4_INT_GPT);
mask &= ~(1 << NILE4_INT_GPT);
}
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
if (mask & 1) {
nile4_disable_irq(nile4_irq);
if (nile4_irq == NILE4_INT_INTC) {
int i8259_irq = nile4_i8259_iack();
i8259_do_irq(i8259_irq, regs);
} else {
do_IRQ(nile4_to_irq(nile4_irq), regs);
}
nile4_enable_irq(nile4_irq);
}
#if 0
if (--nesting == 0)
ddb5476_led_d3(0);
ddb5476_led_hex(nesting < 16 ? nesting : 15);
#endif
}
void ddb_local1_irqdispatch(void)
{
printk("ddb_local1_irqdispatch called\n");
}
void ddb_buserror_irq(void)
{
printk("ddb_buserror_irq called\n");
}
void ddb_8254timer_irq(void)
{
printk("ddb_8254timer_irq called\n");
}
void ddb_phantom_irq(unsigned long cause)
{
printk("phantom interrupts detected : \n");
printk("\tcause \t\t0x%08x\n", cause);
printk("\tcause reg\t0x%08x\n",
read_32bit_cp0_register(CP0_CAUSE));
printk("\tstatus reg\t0x%08x\n",
read_32bit_cp0_register(CP0_STATUS));
}
extern asmlinkage void ddb5476_handle_int(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);
extern void vrc5476_irq_init(u32 irq_base);
void __init ddb_irq_setup(void)
void __init ddb5476_irq_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
printk("Wait for gdb client connection ...\n");
set_debug_traps();
breakpoint(); /* you may move this line to whereever you want :-) */
#endif
i8259_setup_irq(2, &irq2);
/* hardware initialization */
nile4_irq_setup();
m1543_irq_setup();
/* we pin #0 - #4 (no internal timer) */
change_cp0_status(ST0_IM,
IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
set_except_vector(0, ddbIRQ);
/* controller setup */
init_i8259_irqs();
vrc5476_irq_init(VRC5476_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
/* setup cascade interrupts */
setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
/* setup error interrupts for debugging */
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
/* setup the grandpa intr vector */
set_except_vector(0, ddb5476_handle_int);
}
arch/mips/ddb5xxx/ddb5476/nile4_pic.c 0 → 100644
View file @ 3ad349a5
/*
* arch/mips/ddb5476/nile4.c --
* low-level PIC code for NEC Vrc-5476 (Nile 4)
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* Interrupt Programming
*/
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(7 << (nile4_irq * 4));
t |= cpu_irq << (nile4_irq * 4);
ddb_out32(offset, t);
}
void nile4_map_irq_all(int cpu_irq)
{
u32 all, t;
all = cpu_irq;
all |= all << 4;
all |= all << 8;
all |= all << 16;
t = ddb_in32(DDB_INTCTRL);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL, t);
t = ddb_in32(DDB_INTCTRL + 4);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL + 4, t);
}
void nile4_enable_irq(int nile4_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t |= 8 << (nile4_irq * 4);
ddb_out32(offset, t);
}
void nile4_disable_irq(int nile4_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(8 << (nile4_irq * 4));
ddb_out32(offset, t);
}
void nile4_disable_irq_all(void)
{
ddb_out32(DDB_INTCTRL, 0);
ddb_out32(DDB_INTCTRL + 4, 0);
}
u16 nile4_get_irq_stat(int cpu_irq)
{
return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
}
void nile4_enable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t |= 1 << (16 + cpu_irq);
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_disable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t &= ~(1 << (16 + cpu_irq));
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (high)
t &= ~(1 << (pci_irq * 2));
else
t |= 1 << (pci_irq * 2);
ddb_out32(DDB_INTPPES, t);
}
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (level)
t |= 2 << (pci_irq * 2);
else
t &= ~(2 << (pci_irq * 2));
ddb_out32(DDB_INTPPES, t);
}
void nile4_clear_irq(int nile4_irq)
{
ddb_out32(DDB_INTCLR, 1 << nile4_irq);
}
void nile4_clear_irq_mask(u32 mask)
{
ddb_out32(DDB_INTCLR, mask);
}
u8 nile4_i8259_iack(void)
{
u8 irq;
u32 reg;
/* Set window 0 for interrupt acknowledge */
reg = ddb_in32(DDB_PCIINIT0);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
/* restore window 0 for PCI I/O space */
// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_out32(DDB_PCIINIT0, reg);
/* i8269.c set the base vector to be 0x0 */
return irq + I8259_IRQ_BASE;
}
#if defined(CONFIG_RUNTIME_DEBUG)
void nile4_dump_irq_status(void)
{
printk(KERN_DEBUG "
CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
(void *) ddb_in32(DDB_CPUSTAT));
printk(KERN_DEBUG "
INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
(void *) ddb_in32(DDB_INTCTRL));
printk(KERN_DEBUG
"INTSTAT0 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT0 + 4),
(void *) ddb_in32(DDB_INTSTAT0));
printk(KERN_DEBUG
"INTSTAT1 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT1 + 4),
(void *) ddb_in32(DDB_INTSTAT1));
printk(KERN_DEBUG
"INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
(void *) ddb_in32(DDB_INTCLR));
printk(KERN_DEBUG
"INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
(void *) ddb_in32(DDB_INTPPES));
}
#endif
arch/mips/ddb5476/setup.c → arch/mips/ddb5xxx/ddb5476/setup.c
View file @ 3ad349a5
......@@ -13,31 +13,37 @@
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/pc_keyb.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/keyboard.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/nile4.h>
#include <asm/time.h>
#include <asm/debug.h>
#include <asm/traps.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#ifdef CONFIG_REMOTE_DEBUG
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
#ifdef USE_CPU_COUNTER_TIMER
#define CPU_COUNTER_FREQUENCY 83000000
#else
/* otherwise we use general purpose timer */
#define TIMER_FREQUENCY 83000000
#define TIMER_BASE DDB_T2CTRL
#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
#endif
#if defined(CONFIG_SERIAL_CONSOLE)
extern void console_setup(char *);
#ifdef CONFIG_KGDB
extern void breakpoint(void);
#endif
extern struct ide_ops std_ide_ops;
extern struct rtc_ops ddb_rtc_ops;
extern struct kbd_ops std_kbd_ops;
static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
......@@ -47,59 +53,62 @@ static void ddb_machine_restart(char *command)
u32 t;
/* PCI cold reset */
t = nile4_in32(NILE4_PCICTRL + 4);
t = ddb_in32(DDB_PCICTRL + 4);
t |= 0x40000000;
nile4_out32(NILE4_PCICTRL + 4, t);
ddb_out32(DDB_PCICTRL + 4, t);
/* CPU cold reset */
t = nile4_in32(NILE4_CPUSTAT);
t = ddb_in32(DDB_CPUSTAT);
t |= 1;
nile4_out32(NILE4_CPUSTAT, t);
ddb_out32(DDB_CPUSTAT, t);
/* Call the PROM */
back_to_prom();
}
static void ddb_machine_halt(void)
{
printk("DDB Vrc-5476 halted.\n");
printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
while (1);
}
static void ddb_machine_power_off(void)
{
printk("DDB Vrc-5476 halted. Please turn off the power.\n");
printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
while (1);
}
extern void ddb_irq_setup(void);
extern void rtc_ds1386_init(unsigned long base);
static void __init ddb_time_init(struct irqaction *irq)
static void __init ddb_time_init(void)
{
printk("ddb_time_init invoked.\n");
mips_counter_frequency = 83000000;
#if defined(USE_CPU_COUNTER_TIMER)
mips_counter_frequency = CPU_COUNTER_FREQUENCY;
#endif
/* we have ds1396 RTC chip */
rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
#if defined(USE_CPU_COUNTER_TIMER)
unsigned int count;
/* we are using the cpu counter for timer interrupts */
i8259_setup_irq(0, irq);
set_cp0_status(IE_IRQ5);
setup_irq(CPU_IRQ_BASE + 7, irq);
/* to generate the first timer interrupt */
count = read_32bit_cp0_register(CP0_COUNT);
write_32bit_cp0_register(CP0_COMPARE, count + 1000);
#if 0 /* the old way to do timer interrupt */
/* set the clock to 100 Hz */
nile4_out32(NILE4_T2CTRL, 830000);
/* enable the General-Purpose Timer */
nile4_out32(NILE4_T2CTRL + 4, 0x00000001);
/* reset timer */
nile4_out32(NILE4_T2CNTR, 0);
/* enable interrupt */
nile4_enable_irq(NILE4_INT_GPT);
i8259_setup_irq(nile4_to_irq(NILE4_INT_GPT), irq);
count = read_c0_count();
write_c0_compare(count + 1000);
#else
ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
setup_irq(TIMER_IRQ, irq);
#endif
}
......@@ -125,16 +134,21 @@ static struct {
static struct {
struct resource nile4;
} ddb5476_iomem = {
{ "Nile 4", NILE4_BASE, NILE4_BASE + NILE4_SIZE - 1, IORESOURCE_BUSY}
{ "Nile 4", DDB_BASE, DDB_BASE + DDB_SIZE - 1, IORESOURCE_BUSY}
};
void __init ddb_setup(void)
static void ddb5476_board_init(void);
extern void ddb5476_irq_setup(void);
extern void (*irq_setup)(void);
void __init
ddb_setup(void)
{
extern int panic_timeout;
irq_setup = ddb_irq_setup;
mips_io_port_base = NILE4_PCI_IO_BASE;
isa_slot_offset = NILE4_PCI_MEM_BASE;
irq_setup = ddb5476_irq_setup;
set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
board_time_init = ddb_time_init;
board_timer_setup = ddb_timer_setup;
......@@ -160,11 +174,6 @@ void __init ddb_setup(void)
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
#endif
rtc_ops = &ddb_rtc_ops;
#ifdef CONFIG_PC_KEYB
kbd_ops = &std_kbd_ops;
#endif
/* Reboot on panic */
panic_timeout = 180;
......@@ -176,19 +185,74 @@ void __init ddb_setup(void)
conswitchp = &dummy_con;
#endif
/* board initialization stuff */
ddb5476_board_init();
}
/* board initialization stuff - non-fundamental, but need to be set
* before kernel runs */
/*
* We don't trust bios. We essentially does hardware re-initialization
* as complete as possible, as far as we know we can safely do.
*/
static void ddb5476_board_init(void)
{
/* ----------- setup PDARs ------------ */
/* check SDRAM0, whether we are on MEM bus does not matter */
db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
/* SDRAM1 should be turned off. What is this for anyway ? */
db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
/* flash 1&2, DDB status, DDB control */
ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
/* shut off other pdar so they don't accidentally get into the way */
ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
/* verify VRC5477 base addr */
/* don't care about some details */
db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
/* verify BOOT ROM addr */
/* don't care about some details */
db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
/* setup PCI windows - window1 for MEM/config, window0 for IO */
ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
/* ----------- setup PDARs ------------ */
/* this is problematic - it will reset Aladin which cause we loose
* serial port, and we don't know how to set up Aladin chip again.
*/
// ddb_pci_reset_bus();
/* setup I/O space */
nile4_set_pdar(NILE4_PCIW0,
PHYSADDR(NILE4_PCI_IO_BASE), 0x02000000, 32, 0, 0);
nile4_set_pmr(NILE4_PCIINIT0, NILE4_PCICMD_IO, 0);
ddb_out32(DDB_BAR0, 0x00000008);
/* map config space to 0xa8000000, 128MB */
nile4_set_pdar(NILE4_PCIW1,
PHYSADDR(NILE4_PCI_CFG_BASE), 0x08000000, 32, 0, 0);
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, 0x0);
ddb_out32(DDB_BARC, 0xffffffff);
ddb_out32(DDB_BARB, 0xffffffff);
ddb_out32(DDB_BAR1, 0xffffffff);
ddb_out32(DDB_BAR2, 0xffffffff);
ddb_out32(DDB_BAR3, 0xffffffff);
ddb_out32(DDB_BAR4, 0xffffffff);
ddb_out32(DDB_BAR5, 0xffffffff);
ddb_out32(DDB_BAR6, 0xffffffff);
ddb_out32(DDB_BAR7, 0xffffffff);
ddb_out32(DDB_BAR8, 0xffffffff);
/* ----------- switch PCI1 to PCI CONFIG space ------------ */
ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
/* ----- M1543 PCI setup ------ */
......@@ -200,9 +264,9 @@ void __init ddb_setup(void)
/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
* no IOCHRDY signal, (bit 7 - 1)
* M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
* Bypass USB Master INTAJ level to edge conversion (bit 4 - 0)
* Make USB Master INTAJ level to edge conversion (bit 4 - 1)
*/
*(unsigned char *) 0xa8040074 = 0xc1;
*(unsigned char *) 0xa8040074 = 0xd1;
/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
* SCI routing to IRQ 13 disabled (bit 7 - 1)
......@@ -256,138 +320,7 @@ void __init ddb_setup(void)
/* ----- end of reset on-board ether chip ------ */
/* ----- set pci window 1 to pci memory space -------- */
nile4_set_pdar(NILE4_PCIW1,
PHYSADDR(NILE4_PCI_MEM_BASE), 0x08000000, 32, 0, 0);
// nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0x08000000);
}
#define USE_NILE4_SERIAL 0
#if USE_NILE4_SERIAL
#define ns16550_in(reg) nile4_in8((reg)*8)
#define ns16550_out(reg, val) nile4_out8((reg)*8, (val))
#else
#define NS16550_BASE (NILE4_PCI_IO_BASE+0x03f8)
static inline u8 ns16550_in(u32 reg)
{
return *(volatile u8 *) (NS16550_BASE + reg);
}
static inline void ns16550_out(u32 reg, u8 val)
{
*(volatile u8 *) (NS16550_BASE + reg) = val;
}
#endif
#define NS16550_RBR 0
#define NS16550_THR 0
#define NS16550_DLL 0
#define NS16550_IER 1
#define NS16550_DLM 1
#define NS16550_FCR 2
#define NS16550_IIR 2
#define NS16550_LCR 3
#define NS16550_MCR 4
#define NS16550_LSR 5
#define NS16550_MSR 6
#define NS16550_SCR 7
#define NS16550_LSR_DR 0x01 /* Data ready */
#define NS16550_LSR_OE 0x02 /* Overrun */
#define NS16550_LSR_PE 0x04 /* Parity error */
#define NS16550_LSR_FE 0x08 /* Framing error */
#define NS16550_LSR_BI 0x10 /* Break */
#define NS16550_LSR_THRE 0x20 /* Xmit holding register empty */
#define NS16550_LSR_TEMT 0x40 /* Xmitter empty */
#define NS16550_LSR_ERR 0x80 /* Error */
void _serinit(void)
{
#if USE_NILE4_SERIAL
ns16550_out(NS16550_LCR, 0x80);
ns16550_out(NS16550_DLM, 0x00);
ns16550_out(NS16550_DLL, 0x36); /* 9600 baud */
ns16550_out(NS16550_LCR, 0x00);
ns16550_out(NS16550_LCR, 0x03);
ns16550_out(NS16550_FCR, 0x47);
#else
/* done by PMON */
#endif
}
void _putc(char c)
{
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
ns16550_out(NS16550_THR, c);
if (c == '\n') {
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_THRE));
ns16550_out(NS16550_THR, '\r');
}
}
void _puts(const char *s)
{
char c;
while ((c = *s++))
_putc(c);
}
char _getc(void)
{
while (!(ns16550_in(NS16550_LSR) & NS16550_LSR_DR));
return ns16550_in(NS16550_RBR);
}
int _testc(void)
{
return (ns16550_in(NS16550_LSR) & NS16550_LSR_DR) != 0;
}
/*
* Hexadecimal 7-segment LED
*/
void ddb5476_led_hex(int hex)
{
outb(hex, 0x80);
}
/*
* LEDs D2 and D3, connected to the GPIO pins of the PMU in the ALi M1543
*/
struct pci_dev *pci_pmu = NULL;
void ddb5476_led_d2(int on)
{
u8 t;
if (pci_pmu) {
pci_read_config_byte(pci_pmu, 0x7e, &t);
if (on)
t &= 0x7f;
else
t |= 0x80;
pci_write_config_byte(pci_pmu, 0x7e, t);
}
}
void ddb5476_led_d3(int on)
{
u8 t;
if (pci_pmu) {
pci_read_config_byte(pci_pmu, 0x7e, &t);
if (on)
t &= 0xbf;
else
t |= 0x40;
pci_write_config_byte(pci_pmu, 0x7e, t);
}
/* ----------- switch PCI1 back to PCI MEM space ------------ */
ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
}
arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c 0 → 100644
View file @ 3ad349a5
/*
* The irq controller for vrc5476.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/system.h>
#include <asm/ddb5xxx/ddb5xxx.h>
static int irq_base;
static void vrc5476_irq_enable(uint irq)
{
nile4_enable_irq(irq - irq_base);
}
static void vrc5476_irq_disable(uint irq)
{
nile4_disable_irq(irq - irq_base);
}
static unsigned int vrc5476_irq_startup(uint irq)
{
nile4_enable_irq(irq - irq_base);
return 0;
}
#define vrc5476_irq_shutdown vrc5476_irq_disable
static void vrc5476_irq_ack(uint irq)
{
nile4_clear_irq(irq - irq_base);
nile4_disable_irq(irq - irq_base);
}
static void vrc5476_irq_end(uint irq)
{
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
vrc5476_irq_enable(irq);
}
static hw_irq_controller vrc5476_irq_controller = {
"vrc5476",
vrc5476_irq_startup,
vrc5476_irq_shutdown,
vrc5476_irq_enable,
vrc5476_irq_disable,
vrc5476_irq_ack,
vrc5476_irq_end,
NULL /* no affinity stuff for UP */
};
void __init
vrc5476_irq_init(u32 base)
{
extern irq_desc_t irq_desc[];
u32 i;
irq_base = base;
for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &vrc5476_irq_controller;
}
}
asmlinkage void
vrc5476_irq_dispatch(struct pt_regs *regs)
{
extern void spurious_interrupt(void);
u32 mask;
int nile4_irq;
mask = nile4_get_irq_stat(0);
/* quick check for possible time interrupt */
if (mask & (1 << VRC5476_IRQ_GPT)) {
do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
return;
}
/* check for i8259 interrupts */
if (mask & (1 << VRC5476_I8259_CASCADE)) {
int i8259_irq = nile4_i8259_iack();
do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
return;
}
/* regular nile4 interrupts (we should not really have any */
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
if (mask & 1) {
do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
return;
}
}
spurious_interrupt();
}
arch/mips/ddb5xxx/ddb5477/Makefile
View file @ 3ad349a5
......@@ -2,10 +2,9 @@
# Makefile for NEC DDB-Vrc5477 board
#
EXTRA_AFLAGS := $(CFLAGS)
obj-y += int-handler.o irq.o irq_5477.o setup.o lcd44780.o
obj-y += int-handler.o irq.o irq_5477.o setup.o pci.o pci_ops.o
obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
obj-$(CONFIG_KGDB) += kgdb_io.o
obj-$(CONFIG_LL_DEBUG) += debug.o
obj-$(CONFIG_REMOTE_DEBUG) += kgdb_io.o
obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/ddb5xxx/ddb5477/debug.c
View file @ 3ad349a5
......@@ -15,8 +15,6 @@
*/
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/signal.h> /* SA_INTERRUPT */
#include <asm/mipsregs.h>
#include <asm/ddb5xxx/ddb5xxx.h>
......@@ -32,9 +30,9 @@ void jsun_show_regs(char *name, Register *regs)
printk("\nshow regs: %s\n", name);
for(i=0;regs[i].regname!= NULL; i++) {
printk("%-16s= %08x\t\t(@%08x)\n",
regs[i].regname,
*(unsigned *)(regs[i].regaddr),
printk("%-16s= %08x\t\t(@%08x)\n",
regs[i].regname,
*(unsigned *)(regs[i].regaddr),
regs[i].regaddr);
}
}
......@@ -58,15 +56,15 @@ static Register int_regs[] = {
void vrc5477_show_int_regs()
{
jsun_show_regs("interrupt registers", int_regs);
printk("CPU CAUSE = %08x\n", read_32bit_cp0_register(CP0_CAUSE));
printk("CPU STATUS = %08x\n", read_32bit_cp0_register(CP0_STATUS));
printk("CPU CAUSE = %08x\n", read_c0_cause());
printk("CPU STATUS = %08x\n", read_c0_status());
}
static Register pdar_regs[] = {
{"DDB_SDRAM0", DDB_BASE + DDB_SDRAM0},
{"DDB_SDRAM1", DDB_BASE + DDB_SDRAM1},
{"DDB_LDCS0", DDB_BASE + DDB_LDCS0},
{"DDB_LDCS1", DDB_BASE + DDB_LDCS1},
{"DDB_LDCS2", DDB_BASE + DDB_LDCS2},
{"DDB_LCS0", DDB_BASE + DDB_LCS0},
{"DDB_LCS1", DDB_BASE + DDB_LCS1},
{"DDB_LCS2", DDB_BASE + DDB_LCS2},
{"DDB_INTCS", DDB_BASE + DDB_INTCS},
{"DDB_BOOTCS", DDB_BASE + DDB_BOOTCS},
{"DDB_PCIW0", DDB_BASE + DDB_PCIW0},
......
arch/mips/ddb5xxx/ddb5477/int-handler.S
View file @ 3ad349a5
......@@ -9,13 +9,12 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/ddb5xxx/ddb5477.h>
/*
* first level interrupt dispatcher for ocelot board -
......@@ -28,14 +27,14 @@
CLI
.set at
.set noreorder
mfc0 t0, CP0_CAUSE
mfc0 t0, CP0_CAUSE
mfc0 t2, CP0_STATUS
and t0, t2
andi t1, t0, STATUSF_IP7 /* cpu timer */
bnez t1, ll_cputimer_irq
andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
andi t1, t0, (STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6 )
bnez t1, ll_vrc5477_irq
andi t1, t0, STATUSF_IP0 /* software int 0 */
bnez t1, ll_cpu_ip0
......@@ -51,26 +50,26 @@
.align 5
ll_vrc5477_irq:
ll_vrc5477_irq:
move a0, sp
jal vrc5477_irq_dispatch
j ret_from_irq
ll_cputimer_irq:
li a0, 7
li a0, CPU_IRQ_BASE + 7
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip0:
li a0, 0
ll_cpu_ip0:
li a0, CPU_IRQ_BASE + 0
move a1, sp
jal do_IRQ
j ret_from_irq
ll_cpu_ip1:
li a0, 1
ll_cpu_ip1:
li a0, CPU_IRQ_BASE + 1
move a1, sp
jal do_IRQ
j ret_from_irq
arch/mips/ddb5xxx/ddb5477/irq.c
View file @ 3ad349a5
......@@ -12,16 +12,20 @@
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/i8259.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/debug.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
#include <asm/ddb5xxx/debug.h>
/*
* IRQ mapping
......@@ -37,7 +41,7 @@
* 7 - cpu timer (used by default)
*
* 8-39: 32 Vrc5477 interrupt sources
* (refer to the Vrc5477 manual)
* (refer to the Vrc5477 manual)
*/
#define PCI0 DDB_INTPPES0
......@@ -55,7 +59,7 @@
#define INTD 3
#define INTE 4
static inline void
static inline void
set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
{
u32 reg_value;
......@@ -63,7 +67,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
reg_value = ddb_in32(pci);
reg_bitmask = 0x3 << (intn * 2);
reg_value &= ~reg_bitmask;
reg_value |= (active | trigger) << (intn * 2);
ddb_out32(pci, reg_value);
......@@ -72,26 +76,31 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
extern void vrc5477_irq_init(u32 base);
extern void mips_cpu_irq_init(u32 base);
extern asmlinkage void ddb5477_handle_int(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
void
ddb5477_irq_setup(void)
{
MIPS_DEBUG(printk("ddb5477_irq_setup invoked.\n"));
db_run(printk("ddb5477_irq_setup invoked.\n"));
/* by default, we disable all interrupts and route all vrc5477
/* by default, we disable all interrupts and route all vrc5477
* interrupts to pin 0 (irq 2) */
ddb_out32(DDB_INTCTRL0, 0);
ddb_out32(DDB_INTCTRL1, 0);
ddb_out32(DDB_INTCTRL2, 0);
ddb_out32(DDB_INTCTRL3, 0);
clear_cp0_status(0xff00);
set_cp0_status(0x0400);
clear_c0_status(0xff00);
set_c0_status(0x0400);
/* setup PCI interrupt attributes */
set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
if (mips_machtype == MACH_NEC_ROCKHOPPERII)
set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
else
set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);
......@@ -101,9 +110,9 @@ ddb5477_irq_setup(void)
set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);
/*
/*
* for debugging purpose, we enable several error interrupts
* and route them to pin 1. (IP3)
* and route them to pin 1. (IP3)
*/
/* cpu parity check - 0 */
ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
......@@ -121,13 +130,34 @@ ddb5477_irq_setup(void)
ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);
/* init all controllers */
mips_cpu_irq_init(0);
vrc5477_irq_init(8);
init_i8259_irqs();
mips_cpu_irq_init(CPU_IRQ_BASE);
vrc5477_irq_init(VRC5477_IRQ_BASE);
/* setup cascade interrupts */
setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
/* hook up the first-level interrupt handler */
set_except_vector(0, ddb5477_handle_int);
}
u8 i8259_interrupt_ack(void)
{
u8 irq;
u32 reg;
/* Set window 0 for interrupt acknowledge */
reg = ddb_in32(DDB_PCIINIT10);
ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
ddb_out32(DDB_PCIINIT10, reg);
/* i8259.c set the base vector to be 0x0 */
return irq + I8259_IRQ_BASE;
}
/*
* the first level int-handler will jump here if it is a vrc5477 irq
*/
......@@ -135,29 +165,38 @@ ddb5477_irq_setup(void)
asmlinkage void
vrc5477_irq_dispatch(struct pt_regs *regs)
{
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
u32 intStatus;
u32 bitmask;
u32 i;
MIPS_ASSERT(ddb_in32(DDB_INT2STAT) == 0);
MIPS_ASSERT(ddb_in32(DDB_INT3STAT) == 0);
MIPS_ASSERT(ddb_in32(DDB_INT4STAT) == 0);
MIPS_ASSERT(ddb_in32(DDB_NMISTAT) == 0);
db_assert(ddb_in32(DDB_INT2STAT) == 0);
db_assert(ddb_in32(DDB_INT3STAT) == 0);
db_assert(ddb_in32(DDB_INT4STAT) == 0);
db_assert(ddb_in32(DDB_NMISTAT) == 0);
if (ddb_in32(DDB_INT1STAT) != 0) {
#if defined(CONFIG_LL_DEBUG)
#if defined(CONFIG_RUNTIME_DEBUG)
vrc5477_show_int_regs();
#endif
panic("error interrupt has happened.\n");
panic("error interrupt has happened.");
}
intStatus = ddb_in32(DDB_INT0STAT);
if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
/* check for i8259 interrupts */
if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
int i8259_irq = i8259_interrupt_ack();
do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
return;
}
}
for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
/* do we need to "and" with the int mask? */
if (intStatus & bitmask) {
do_IRQ(8 + i, regs);
do_IRQ(VRC5477_IRQ_BASE + i, regs);
return;
}
}
}
arch/mips/ddb5xxx/ddb5477/irq_5477.c
View file @ 3ad349a5
/***********************************************************************
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
......@@ -9,7 +9,7 @@
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*
*/
/*
......@@ -19,37 +19,36 @@
* vrc5477_irq_init(u32 irq_base);
*/
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/debug.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
#include <asm/ddb5xxx/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/* number of total irqs supported by Vrc5477 */
#define NUM_5477_IRQ 32
static int vrc5477_irq_base=-1;
static int vrc5477_irq_base = -1;
static void
static void
vrc5477_irq_enable(unsigned int irq)
{
MIPS_ASSERT(vrc5477_irq_base != -1);
MIPS_ASSERT(irq >= vrc5477_irq_base);
MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
}
static void
static void
vrc5477_irq_disable(unsigned int irq)
{
MIPS_ASSERT(vrc5477_irq_base != -1);
MIPS_ASSERT(irq >= vrc5477_irq_base);
MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
}
......@@ -65,9 +64,9 @@ static unsigned int vrc5477_irq_startup(unsigned int irq)
static void
vrc5477_irq_ack(unsigned int irq)
{
MIPS_ASSERT(vrc5477_irq_base != -1);
MIPS_ASSERT(irq >= vrc5477_irq_base);
MIPS_ASSERT(irq < vrc5477_irq_base+ NUM_5477_IRQ);
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
/* clear the interrupt bit */
/* some irqs require the driver to clear the sources */
......@@ -82,11 +81,12 @@ vrc5477_irq_ack(unsigned int irq)
static void
vrc5477_irq_end(unsigned int irq)
{
MIPS_ASSERT(vrc5477_irq_base != -1);
MIPS_ASSERT(irq >= vrc5477_irq_base);
MIPS_ASSERT(irq < vrc5477_irq_base + NUM_5477_IRQ);
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
}
hw_irq_controller vrc5477_irq_controller = {
......@@ -100,7 +100,7 @@ hw_irq_controller vrc5477_irq_controller = {
NULL /* no affinity stuff for UP */
};
void
void
vrc5477_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
......@@ -112,17 +112,8 @@ vrc5477_irq_init(u32 irq_base)
irq_desc[i].depth = 1;
irq_desc[i].handler = &vrc5477_irq_controller;
}
vrc5477_irq_base = irq_base;
}
int vrc5477_irq_to_irq(int irq)
{
MIPS_ASSERT(irq >= 0);
MIPS_ASSERT(irq < NUM_5477_IRQ);
return irq + vrc5477_irq_base;
vrc5477_irq_base = irq_base;
}
void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
......@@ -131,10 +122,10 @@ void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
u32 reg_bitmask;
u32 reg_index;
MIPS_ASSERT(vrc5477_irq >= 0);
MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
MIPS_ASSERT(ip >= 0);
MIPS_ASSERT((ip < 5) || (ip == 6));
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
db_assert(ip >= 0);
db_assert((ip < 5) || (ip == 6));
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
......@@ -150,13 +141,13 @@ void ll_vrc5477_irq_enable(int vrc5477_irq)
u32 reg_bitmask;
u32 reg_index;
MIPS_ASSERT(vrc5477_irq >= 0);
MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
MIPS_ASSERT((reg_value & reg_bitmask) == 0);
db_assert((reg_value & reg_bitmask) == 0);
ddb_out32(reg_index, reg_value | reg_bitmask);
}
......@@ -166,14 +157,14 @@ void ll_vrc5477_irq_disable(int vrc5477_irq)
u32 reg_bitmask;
u32 reg_index;
MIPS_ASSERT(vrc5477_irq >= 0);
MIPS_ASSERT(vrc5477_irq < NUM_5477_IRQ);
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
/* we assert that the interrupt is enabled (perhaps over-zealous) */
MIPS_ASSERT( (reg_value & reg_bitmask) != 0);
db_assert( (reg_value & reg_bitmask) != 0);
ddb_out32(reg_index, reg_value & ~reg_bitmask);
}
arch/mips/ddb5xxx/ddb5477/kgdb_io.c
View file @ 3ad349a5
/*
* kgdb io functions for DDB5477. We use the second serial port (upper one).
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/* ======================= CONFIG ======================== */
#include <linux/config.h>
/* [jsun] we use the second serial port for kdb */
#define BASE 0xbfa04240
#define MAX_BAUD 115200
#if (defined(CONFIG_DDB5477) && defined(CONFIG_REMOTE_DEBUG))
/* distance in bytes between two serial registers */
#define REG_OFFSET 8
/* --- CONFIG --- */
/*
* 0 - kgdb does serial init
* 1 - kgdb skip serial init
*/
static int remoteDebugInitialized = 0;
/*
* the default baud rate *if* kgdb does serial init
*/
#define BAUD_DEFAULT UART16550_BAUD_38400
/* ======================= END OF CONFIG ======================== */
/* we need uint32 uint8 */
/* #include "types.h" */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
......@@ -34,21 +58,10 @@ typedef unsigned int uint32;
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE 0xbfa04240
#define MAX_BAUD 115200
#define REG_OFFSET 8
/* === END OF CONFIG === */
/* register offset */
#define OFS_RCV_BUFFER (0*REG_OFFSET)
#define OFS_TRANS_HOLD (0*REG_OFFSET)
#define OFS_SEND_BUFFER (0*REG_OFFSET)
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
......@@ -70,73 +83,54 @@ typedef unsigned int uint32;
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up buad rate */
{
uint32 divisor;
/* set up buad rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
int debug_state = -1;
uint8 getDebugChar(void)
{
uint8 c;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
c= UART16550_READ(OFS_RCV_BUFFER);
/*
if (state != 1) {
state = 1;
debug_out("\ngetDebugChar: ", 15);
}
debug_out(&c, 1);
*/
return c;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_9600,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
if (debug_state != 2) {
debug_state = 2;
// debug_out("\nputDebugChar: ", 15);
}
// debug_out(&byte, 1);
return 1;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/ddb5xxx/ddb5477/lcd44780.c 0 → 100644
View file @ 3ad349a5
/*
* lcd44780.c
* Simple "driver" for a memory-mapped 44780-style LCD display.
*
* Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#define LCD44780_COMMAND ((volatile unsigned char *)0xbe020000)
#define LCD44780_DATA ((volatile unsigned char *)0xbe020001)
#define LCD44780_4BIT_1LINE 0x20
#define LCD44780_4BIT_2LINE 0x28
#define LCD44780_8BIT_1LINE 0x30
#define LCD44780_8BIT_2LINE 0x38
#define LCD44780_MODE_DEC 0x04
#define LCD44780_MODE_DEC_SHIFT 0x05
#define LCD44780_MODE_INC 0x06
#define LCD44780_MODE_INC_SHIFT 0x07
#define LCD44780_SCROLL_LEFT 0x18
#define LCD44780_SCROLL_RIGHT 0x1e
#define LCD44780_CURSOR_UNDERLINE 0x0e
#define LCD44780_CURSOR_BLOCK 0x0f
#define LCD44780_CURSOR_OFF 0x0c
#define LCD44780_CLEAR 0x01
#define LCD44780_BLANK 0x08
#define LCD44780_RESTORE 0x0c // Same as CURSOR_OFF
#define LCD44780_HOME 0x02
#define LCD44780_LEFT 0x10
#define LCD44780_RIGHT 0x14
void lcd44780_wait(void)
{
int i, j;
for(i=0; i < 400; i++)
for(j=0; j < 10000; j++);
}
void lcd44780_command(unsigned char c)
{
*LCD44780_COMMAND = c;
lcd44780_wait();
}
void lcd44780_data(unsigned char c)
{
*LCD44780_DATA = c;
lcd44780_wait();
}
void lcd44780_puts(const char* s)
{
int i,j;
int pos = 0;
lcd44780_command(LCD44780_CLEAR);
while(*s) {
lcd44780_data(*s);
s++;
pos++;
if (pos == 8) {
/* We must write 32 of spaces to get cursor to 2nd line */
for (j=0; j<32; j++) {
lcd44780_data(' ');
}
}
if (pos == 16) {
/* We have filled all 16 character positions, so stop
outputing data */
break;
}
}
#ifdef LCD44780_PUTS_PAUSE
for(i = 1; i < 2000; i++)
lcd44780_wait();
#endif
}
void lcd44780_init(void)
{
// The display on the RockHopper is physically a single
// 16 char line (two 8 char lines concatenated). bdl
lcd44780_command(LCD44780_8BIT_2LINE);
lcd44780_command(LCD44780_MODE_INC);
lcd44780_command(LCD44780_CURSOR_BLOCK);
lcd44780_command(LCD44780_CLEAR);
}
arch/mips/ddb5xxx/ddb5477/lcd44780.h 0 → 100644
View file @ 3ad349a5
/*
* lcd44780.h
* Simple "driver" for a memory-mapped 44780-style LCD display.
*
* Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
void lcd44780_puts(const char* s);
void lcd44780_init(void);
arch/mips/ddb5xxx/ddb5477/pci.c deleted 100644 → 0
View file @ 320bcfc9
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#include <asm/ddb5xxx/debug.h>
#include <asm/ddb5xxx/pci.h>
static struct resource extpci_io_resource = {
"ext pci IO space",
DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE,
DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE -1,
IORESOURCE_IO};
static struct resource extpci_mem_resource = {
"ext pci memory space",
DDB_PCI0_MEM_BASE,
DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE -1,
IORESOURCE_MEM};
static struct resource iopci_io_resource = {
"io pci IO space",
DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE,
DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE -1,
IORESOURCE_IO};
static struct resource iopci_mem_resource = {
"ext pci memory space",
DDB_PCI1_MEM_BASE,
DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE -1,
IORESOURCE_MEM};
extern struct pci_ops ddb5477_ext_pci_ops;
extern struct pci_ops ddb5477_io_pci_ops;
struct pci_channel mips_pci_channels[] = {
{ &ddb5477_ext_pci_ops, &extpci_io_resource, &extpci_mem_resource },
{ &ddb5477_io_pci_ops, &iopci_io_resource, &iopci_mem_resource },
{ NULL, NULL, NULL}
};
/*
* we fix up irqs based on the slot number.
* The first entry is at AD:11.
* Fortunately this works because, although we have two pci buses,
* they all have different slot numbers.
*
* This does not work for devices on sub-buses.
*
* Note that the irq number in the array is relative number in vrc5477.
* We need to translate it to global irq number.
*/
/*
* irq mapping : PCI int # -> vrc5477 irq #
* based on vrc5477 manual page 46
*/
#define PCI_EXT_INTA 8
#define PCI_EXT_INTB 9
#define PCI_EXT_INTC 10
#define PCI_EXT_INTD 11
#define PCI_EXT_INTE 12
#define PCI_IO_INTA 16
#define PCI_IO_INTB 17
#define PCI_IO_INTC 18
#define PCI_IO_INTD 19
/*
* irq mapping : device -> pci int #,
* ddb5477 board manual page 4 and vrc5477 manual page 46
*/
#define INT_ONBOARD_TULIP PCI_EXT_INTA
#define INT_SLOT1 PCI_EXT_INTB
#define INT_SLOT2 PCI_EXT_INTC
#define INT_SLOT3 PCI_EXT_INTD
#define INT_SLOT4 PCI_EXT_INTE
#define INT_USB_HOST PCI_IO_INTA
#define INT_USB_PERI PCI_IO_INTB
#define INT_AC97 PCI_IO_INTC
/*
* based on ddb5477 manual page 11
*/
#define MAX_SLOT_NUM 21
static unsigned char irq_map[MAX_SLOT_NUM] = {
/* AD:11 */ 0xff, 0xff, 0xff, 0xff,
/* AD:15 */ INT_ONBOARD_TULIP, INT_SLOT1, INT_SLOT2, INT_SLOT3,
/* AD:19 */ INT_SLOT4, 0xff, 0xff, 0xff,
/* AD:23 */ 0xff, 0xff, 0xff, 0xff,
/* AD:27 */ 0xff, 0xff, INT_AC97, INT_USB_PERI,
/* AD:31 */ INT_USB_HOST
};
extern int vrc5477_irq_to_irq(int irq);
void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev = NULL;
int slot_num;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
slot_num = PCI_SLOT(dev->devfn);
MIPS_ASSERT(slot_num < MAX_SLOT_NUM);
MIPS_ASSERT(irq_map[slot_num] != 0xff);
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
irq_map[slot_num]);
dev->irq = vrc5477_irq_to_irq(irq_map[slot_num]);
}
}
#if defined(CONFIG_LL_DEBUG)
extern void jsun_scan_pci_bus(void);
extern void jsun_assign_pci_resource(void);
#endif
void __init ddb_pci_reset_bus(void)
{
u32 temp;
/*
* I am not sure about the "official" procedure, the following
* steps work as far as I know:
* We first set PCI cold reset bit (bit 31) in PCICTRL-H.
* Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
* The same is true for both PCI channels.
*/
temp = ddb_in32(DDB_PCICTL0_H);
temp |= 0x80000000;
ddb_out32(DDB_PCICTL0_H, temp);
temp &= ~0xc0000000;
ddb_out32(DDB_PCICTL0_H, temp);
temp = ddb_in32(DDB_PCICTL1_H);
temp |= 0x80000000;
ddb_out32(DDB_PCICTL1_H, temp);
temp &= ~0xc0000000;
ddb_out32(DDB_PCICTL1_H, temp);
}
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
arch/mips/ddb5xxx/ddb5477/pci_ops.c deleted 100644 → 0
View file @ 320bcfc9
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/ddb5xxx/ddb5477/pci_ops.c
* Define the pci_ops for DB5477.
*
* Much of the code is derived from the original DDB5074 port by
* Geert Uytterhoeven <geert@sonycom.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
/*
* DDB5477 has two PCI channels, external PCI and IOPIC (internal)
* Therefore we provide two sets of pci_ops.
*/
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/ddb5xxx/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* config_swap structure records what set of pdar/pmr are used
* to access pci config space. It also provides a place hold the
* original values for future restoring.
*/
struct pci_config_swap {
u32 pdar;
u32 pmr;
u32 config_base;
u32 config_size;
u32 pdar_backup;
u32 pmr_backup;
};
/*
* On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI.
*/
struct pci_config_swap ext_pci_swap = {
DDB_PCIW0,
DDB_PCIINIT00,
DDB_PCI0_CONFIG_BASE,
DDB_PCI0_CONFIG_SIZE
};
struct pci_config_swap io_pci_swap = {
DDB_IOPCIW0,
DDB_PCIINIT01,
DDB_PCI1_CONFIG_BASE,
DDB_PCI1_CONFIG_SIZE
};
/*
* access config space
*/
static inline u32 ddb_access_config_base(struct pci_config_swap *swap,
u32 bus,/* 0 means top level bus */
u32 slot_num)
{
u32 pci_addr = 0;
u32 pciinit_offset = 0;
u32 virt_addr = swap->config_base;
u32 option;
/* [jsun] hack for testing */
// if (slot_num == 4) slot_num = 0;
/* minimum pdar (window) size is 2MB */
MIPS_ASSERT(swap->config_size >= (2 << 20));
MIPS_ASSERT(slot_num < (1 << 5));
MIPS_ASSERT(bus < (1 << 8));
/* backup registers */
swap->pdar_backup = ddb_in32(swap->pdar);
swap->pmr_backup = ddb_in32(swap->pmr);
/* set the pdar (pci window) register */
ddb_set_pdar(swap->pdar,
swap->config_base,
swap->config_size,
32, /* 32 bit wide */
0, /* not on local memory bus */
0); /* not visible from PCI bus (N/A) */
/*
* calcuate the absolute pci config addr;
* according to the spec, we start scanning from adr:11 (0x800)
*/
if (bus == 0) {
/* type 0 config */
pci_addr = 0x800 << slot_num;
} else {
/* type 1 config */
pci_addr = (bus << 16) | (slot_num << 11);
panic("ddb_access_config_base: we don't support type 1 config Yet");
}
/*
* if pci_addr is less than pci config window size, we set
* pciinit_offset to 0 and adjust the virt_address.
* Otherwise we will try to adjust pciinit_offset.
*/
if (pci_addr < swap->config_size) {
virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
pciinit_offset = 0;
} else {
MIPS_ASSERT( (pci_addr & (swap->config_size - 1)) == 0);
virt_addr = KSEG1ADDR(swap->config_base);
pciinit_offset = pci_addr;
}
/* set the pmr register */
option = DDB_PCI_ACCESS_32;
if (bus != 0) option |= DDB_PCI_CFGTYPE1;
ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
return virt_addr;
}
static inline void ddb_close_config_base(struct pci_config_swap *swap)
{
ddb_out32(swap->pdar, swap->pdar_backup);
ddb_out32(swap->pmr, swap->pmr_backup);
}
static int read_config(struct pci_config_swap *swap,
struct pci_bus *bus,
unsigned int devfn,
u32 where,
int size,
u32 *val)
{
u32 busnum, slot_num, func_num, base, result;
int status
switch (size) {
case 4:
MIPS_ASSERT((where & 3) == 0);
MIPS_ASSERT(where < (1 << 8));
/* check if the bus is top-level */
if (bus->parent != NULL) {
busnum = bus->number;
MIPS_ASSERT(busnum != 0);
} else {
busnum = 0;
}
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
base = ddb_access_config_base(swap, busnum, slot_num);
*val = *(volatile u32*) (base + (func_num << 8) + where);
ddb_close_config_base(swap);
return PCIBIOS_SUCCESSFUL;
case 2:
MIPS_ASSERT((where & 1) == 0);
status = read_config(swap, bus, devfn, where & ~3, 4,
&result);
if (where & 2) result >>= 16;
*val = (u16)(result & 0xffff);
return status;
case 1:
status = read_config(swap, bus, devfn, where & ~3, 4,
&result);
if (where & 1) result >>= 8;
if (where & 2) result >>= 16;
*val = (u8)(result & 0xff);
return status;
}
}
static int write_config(struct pci_config_swap *swap,
struct pci_bus *bus,
unsigned int devfn,
u32 where,
int size,
u32 val)
{
u32 busnum, slot_num, func_num, base, results;
int status, shift = 0;
switch (size) {
case 4:
MIPS_ASSERT((where & 3) == 0);
MIPS_ASSERT(where < (1 << 8));
/* check if the bus is top-level */
if (bus->parent != NULL) {
busnum = bus->number;
MIPS_ASSERT(busnum != 0);
} else {
busnum = 0;
}
slot_num = PCI_SLOT(devfn);
func_num = PCI_FUNC(devfn);
base = ddb_access_config_base(swap, busnum, slot_num);
*(volatile u32*) (base + (func_num << 8) + where) = val;
ddb_close_config_base(swap);
return PCIBIOS_SUCCESSFUL;
case 2:
MIPS_ASSERT((where & 1) == 0);
status = read_config(swap, bus, devfn, where & ~3, 4,
&result);
if (status != PCIBIOS_SUCCESSFUL) return status;
if (where & 2)
shift += 16;
result &= ~(0xffff << shift);
result |= (u16)(val << shift);
return write_config(swap, bus, devfn, where & ~3, size,
result);
case 1:
status = read_config(swap, bus, devfn, where & ~3, 4,
&result);
if (status != PCIBIOS_SUCCESSFUL) return status;
if (where & 2)
shift += 16;
if (where & 1)
shift += 8;
result &= ~(0xff << shift);
result |= (u8)(val << shift);
return write_config(swap, bus, devfn, where & ~3, size,
result);
}
}
#define MAKE_PCI_OPS(prefix, rw, pciswap) \
static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, \
int where, int size, u32 val) \
{ \
return rw##_config(pciswap, bus, devfn, \
where, size, val); \
}
MAKE_PCI_OPS(extpci, read, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, &ext_pci_swap)
MAKE_PCI_OPS(iopci, read, &io_pci_swap)
MAKE_PCI_OPS(iopci, write, &io_pci_swap)
struct pci_ops ddb5477_ext_pci_ops ={
.read = extpci_read_config,
.write = extpci_write_config,
};
struct pci_ops ddb5477_io_pci_ops ={
.read = iopci_read_config,
.write = iopci_write_config,
};
#if defined(CONFIG_LL_DEBUG)
void jsun_scan_pci_bus(void)
{
struct pci_bus bus;
struct pci_dev dev;
unsigned int devfn;
int j;
bus.parent = NULL; /* we scan the top level only */
dev.bus = &bus;
dev.sysdata = NULL;
/* scan ext pci bus and io pci bus*/
for (j=0; j< 2; j++) {
if (j == 0) {
printk("scan ddb5477 external PCI bus:\n");
bus.ops = &ddb5477_ext_pci_ops;
} else {
printk("scan ddb5477 IO PCI bus:\n");
bus.ops = &ddb5477_io_pci_ops;
}
for (devfn = 0; devfn < 0x100; devfn += 8) {
u32 temp;
u16 temp16;
u8 temp8;
int i;
dev.devfn = devfn;
MIPS_VERIFY(pci_read_config_dword(&dev, 0, &temp),
== PCIBIOS_SUCCESSFUL);
if (temp == 0xffffffff) continue;
printk("slot %d: (addr %d) \n", devfn/8, 11+devfn/8);
/* verify read word and byte */
MIPS_VERIFY(pci_read_config_word(&dev, 2, &temp16),
== PCIBIOS_SUCCESSFUL);
MIPS_ASSERT(temp16 == (temp >> 16));
MIPS_VERIFY(pci_read_config_byte(&dev, 3, &temp8),
== PCIBIOS_SUCCESSFUL);
MIPS_ASSERT(temp8 == (temp >> 24));
MIPS_VERIFY(pci_read_config_byte(&dev, 1, &temp8),
== PCIBIOS_SUCCESSFUL);
MIPS_ASSERT(temp8 == ((temp >> 8) & 0xff));
for (i=0; i < 16; i++) {
MIPS_VERIFY(pci_read_config_dword(&dev, i*4, &temp),
== PCIBIOS_SUCCESSFUL);
printk("\t%08X", temp);
if ((i%4) == 3) printk("\n");
}
}
}
}
static void jsun_hardcode_pci_resources_eepro(void)
{
struct pci_bus bus;
struct pci_dev dev;
u32 temp;
bus.parent = NULL; /* we scan the top level only */
bus.ops = &ddb5477_ext_pci_ops;
dev.bus = &bus;
dev.sysdata = NULL;
/* for slot 5 (ext pci 1) eepro card */
dev.devfn = 5*8;
pci_read_config_dword(&dev, 0, &temp);
MIPS_ASSERT(temp == 0x12298086);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, DDB_PCI0_MEM_BASE);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_2, DDB_PCI0_MEM_BASE+0x100000);
pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 17);
}
static void jsun_hardcode_pci_resources_onboard_tulip(void)
{
struct pci_bus bus;
struct pci_dev dev;
u32 temp;
bus.parent = NULL; /* we scan the top level only */
bus.ops = &ddb5477_ext_pci_ops;
dev.bus = &bus;
dev.sysdata = NULL;
/* for slot 4 on board ether chip */
dev.devfn = 4*8;
pci_read_config_dword(&dev, 0, &temp);
MIPS_ASSERT(temp == 0x00191011);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_0, 0x1000);
pci_write_config_dword(&dev, PCI_BASE_ADDRESS_1, DDB_PCI0_MEM_BASE);
pci_write_config_dword(&dev, PCI_INTERRUPT_LINE, 16);
}
static void jsun_hardcode_pci_resources(void)
{
jsun_hardcode_pci_resources_onboard_tulip();
}
void jsun_assign_pci_resource(void)
{
jsun_hardcode_pci_resources();
}
#endif
arch/mips/ddb5xxx/ddb5477/setup.c
View file @ 3ad349a5
/***********************************************************************
/*
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
......@@ -10,14 +10,10 @@
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
......@@ -26,29 +22,35 @@
#include <linux/fs.h>
#include <linux/ioport.h>
#include <linux/param.h> /* for HZ */
#include <linux/major.h>
#include <linux/kdev_t.h>
#include <linux/root_dev.h>
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/time.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/traps.h>
#include <asm/debug.h>
#ifdef CONFIG_PC_KEYB
#include <asm/keyboard.h>
#endif
#include <asm/ddb5xxx/ddb5xxx.h>
#include "lcd44780.h"
#define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
#ifdef USE_CPU_COUNTER_TIMER
#define CPU_COUNTER_FREQUENCY 83000000
#else
/* otherwise we use special timer 1 */
#define SP_TIMER_FREQUENCY 83000000
#define SP_TIMER_BASE DDB_SPT1CTRL_L
#define SP_TIMER_IRQ (8 + 6)
#endif
#define SP_TIMER_IRQ VRC5477_IRQ_SPT1
static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
static void ddb_machine_restart(char *command)
{
......@@ -61,7 +63,7 @@ static void ddb_machine_restart(char *command)
/* CPU cold reset */
t = ddb_in32(DDB_CPUSTAT);
MIPS_ASSERT((t&1));
db_assert((t&1));
ddb_out32(DDB_CPUSTAT, t);
/* Call the PROM */
......@@ -81,44 +83,89 @@ static void ddb_machine_power_off(void)
}
extern void rtc_ds1386_init(unsigned long base);
static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
{
unsigned int freq;
unsigned char c;
unsigned int t1, t2;
unsigned i;
ddb_out32(SP_TIMER_BASE, 0xffffffff);
ddb_out32(SP_TIMER_BASE+4, 0x1);
ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
/* check if rtc is running */
c= *(volatile unsigned char*)rtc_base;
for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
if (c == *(volatile unsigned char*)rtc_base) {
printk("Failed to detect bus frequency. Use default 83.3MHz.\n");
return 83333000;
}
c= *(volatile unsigned char*)rtc_base;
while (c == *(volatile unsigned char*)rtc_base);
/* we are now at the turn of 1/100th second, if no error. */
t1 = ddb_in32(SP_TIMER_BASE+8);
for (i=0; i< 10; i++) {
c= *(volatile unsigned char*)rtc_base;
while (c == *(volatile unsigned char*)rtc_base);
/* we are now at the turn of another 1/100th second */
t2 = ddb_in32(SP_TIMER_BASE+8);
}
ddb_out32(SP_TIMER_BASE+4, 0x0); /* disable it again */
freq = (t1 - t2)*10;
printk("DDB bus frequency detection : %u \n", freq);
return freq;
}
static void __init ddb_time_init(void)
{
#if defined(USE_CPU_COUNTER_TIMER)
mips_counter_frequency = CPU_COUNTER_FREQUENCY;
#endif
unsigned long rtc_base;
unsigned int i;
/* we have ds1396 RTC chip */
rtc_ds1386_init(KSEG1ADDR(DDB_LCS1_BASE));
if (mips_machtype == MACH_NEC_ROCKHOPPER
|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
} else {
rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
}
rtc_ds1386_init(rtc_base);
/* do we need to do run-time detection of bus speed? */
if (bus_frequency == 0) {
bus_frequency = detect_bus_frequency(rtc_base);
}
/* mips_counter_frequency is 1/2 of the cpu core freq */
i = (read_32bit_cp0_register(CP0_CONFIG) >> 28 ) & 7;
if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
i = 4;
mips_counter_frequency = bus_frequency*(i+4)/4;
}
#if defined(CONFIG_LL_DEBUG)
int board_init_done_flag = 0;
#endif
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
#if defined(USE_CPU_COUNTER_TIMER)
unsigned int count;
/* we are using the cpu counter for timer interrupts */
setup_irq(7, irq);
/* to generate the first timer interrupt */
count = read_32bit_cp0_register(CP0_COUNT);
write_32bit_cp0_register(CP0_COMPARE, count + 1000);
setup_irq(CPU_IRQ_BASE + 7, irq);
#else
/* if we don't use Special purpose timer 1 */
ddb_out32(SP_TIMER_BASE, SP_TIMER_FREQUENCY/HZ);
/* if we use Special purpose timer 1 */
ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
ddb_out32(SP_TIMER_BASE+4, 0x1);
setup_irq(SP_TIMER_IRQ, irq);
#endif
/* this is the last board dependent code */
MIPS_DEBUG(board_init_done_flag = 1);
}
static void ddb5477_board_init(void);
......@@ -126,14 +173,20 @@ extern void ddb5477_irq_setup(void);
#if defined(CONFIG_BLK_DEV_INITRD)
extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
#endif
#endif
void __init ddb_setup(void)
{
extern int panic_timeout;
#ifdef CONFIG_BLK_DEV_IDE
extern struct ide_ops std_ide_ops;
#endif
/* initialize board - we don't trust the loader */
ddb5477_board_init();
irq_setup = ddb5477_irq_setup;
mips_io_port_base = KSEG1ADDR(DDB_PCI_IO_BASE);
set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
board_time_init = ddb_time_init;
board_timer_setup = ddb_timer_setup;
......@@ -145,47 +198,69 @@ void __init ddb_setup(void)
/* setup resource limits */
ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
iomem_resource.end = 0xffffffff;
/* Reboot on panic */
panic_timeout = 180;
/* initialize board - we don't trust the loader */
ddb5477_board_init();
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
#endif
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
#if defined(CONFIG_BLK_DEV_INITRD)
ROOT_DEV = Root_RAM0;
initrd_start = (unsigned long)&__rd_start;
initrd_end = (unsigned long)&__rd_end;
#endif
}
static void __init ddb5477_board_init()
static void __init ddb5477_board_init(void)
{
#ifdef CONFIG_PC_KEYB
extern struct kbd_ops std_kbd_ops;
#endif
/* ----------- setup PDARs ------------ */
/* SDRAM should have been set */
MIPS_ASSERT(ddb_in32(DDB_SDRAM0) ==
ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
db_assert(ddb_in32(DDB_SDRAM0) ==
ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
/* SDRAM1 should be turned off. What is this for anyway ? */
MIPS_ASSERT( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
/* Set LDCSs */
/* flash */
/* Setup local bus. */
/* Flash U12 PDAR and timing. */
ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
/* misc */
ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
/* mezzanie (?) */
ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
ddb_out32(DDB_LCST0, 0x00090842);
/* We need to setup LCS1 and LCS2 differently based on the
board_version */
if (mips_machtype == MACH_NEC_ROCKHOPPER) {
/* Flash U13 PDAR and timing. */
ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
ddb_out32(DDB_LCST1, 0x00090842);
/* EPLD (NVRAM, switch, LCD, and mezzanie). */
ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
} else {
/* misc */
ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
/* mezzanie (?) */
ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
}
/* verify VRC5477 base addr */
MIPS_ASSERT(ddb_in32(DDB_VRC5477) ==
ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
db_assert(ddb_in32(DDB_VRC5477) ==
ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
/* verify BOOT ROM addr */
MIPS_ASSERT(ddb_in32(DDB_BOOTCS) ==
ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
db_assert(ddb_in32(DDB_BOOTCS) ==
ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
/* setup PCI windows - window0 for MEM/config, window1 for IO */
ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
......@@ -219,7 +294,7 @@ static void __init ddb5477_board_init()
ddb_out32(DDB_BAR51, 0xffffffff);
ddb_out32(DDB_BARB1, 0xffffffff);
/*
/*
* We use pci master register 0 for memory space / config space
* And we use register 1 for IO space.
* Note that for memory space, we bump up the pci base address
......@@ -227,26 +302,133 @@ static void __init ddb5477_board_init()
* For PCI IO space, it starts from 0 in PCI IO space but with
* DDB_xx_IO_BASE in CPU physical address space.
*/
ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
DDB_PCI_ACCESS_32);
ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
DDB_PCI_ACCESS_32);
ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
DDB_PCI_ACCESS_32);
/* PCI cross window should be set properly */
ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
if (mips_machtype == MACH_NEC_ROCKHOPPER
|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
/* Disable bus diagnostics. */
ddb_out32(DDB_PCICTL0_L, 0);
ddb_out32(DDB_PCICTL0_H, 0);
ddb_out32(DDB_PCICTL1_L, 0);
ddb_out32(DDB_PCICTL1_H, 0);
}
if (mips_machtype == MACH_NEC_ROCKHOPPER) {
u16 vid;
struct pci_bus bus;
struct pci_dev dev_m1533;
extern struct pci_ops ddb5477_ext_pci_ops;
bus.parent = NULL; /* we scan the top level only */
bus.ops = &ddb5477_ext_pci_ops;
dev_m1533.bus = &bus;
dev_m1533.sysdata = NULL;
dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
pci_read_config_word(&dev_m1533, 0, &vid);
if (vid == PCI_VENDOR_ID_AL) {
printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
mips_machtype = MACH_NEC_ROCKHOPPERII;
}
}
/* enable USB input buffers */
ddb_out32(DDB_PIBMISC, 0x00000007);
/* For dual-function pins, make them all non-GPIO */
ddb_out32(DDB_GIUFUNSEL, 0x0);
// ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff); /* NEC recommanded value */
if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
#ifdef CONFIG_PC_KEYB
printk("kdb_ops is std\n");
kbd_ops = &std_kbd_ops;
#endif
}
if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
/* enable IDE controller on Ali chip (south bridge) */
u8 temp8;
struct pci_bus bus;
struct pci_dev dev_m1533;
struct pci_dev dev_m5229;
extern struct pci_ops ddb5477_ext_pci_ops;
/* Setup M1535 registers */
bus.parent = NULL; /* we scan the top level only */
bus.ops = &ddb5477_ext_pci_ops;
dev_m1533.bus = &bus;
dev_m1533.sysdata = NULL;
dev_m1533.devfn = 7*8; // slot 7: M1533 SouthBridge.
/* setup IDE controller
* enable IDE controller (bit 6 - 1)
* IDE IDSEL to be addr:A15 (bit 4:5 - 11)
* disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
* enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
*/
pci_write_config_byte(&dev_m1533, 0x58, 0x74);
/*
* positive decode (bit6 -0)
* enable IDE controler interrupt (bit 4 -1)
* setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
*/
pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
/* Setup M5229 registers */
dev_m5229.bus = &bus;
dev_m5229.sysdata = NULL;
dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
/*
* enable IDE in the M5229 config register 0x50 (bit 0 - 1)
* M5229 IDSEL is addr:15; see above setting
*/
pci_read_config_byte(&dev_m5229, 0x50, &temp8);
pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
/*
* enable bus master (bit 2) and IO decoding (bit 0)
*/
pci_read_config_byte(&dev_m5229, 0x04, &temp8);
pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
/*
* enable native, copied from arch/ppc/k2boot/head.S
* TODO - need volatile, need to be portable
*/
pci_write_config_byte(&dev_m5229, 0x09, 0xef);
/* Set Primary Channel Command Block Timing */
pci_write_config_byte(&dev_m5229, 0x59, 0x31);
/*
* Enable primary channel 40-pin cable
* M5229 register 0x4a (bit 0)
*/
pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
}
if (mips_machtype == MACH_NEC_ROCKHOPPER
|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
printk("lcd44780: initializing\n");
lcd44780_init();
lcd44780_puts("MontaVista Linux");
}
}
arch/mips/defconfig-ddb5476
View file @ 3ad349a5
......@@ -2,98 +2,122 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
CONFIG_DDB5476=y
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_ISA=y
CONFIG_PCI=y
CONFIG_PC_KEYB=y
CONFIG_ROTTEN_IRQ=y
CONFIG_I8259=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_DDB5XXX_COMMON=y
CONFIG_NEW_PCI=y
CONFIG_FB=y
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
CONFIG_NEW_TIME_C=y
CONFIG_EISA=y
# CONFIG_I8259 is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
CONFIG_CPU_R5432=y
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_PCI_NAMES is not set
CONFIG_PCI=y
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
#
# Plug and Play configuration
# Executable file formats
#
# CONFIG_PNP is not set
# CONFIG_ISAPNP is not set
# CONFIG_PNPBIOS is not set
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
#
# Memory Technology Devices (MTD)
......@@ -105,40 +129,94 @@ CONFIG_SYSCTL=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
#
# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_TASKFILE_IO=y
#
# IDE chipset support/bugfixes
#
# CONFIG_BLK_DEV_IDEPCI is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
......@@ -148,22 +226,27 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -176,84 +259,9 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
#
CONFIG_IDE=y
#
# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD_IDE is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_BLK_DEV_IDECS is not set
# CONFIG_BLK_DEV_IDECD is not set
# CONFIG_BLK_DEV_IDETAPE is not set
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_BLK_DEV_IDESCSI is not set
#
# IDE chipset support/bugfixes
#
# CONFIG_BLK_DEV_CMD640 is not set
# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
# CONFIG_BLK_DEV_ISAPNP is not set
# CONFIG_BLK_DEV_RZ1000 is not set
# CONFIG_IDEPCI_SHARE_IRQ is not set
# CONFIG_BLK_DEV_IDEDMA_PCI is not set
# CONFIG_BLK_DEV_OFFBOARD is not set
# CONFIG_IDEDMA_PCI_AUTO is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
# CONFIG_BLK_DEV_AEC62XX is not set
# CONFIG_AEC62XX_TUNING is not set
# CONFIG_BLK_DEV_ALI15X3 is not set
# CONFIG_WDC_ALI15X3 is not set
# CONFIG_BLK_DEV_AMD74XX is not set
# CONFIG_AMD74XX_OVERRIDE is not set
# CONFIG_BLK_DEV_CMD64X is not set
# CONFIG_BLK_DEV_CY82C693 is not set
# CONFIG_BLK_DEV_CS5530 is not set
# CONFIG_BLK_DEV_HPT34X is not set
# CONFIG_HPT34X_AUTODMA is not set
# CONFIG_BLK_DEV_HPT366 is not set
# CONFIG_BLK_DEV_NS87415 is not set
# CONFIG_BLK_DEV_OPTI621 is not set
# CONFIG_BLK_DEV_PDC202XX is not set
# CONFIG_PDC202XX_BURST is not set
# CONFIG_PDC202XX_FORCE is not set
# CONFIG_BLK_DEV_SVWKS is not set
# CONFIG_BLK_DEV_SIS5513 is not set
# CONFIG_BLK_DEV_TRM290 is not set
# CONFIG_BLK_DEV_VIA82CXXX is not set
# CONFIG_IDE_CHIPSETS is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_ATARAID is not set
# CONFIG_BLK_DEV_ATARAID_PDC is not set
# CONFIG_BLK_DEV_ATARAID_HPT is not set
#
# SCSI support
#
# CONFIG_SCSI is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
......@@ -264,70 +272,43 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_MII is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_AT1700 is not set
# CONFIG_DEPCA is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_AC3200 is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set
# CONFIG_TULIP_MMIO is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
CONFIG_EEPRO100=y
# CONFIG_LNE390 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
CONFIG_NE2K_PCI=y
# CONFIG_NE3210 is not set
# CONFIG_ES3210 is not set
# CONFIG_8139TOO is not set
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_LAN_SAA9730 is not set
# CONFIG_NET_POCKET is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -337,10 +318,8 @@ CONFIG_NE2K_PCI=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -362,22 +341,67 @@ CONFIG_NE2K_PCI=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
# CONFIG_VT_CONSOLE is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -387,39 +411,35 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
CONFIG_MOUSE=y
CONFIG_PSMOUSE=y
# CONFIG_82C710_MOUSE is not set
# CONFIG_PC110_PAD is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -427,245 +447,166 @@ CONFIG_PSMOUSE=y
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_V4 is not set
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Console drivers
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
#
# Frame-buffer support
# Graphics support
#
CONFIG_FB=y
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FB_RIVA is not set
# CONFIG_FB_CLGEN is not set
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_E1355 is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_SIS is not set
CONFIG_FB_3DFX=y
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_E1356 is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FBCON_ADVANCED is not set
CONFIG_FBCON_CFB8=y
CONFIG_FBCON_CFB16=y
CONFIG_FBCON_CFB32=y
# CONFIG_FBCON_FONTWIDTH8_ONLY is not set
# CONFIG_FBCON_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
# Console display driver support
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
#
# USB Multimedia devices
# Logo configuration
#
# CONFIG_LOGO is not set
#
# Video4Linux support is needed for USB Multimedia device support
# Sound
#
# CONFIG_USB_DABUSB is not set
# CONFIG_SOUND is not set
#
# USB Network adaptors
# USB support
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# USB port drivers
# Bluetooth support
#
# CONFIG_USB_USS720 is not set
# CONFIG_BT is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_CRYPTO is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_GDB_CONSOLE is not set
# CONFIG_LL_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
arch/mips/defconfig-ddb5477
View file @ 3ad349a5
......@@ -2,90 +2,123 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
CONFIG_DDB5477=y
CONFIG_DDB5477_BUS_FREQUENCY=0
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_I8259=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_PCI=y
CONFIG_NEW_TIME_C=y
CONFIG_NEW_IRQ=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_I8259 is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
CONFIG_IRQ_CPU=y
CONFIG_DUMMY_KEYB=y
CONFIG_DDB5XXX_COMMON=y
CONFIG_NEW_PCI=y
# CONFIG_FB is not set
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
CONFIG_CPU_R5432=y
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_PCI=y
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
#
# Memory Technology Devices (MTD)
......@@ -97,40 +130,72 @@ CONFIG_SYSCTL=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
......@@ -140,22 +205,27 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
#
# SCTP Configuration (EXPERIMENTAL)
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -168,27 +238,9 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
# CONFIG_SCSI is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
......@@ -199,67 +251,43 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_MII is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set
# CONFIG_TULIP_MMIO is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
# CONFIG_EEPRO100 is not set
# CONFIG_LNE390 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NE3210 is not set
# CONFIG_ES3210 is not set
# CONFIG_8139TOO is not set
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_LAN_SAA9730 is not set
# CONFIG_NET_POCKET is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -269,10 +297,8 @@ CONFIG_TULIP=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -294,22 +320,67 @@ CONFIG_TULIP=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Input Device Drivers
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_UNIX98_PTYS is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
......@@ -317,36 +388,35 @@ CONFIG_SERIAL_CONSOLE=y
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -354,213 +424,167 @@ CONFIG_SERIAL_CONSOLE=y
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
CONFIG_AUTOFS4_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
# CONFIG_DEVPTS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Sound
# Graphics support
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
# Sound
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
CONFIG_SOUND=y
#
# USB Multimedia devices
# Advanced Linux Sound Architecture
#
# CONFIG_SND is not set
#
# Video4Linux support is needed for USB Multimedia device support
# Open Sound System
#
# CONFIG_USB_DABUSB is not set
CONFIG_SOUND_PRIME=y
# CONFIG_SOUND_BT878 is not set
# CONFIG_SOUND_CMPCI is not set
# CONFIG_SOUND_EMU10K1 is not set
# CONFIG_SOUND_FUSION is not set
# CONFIG_SOUND_CS4281 is not set
# CONFIG_SOUND_ES1370 is not set
# CONFIG_SOUND_ES1371 is not set
# CONFIG_SOUND_ESSSOLO1 is not set
# CONFIG_SOUND_MAESTRO is not set
# CONFIG_SOUND_MAESTRO3 is not set
# CONFIG_SOUND_ICH is not set
# CONFIG_SOUND_RME96XX is not set
# CONFIG_SOUND_SONICVIBES is not set
CONFIG_SOUND_VRC5477=y
# CONFIG_SOUND_TRIDENT is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_VIA82CXXX is not set
# CONFIG_SOUND_OSS is not set
#
# USB Network adaptors
# USB support
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# USB port drivers
# Bluetooth support
#
# CONFIG_USB_USS720 is not set
# CONFIG_BT is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_CRYPTO is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_GDB_CONSOLE is not set
CONFIG_LL_DEBUG=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
include/asm-mips/ddb5xxx/ddb5074.h 0 → 100644
View file @ 3ad349a5
/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#ifndef _ASM_DDB5XXX_DDB5074_H
#define _ASM_DDB5XXX_DDB5074_H
#include <asm/nile4.h>
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
#define NILE4_PCI_IO_BASE 0xa6000000
#define NILE4_PCI_MEM_BASE 0xa8000000
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
#define CPU_NILE4_CASCADE 2
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
extern void nile4_irq_setup(u32 base);
#endif
include/asm-mips/ddb5xxx/ddb5476.h 0 → 100644
View file @ 3ad349a5
/*
* header file specific for ddb5476
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
/* aliases */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5476 - 16 sources
*
* They connected as follows:
* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
* all i2869 are routed to INTC in vrc5476 (by hardware connection)
*
* All VRC5476 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5476_IRQ 16
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
/*
* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
*/
#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
#define VRC5476_IRQ_CNTD 1 /* cpu no target */
#define VRC5476_IRQ_MCE 2 /* memory check error */
#define VRC5476_IRQ_DMA 3 /* DMA */
#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
#define VRC5476_IRQ_GPT 6 /* general purpose timer */
#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
#define VRC5476_IRQ_PCI 15 /* PCI internal error */
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 0
#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
#define I8259_IRQ_CASCADE 2
#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A 4 /* M1543 default */
#define I8259_IRQ_PARALLEL 5 /* M1543 default */
#define I8259_IRQ_RESERVED_6 6
#define I8259_IRQ_RESERVED_7 7
#define I8259_IRQ_RTC 8 /* who set this? */
#define I8259_IRQ_USB 9 /* ddb_setup */
#define I8259_IRQ_PMU 10 /* ddb_setup */
#define I8259_IRQ_RESERVED_11 11
#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 13
#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
#define I8259_IRQ_HDC2 15 /* default */
/*
* misc
*/
#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
#define CPU_VRC5476_CASCADE 2
#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
/*
* low-level irq functions
*/
#ifndef __ASSEMBLY__
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif /* !__ASSEMBLY__ */
include/asm-mips/ddb5xxx/ddb5477.h
View file @ 3ad349a5
......@@ -18,7 +18,6 @@
#define __ASM_DDB5XXX_DDB5477_H
#include <linux/config.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* This contains macros that are specific to DDB5477 or renamed from
......@@ -28,9 +27,9 @@
/*
* renamed PADRs
*/
#define DDB_LCS0 DDB_LDCS0
#define DDB_LCS1 DDB_LDCS1
#define DDB_LCS2 DDB_LDCS2
#define DDB_LCS0 DDB_DCS2
#define DDB_LCS1 DDB_DCS3
#define DDB_LCS2 DDB_DCS4
#define DDB_VRC5477 DDB_INTCS
/*
......@@ -173,8 +172,10 @@
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x08000000 /* 128MB, for sure? */
#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
#define DDB_PCI0_MEM_BASE 0x08000000
#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
......@@ -215,6 +216,7 @@
/*
* DDB5477 specific functions
*/
#ifndef __ASSEMBLY__
extern void ddb5477_irq_setup(void);
/* route irq to cpu int pin */
......@@ -223,11 +225,111 @@ extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
/* low-level routine for enabling vrc5477 irq, bypassing high-level */
extern void ll_vrc5477_irq_enable(int vrc5477_irq);
extern void ll_vrc5477_irq_disable(int vrc5477_irq);
#endif /* !__ASSEMBLY__ */
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5477 - 32 sources
*
* They connected as follows:
* all vrc5477 interrupts are routed to cpu IP2 (by software setting)
* all i8359 are routed to INTC in vrc5477 (by hardware connection)
*
* All VRC5477 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5477_IRQ 32
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
/*
* vrc5477 irq defs
*/
#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE)
#define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */
#define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE)
#define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */
#define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */
/*
* misc
*/
#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
#define CPU_VRC5477_CASCADE 2
/*
* debug routines
*/
#if defined(CONFIG_LL_DEBUG)
#ifndef __ASSEMBLY__
#if defined(CONFIG_RUNTIME_DEBUG)
extern void vrc5477_show_pdar_regs(void);
extern void vrc5477_show_pci_regs(void);
extern void vrc5477_show_bar_regs(void);
......@@ -235,4 +337,10 @@ extern void vrc5477_show_int_regs(void);
extern void vrc5477_show_all_regs(void);
#endif
/*
* RAM size
*/
extern int board_ram_size;
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_DDB5XXX_DDB5477_H */
include/asm-mips/ddb5xxx/ddb5xxx.h
View file @ 3ad349a5
/***********************************************************************
*
/*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
......@@ -14,7 +13,6 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5XXX_H
......@@ -23,8 +21,6 @@
#include <linux/config.h>
#include <linux/types.h>
#include <asm/ddb5xxx/debug.h>
/*
* This file is based on the following documentation:
*
......@@ -34,8 +30,8 @@
* that are true for all DDB 5xxx boards. The modification is based on
*
* uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
* Preliminary Specification Document, Rev 1.1, 27 Dec, 2000
*
* Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
*
*/
......@@ -49,12 +45,13 @@
#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
#define DDB_LDCS0 0x0010 /* Device Chip-Select 0 [R/W] */
#define DDB_LDCS1 0x0018 /* Device Chip-Select 1 [R/W] */
#define DDB_LDCS2 0x0020 /* Device Chip-Select 2 [R/W] */
#define DDB_LDCS3 0x0028 /* Device Chip-Select 3 [R/W] */
#define DDB_LDCS4 0x0030 /* Device Chip-Select 4 [R/W] */
#define DDB_LDCS5 0x0038 /* Device Chip-Select 5 [R/W] */
#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
......@@ -177,8 +174,13 @@
static inline void ddb_sync(void)
{
/* The DDB5074 doesn't seem to like these accesses. They kill the board on
* interrupt load
*/
#ifndef CONFIG_DDB5074
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
#endif
}
static inline void ddb_out32(u32 offset, u32 val)
......@@ -225,9 +227,9 @@ static inline u8 ddb_in8(u32 offset)
* Physical Device Address Registers
*/
extern u32
extern u32
ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
extern void
extern void
ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int pci_visible);
......
include/asm-mips/ddb5xxx/debug.h deleted 100644 → 0
View file @ 320bcfc9
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* include/asm-mips/ddb5xxx/debug.h
* Some debug macros used by ddb code.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DEBUG_H
#define __ASM_DDB5XXX_DEBUG_H
#include <linux/config.h>
/*
* macro for catching spurious errors. Eable to LL_DEBUG in kernel hacking
* config menu.
*/
#ifdef CONFIG_LL_DEBUG
#include <linux/kernel.h>
#define MIPS_ASSERT(x) if (!(x)) { panic("MIPS_ASSERT failed at %s:%d\n", __FILE__, __LINE__); }
#define MIPS_VERIFY(x, y) MIPS_ASSERT(x y)
#define MIPS_DEBUG(x) do { x; } while (0)
#else
#define MIPS_ASSERT(x)
#define MIPS_VERIFY(x, y) x
#define MIPS_DEBUG(x)
#endif
#endif /* __ASM_DDB5XXX_DEBUG_H */
include/asm-mips/ddb5xxx/pci.h deleted 100644 → 0
View file @ 320bcfc9
#ifndef __ASM_DDB5XXXX_PCI_H
#define __ASM_DDB5XXXX_PCI_H
/*
* This file essentially defines the interface between board
* specific PCI code and MIPS common PCI code. Should potentially put
* into include/asm/pci.h file.
*/
#include <linux/ioport.h>
#include <linux/pci.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_channel {
struct pci_ops *pci_ops;
struct resource *io_resource;
struct resource *mem_resource;
};
/*
* each board defines an array of pci_channels, that ends with all NULL entry
*/
extern struct pci_channel mips_pci_channels[];
/*
* board supplied pci irq fixup routine
*/
extern void pcibios_fixup_irqs(void);
#endif /* __ASM_DDB5XXXX_PCI_H */
include/asm-mips/nile4.h
View file @ 3ad349a5
......@@ -7,10 +7,10 @@
* This file is based on the following documentation:
*
* NEC Vrc 5074 System Controller Data Sheet, June 1998
*
* $Id: nile4.h,v 1.1 2000/01/26 00:07:45 ralf Exp $
*/
#ifndef _ASM_NILE4_H
#define _ASM_NILE4_H
#define NILE4_BASE 0xbfa00000
#define NILE4_SIZE 0x00200000 /* 2 MB */
......@@ -293,8 +293,8 @@ extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_enable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq(unsigned int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
......@@ -306,3 +306,5 @@ extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif
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