Commit 3bc26562 authored by Martyn Welch's avatar Martyn Welch Committed by Kumar Gala

powerpc/86xx: Support for NVRAM on GE Fanuc's PPC9A

Add support for NVRAM on GE Fanuc's PPC9A.
Signed-off-by: default avatarMartyn Welch <martyn.welch@gefanuc.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9093067a
...@@ -118,6 +118,12 @@ partition@7800000 { ...@@ -118,6 +118,12 @@ partition@7800000 {
}; };
}; };
nvram@3,0 {
device_type = "nvram";
compatible = "simtek,stk14ca8";
reg = <0x3 0x0 0x20000>;
};
fpga@4,0 { fpga@4,0 {
compatible = "gef,ppc9a-fpga-regs"; compatible = "gef,ppc9a-fpga-regs";
reg = <0x4 0x0 0x40>; reg = <0x4 0x0 0x40>;
......
...@@ -218,7 +218,7 @@ CONFIG_MPIC=y ...@@ -218,7 +218,7 @@ CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set # CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set # CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set # CONFIG_PPC_RTAS is not set
# CONFIG_MMIO_NVRAM is not set CONFIG_MMIO_NVRAM=y
# CONFIG_PPC_MPC106 is not set # CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set # CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set # CONFIG_PPC_INDIRECT_IO is not set
......
...@@ -35,6 +35,7 @@ config MPC8610_HPCD ...@@ -35,6 +35,7 @@ config MPC8610_HPCD
config GEF_PPC9A config GEF_PPC9A
bool "GE Fanuc PPC9A" bool "GE Fanuc PPC9A"
select DEFAULT_UIMAGE select DEFAULT_UIMAGE
select MMIO_NVRAM
select GENERIC_GPIO select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
help help
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#include <asm/udbg.h> #include <asm/udbg.h>
#include <asm/mpic.h> #include <asm/mpic.h>
#include <asm/nvram.h>
#include <sysdev/fsl_pci.h> #include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
...@@ -95,6 +96,10 @@ static void __init gef_ppc9a_setup_arch(void) ...@@ -95,6 +96,10 @@ static void __init gef_ppc9a_setup_arch(void)
printk(KERN_WARNING "Unable to map board registers\n"); printk(KERN_WARNING "Unable to map board registers\n");
of_node_put(regs); of_node_put(regs);
} }
#if defined(CONFIG_MMIO_NVRAM)
mmio_nvram_init();
#endif
} }
/* Return the PCB revision */ /* Return the PCB revision */
......
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