[netdrvr ixgb] massive update

Since Intel agreed to submit further updates via broken-up patches
like they do currently (and admirably) for e1000 and e100, I agreed
to merge this update to bring the driver up to speed.

Contributed by: Ayyappan.Veeraiyan@intel.com

Changes:

Features implemented

*	Support for new 850nm adapters.
*	Copyright notice updated to include year 2004.
*	Fix for "ixgb does not maintain non-default MTU setting across a
link loss" issue - When link loss happens in non-default MTU
environment, driver will incorrectly operate with default 1500 MTU
setting.
*	Netpoll support added
*	Ethtool support - status functionality, FlowControl interface,
Checksum interface, TSO and Scatter Gather interfaces
*	Race condition fix - Race condition (TX path) exists between
ixgb_xmit_frame and clean_tx_irq routines in handling the queue.
* 	Removed dead code segments (#if 0)


Performance improvement features 
*	Mod operator usage is removed - used to cause performance
problems in non-IA architecture based machines
*	Multiple ICR register read in ISR is avoided
*	RS bit set on only 'end of packet' TX descriptors - to avoid
multiple writebacks by controller for packets with multiple descriptors.
*	RX descriptors prefetch is done - improved 1500 MTU TX
performance


All relevant e1000 driver cleanups ported to ixgb
*	Valid error propagation in functions ixgb_up, ixgb_probe,
ixgb_open. 
* 	NAPI code cleanups
* 	u8, u16 and u32 data types are changed to uint8_t, uint16_t and
uint32_t respectively. We use these types on our shared code for
multiple OSes and also to make it uniform with e1000 driver.
*	Some functions in ixgb_main.c are moved to different location -
This enables easy porting of e1000 bug fixes to ixgb 

drivers/net/ixgb/ixgb.h

 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -23,6 +23,7 @@
   Contact Information:
   Linux NICS <linux.nics@intel.com>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
 *******************************************************************************/
 
 #ifndef _IXGB_H_
@@ -34,39 +35,44 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/errno.h>
 #include <linux/ioport.h>
 #include <linux/pci.h>
+#include <linux/kernel.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/delay.h>
 #include <linux/timer.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
 #include <linux/string.h>
 #include <linux/pagemap.h>
 #include <linux/dma-mapping.h>
-#include <linux/bitops.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/capability.h>
 #include <linux/in.h>
 #include <linux/ip.h>
 #include <linux/tcp.h>
 #include <linux/udp.h>
 #include <net/pkt_sched.h>
 #include <linux/list.h>
-#include <linux/workqueue.h>
 #include <linux/reboot.h>
 #ifdef NETIF_F_TSO
 #include <net/checksum.h>
 #endif
 
-/* ethtool support */
 #include <linux/ethtool.h>
 #include <linux/if_vlan.h>
 
-struct ixgb_adapter;
-
 #define BAR_0		0
 #define BAR_1		1
 #define BAR_5		5
 
+struct ixgb_adapter;
 #include "ixgb_hw.h"
 #include "ixgb_ee.h"
 #include "ixgb_ids.h"
@@ -89,7 +95,7 @@ struct ixgb_adapter;
 #define IXGB_TX_QUEUE_WAKE 16
 
 /* How many Rx Buffers do we bundle into one write to the hardware ? */
-#define IXGB_RX_BUFFER_WRITE    16
+#define IXGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */
 
 /* only works for sizes that are powers of 2 */
 #define IXGB_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
@@ -101,6 +107,7 @@ struct ixgb_buffer {
 	uint64_t dma;
 	unsigned long length;
 	unsigned long time_stamp;
+	unsigned int next_to_watch;
 };
 
 struct ixgb_desc_ring {
@@ -121,7 +128,8 @@ struct ixgb_desc_ring {
 };
 
 #define IXGB_DESC_UNUSED(R) \
-((((R)->next_to_clean + (R)->count) - ((R)->next_to_use + 1)) % ((R)->count))
+	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
+	(R)->next_to_clean - (R)->next_to_use - 1)
 
 #define IXGB_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
 #define IXGB_RX_DESC(R, i)		IXGB_GET_DESC(R, i, ixgb_rx_desc)
@@ -133,39 +141,32 @@ struct ixgb_desc_ring {
 struct ixgb_adapter {
 	struct timer_list watchdog_timer;
 	struct vlan_group *vlgrp;
-	char *id_string;
-	u32 bd_number;
-	u32 rx_buffer_len;
-	u32 part_num;
-	u16 link_speed;
-	u16 link_duplex;
+	uint32_t bd_number;
+	uint32_t rx_buffer_len;
+	uint32_t part_num;
+	uint16_t link_speed;
+	uint16_t link_duplex;
+	spinlock_t tx_lock;
 	atomic_t irq_sem;
 	struct work_struct tx_timeout_task;
 
-#ifdef ETHTOOL_PHYS_ID
 	struct timer_list blink_timer;
 	unsigned long led_status;
-#endif
-#ifdef _INTERNAL_LOOPBACK_DRIVER_
-	struct ixgb_desc_ring diag_tx_ring;
-	struct ixgb_desc_ring diag_rx_ring;
-#endif
+
 	/* TX */
 	struct ixgb_desc_ring tx_ring;
 	unsigned long timeo_start;
-	u32 tx_cmd_type;
-	int max_data_per_txd;
+	uint32_t tx_cmd_type;
 	uint64_t hw_csum_tx_good;
 	uint64_t hw_csum_tx_error;
-	boolean_t tx_csum;
-	u32 tx_int_delay;
+	uint32_t tx_int_delay;
 	boolean_t tx_int_delay_enable;
 
 	/* RX */
 	struct ixgb_desc_ring rx_ring;
 	uint64_t hw_csum_rx_error;
 	uint64_t hw_csum_rx_good;
-	u32 rx_int_delay;
+	uint32_t rx_int_delay;
 	boolean_t raidc;
 	boolean_t rx_csum;
 
@@ -177,8 +178,6 @@ struct ixgb_adapter {
 	/* structs defined in ixgb_hw.h */
 	struct ixgb_hw hw;
 	struct ixgb_hw_stats stats;
-	u32 pci_state[16];
-	char ifname[IFNAMSIZ];
+	uint32_t pci_state[16];
 };
-
 #endif				/* _IXGB_H_ */

drivers/net/ixgb/ixgb_ee.h

 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -23,6 +23,7 @@
   Contact Information:
   Linux NICS <linux.nics@intel.com>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
 *******************************************************************************/
 
 #ifndef _IXGB_EE_H_
@@ -73,32 +74,32 @@
 
 /* EEPROM structure */
 struct ixgb_ee_map_type {
-	u8 mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
-	u16 compatibility;
-	u16 reserved1[4];
-	u32 pba_number;
-	u16 init_ctrl_reg_1;
-	u16 subsystem_id;
-	u16 subvendor_id;
-	u16 device_id;
-	u16 vendor_id;
-	u16 init_ctrl_reg_2;
-	u16 oem_reserved[16];
-	u16 swdpins_reg;
-	u16 circuit_ctrl_reg;
-	u8 d3_power;
-	u8 d0_power;
-	u16 reserved2[28];
-	u16 checksum;
+	uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
+	uint16_t compatibility;
+	uint16_t reserved1[4];
+	uint32_t pba_number;
+	uint16_t init_ctrl_reg_1;
+	uint16_t subsystem_id;
+	uint16_t subvendor_id;
+	uint16_t device_id;
+	uint16_t vendor_id;
+	uint16_t init_ctrl_reg_2;
+	uint16_t oem_reserved[16];
+	uint16_t swdpins_reg;
+	uint16_t circuit_ctrl_reg;
+	uint8_t d3_power;
+	uint8_t d0_power;
+	uint16_t reserved2[28];
+	uint16_t checksum;
 };
 
 /* EEPROM Functions */
-u16 ixgb_read_eeprom(struct ixgb_hw *hw, u16 reg);
+uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
 
 boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
 
 void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
 
-void ixgb_write_eeprom(struct ixgb_hw *hw, u16 reg, u16 data);
+void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
 
 #endif				/* IXGB_EE_H */

drivers/net/ixgb/ixgb_ids.h

 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -23,6 +23,7 @@
   Contact Information:
   Linux NICS <linux.nics@intel.com>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
 *******************************************************************************/
 
 #ifndef _IXGB_IDS_H_
@@ -36,8 +37,16 @@
 #define INTEL_SUBVENDOR_ID      0x8086
 
 #define IXGB_DEVICE_ID_82597EX      0x1048
-#define IXGB_SUBDEVICE_ID_A11F  0xA11F	/* Adapter-OEM-1310nm-Fiber */
-#define IXGB_SUBDEVICE_ID_A01F	0xA01F	/* Adapter-Retail-1310nm-Fiber */
+#define IXGB_DEVICE_ID_82597EX_SR   0x1A48
+
+#define IXGB_SUBDEVICE_ID_A11F  0xA11F
+#define IXGB_SUBDEVICE_ID_A01F  0xA01F
+
+#define IXGB_SUBDEVICE_ID_A15F  0xA15F
+#define IXGB_SUBDEVICE_ID_A05F  0xA05F
+
+#define IXGB_SUBDEVICE_ID_A12F  0xA12F
+#define IXGB_SUBDEVICE_ID_A02F  0xA02F
 
 #endif				/* #ifndef _IXGB_IDS_H_ */
 

drivers/net/ixgb/ixgb_osdep.h

 /*******************************************************************************
 
   
-  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
+  Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
   
   This program is free software; you can redistribute it and/or modify it 
   under the terms of the GNU General Public License as published by the Free 
@@ -23,14 +23,15 @@
   Contact Information:
   Linux NICS <linux.nics@intel.com>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
 *******************************************************************************/
 
-/* glue for the OS independant part of ixgb 
+/* glue for the OS independent part of ixgb
  * includes register access macros
  */
 
-#ifndef IXGB_OSDEP_H
-#define IXGB_OSDEP_H
+#ifndef _IXGB_OSDEP_H_
+#define _IXGB_OSDEP_H_
 
 #include <linux/types.h>
 #include <linux/pci.h>
@@ -39,35 +40,42 @@
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 
-/* FIXME: eliminate me */
+#ifndef msec_delay
 #define msec_delay(x)	do { if(in_interrupt()) { \
-	                	mdelay(x); \
+				/* Don't mdelay in interrupt context! */ \
+	                	BUG(); \
 			} else { \
 				set_current_state(TASK_UNINTERRUPTIBLE); \
-				schedule_timeout((x * HZ)/1000); \
+				schedule_timeout((x * HZ)/1000 + 2); \
 			} } while(0)
+#endif
+
+#define PCI_COMMAND_REGISTER   PCI_COMMAND
+#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
 
 typedef enum {
+#undef FALSE
 	FALSE = 0,
+#undef TRUE
 	TRUE = 1
 } boolean_t;
 
+#undef ASSERT
+#define ASSERT(x)	if(!(x)) BUG()
 #define MSGOUT(S, A, B)	printk(KERN_DEBUG S "\n", A, B)
 
 #if DBG
-#define ASSERT(x)	if(!(x)) BUG()
-#define DEBUGOUT(S)		printk(KERN_ERR S "\n")
-#define DEBUGOUT1(S, A...)	printk(KERN_ERR S "\n", A)
+#define DEBUGOUT(S)		printk(KERN_DEBUG S "\n")
+#define DEBUGOUT1(S, A...)	printk(KERN_DEBUG S "\n", A)
 #else
-#define ASSERT(x)
 #define DEBUGOUT(S)
 #define DEBUGOUT1(S, A...)
 #endif
 
-#define DEBUGOUT2 DEBUGOUT1
-#define DEBUGOUT3 DEBUGOUT1
-#define DEBUGOUT7 DEBUGOUT1
 #define DEBUGFUNC(F) DEBUGOUT(F)
+#define DEBUGOUT2 DEBUGOUT1
+#define DEBUGOUT3 DEBUGOUT2
+#define DEBUGOUT7 DEBUGOUT3
 
 #define IXGB_WRITE_REG(a, reg, value) ( \
     writel((value), ((a)->hw_addr + IXGB_##reg)))
@@ -81,4 +89,8 @@ typedef enum {
 #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
     readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
 
-#endif				/* IXGB_OSDEP_H */
+#define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
+
+#define IXGB_MEMCPY memcpy
+
+#endif				/* _IXGB_OSDEP_H_ */