Commit 3d9f96d8 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Kevin Hilman:
 "As usual, quite a few device-tree updates in ARM land.  There was one
  minor churn in DTs due to relicensing under a dual-license, and lots
  of little additions of new peripherals, features etc, but nothing
  really exciting to call to your attention.  Some higlights, focsuing
  on support for new SoCs and boards:

   - AT91: new boards: Overkiz,  Acme Systems' Arietta G25
   - tegra: HDA support
   - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS
     RT-AC87U
   - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys
     boards, DLink DNS-327L
   - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill
     SL50
   - ARM: added support for Juno r1 board
   - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33,
     Mele A1000G
   - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6,
     Gateworks GW5510, and aristainetos2 boards
   - hisilicon: hi6220 SoC support; new boards: 96boards hikey"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits)
  ARM: hisi: revert changes from hisi/hip04-dt branch
  ARM: nomadik: set proper compatible for accelerometer
  ARM64: juno: add GPIO keys
  ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes
  ARM: dts: Introduce STM32F429 MCU
  ARM: socfpga: dts: enable ethernet for Arria10 devkit
  ARM: dts: k2l: fix the netcp range size
  ARM: dts: k2e: fix the netcp range size
  ARM: dts: k2hk: fix the netcp range size
  ARM: dts: k2l-evm: Add device bindings for netcp driver
  ARM: dts: k2e-evm: Add device bindings for netcp driver
  ARM: dts: k2hk-evm: Add device bindings for netcp driver
  ARM: BCM5301X: Add DT for Asus RT-AC87U
  ARM: BCM5301X: add IRQ numbers for PCIe controller
  ARM: BCM5301X: add NAND flash chip description
  arm64: dts: Add dts files for Hisilicon Hi6220 SoC
  clk: hi6220: Document devicetree bindings for hi6220 clock
  arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
  ARM: at91/dt: sama5d4ek: mci0 uses slot 0
  ARM: at91/dt: kizbox: fix mismatch LED PWM device
  ...
parents 4aa705b1 58c17967
Altera SOCFPGA SDRAM Controller
Required properties:
- compatible : Should contain "altr,sdr-ctl" and "syscon".
syscon is required by the Altera SOCFPGA SDRAM EDAC.
- reg : Should contain 1 register range (address and length)
Example:
sdr: sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
};
......@@ -157,3 +157,69 @@ Example:
};
};
ARM Versatile Express Boards
-----------------------------
For details on the device tree bindings for ARM Versatile Express boards
please consult the vexpress.txt file in the same directory as this file.
ARM Juno Boards
----------------
The Juno boards are targeting development for AArch64 systems. The first
iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
with the second iteration, Juno r1, mainly aimed at development of PCIe
based systems. Juno r1 also has support for AXI masters placed on the TLX
connectors to join the coherency domain.
Juno boards are described in a similar way to ARM Versatile Express boards,
with the motherboard part of the hardware being described in a separate file
to highlight the fact that is part of the support infrastructure for the SoC.
Juno device tree bindings also share the Versatile Express bindings as
described under the RS1 memory mapping.
Required properties (in root node):
compatible = "arm,juno"; /* For Juno r0 board */
compatible = "arm,juno-r1"; /* For Juno r1 board */
Required nodes:
The description for the board must include:
- a "psci" node describing the boot method used for the secondary CPUs.
A detailed description of the bindings used for "psci" nodes is present
in the psci.txt file.
- a "cpus" node describing the available cores and their associated
"enable-method"s. For more details see cpus.txt file.
Example:
/dts-v1/;
/ {
model = "ARM Juno development board (r0)";
compatible = "arm,juno", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
};
.....
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
};
.....
};
};
Broadcom BCM2835 device tree bindings
-------------------------------------------
Boards with the BCM2835 SoC shall have the following properties:
Raspberry Pi Model A
Required root node properties:
compatible = "raspberrypi,model-a", "brcm,bcm2835";
Required root node property:
Raspberry Pi Model A+
Required root node properties:
compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
Raspberry Pi Model B
Required root node properties:
compatible = "raspberrypi,model-b", "brcm,bcm2835";
Raspberry Pi Model B (no P5)
early model B with I2C0 rather than I2C1 routed to the expansion header
Required root node properties:
compatible = "raspberrypi,model-b-i2c0", "brcm,bcm2835";
Raspberry Pi Model B rev2
Required root node properties:
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
Raspberry Pi Model B+
Required root node properties:
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";
......@@ -7,3 +7,79 @@ following properties:
Required root node property:
compatible: should be "brcm,bcm63138"
An optional Boot lookup table Device Tree node is required for secondary CPU
initialization as well as a 'resets' phandle to the correct PMB controller as
defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
'enable-method' property.
Required properties for the Boot lookup table node:
- compatible: should be "brcm,bcm63138-bootlut"
- reg: register base address and length for the Boot Lookup table
Optional properties for the primary CPU node:
- enable-method: should be "brcm,bcm63138"
Optional properties for the secondary CPU node:
- enable-method: should be "brcm,bcm63138"
- resets: phandle to the relevant PMB controller, one integer indicating the internal
bus number, and a second integer indicating the address of the CPU in the PMB
internal bus number.
Example:
cpus {
cpu@0 {
compatible = "arm,cotex-a9";
reg = <0>;
...
enable-method = "brcm,bcm63138";
};
cpu@1 {
compatible = "arm,cortex-a9";
reg = <1>;
...
enable-method = "brcm,bcm63138";
resets = <&pmb0 4 1>;
};
};
bootlut: bootlut@8000 {
compatible = "brcm,bcm63138-bootlut";
reg = <0x8000 0x50>;
};
=======
reboot
------
Two nodes are required for software reboot: a timer node and a syscon-reboot node.
Timer node:
- compatible: Must be "brcm,bcm6328-timer", "syscon"
- reg: Register base address and length
Syscon reboot node:
See Documentation/devicetree/bindings/power/reset/syscon-reboot.txt for the
detailed list of properties, the two values defined below are specific to the
BCM6328-style timer:
- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
from the beginning of the TIMER block
- mask: Should be 1 for the SoftRst bit.
Example:
timer: timer@80 {
compatible = "brcm,bcm6328-timer", "syscon";
reg = <0x80 0x3c>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&timer>;
offset = <0x34>;
mask = <0x1>;
};
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";
Hi4511 Board
Required root node properties:
......@@ -13,6 +16,9 @@ HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
Hisilicon system controller
......@@ -40,6 +46,87 @@ Example:
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon Hi6220 system controller
Required properties:
- compatible : "hisilicon,hi6220-sysctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this controller as one of the system controllers,
its main functions are the same as Hisilicon system controller, but
the register offset of some core modules are different.
Example:
/*for Hi6220*/
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Power Always ON domain controller
Required properties:
- compatible : "hisilicon,hi6220-aoctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this system controller to control the power always
on domain for mobile platform.
Example:
/*for Hi6220*/
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Media domain controller
Required properties:
- compatible : "hisilicon,hi6220-mediactrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this system controller to control the multimedia
domain(e.g. codec, G3D ...) for mobile platform.
Example:
/*for Hi6220*/
media_ctrl: media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Power Management domain controller
Required properties:
- compatible : "hisilicon,hi6220-pmctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, some clock registers are define
under this controller and this property must be present.
Hisilicon designs this system controller to control the power management
domain for mobile platform.
Example:
/*for Hi6220*/
pm_ctrl: pm_ctrl@f7032000 {
compatible = "hisilicon,hi6220-pmctrl", "syscon";
reg = <0x0 0xf7032000 0x0 0x1000>;
#clock-cells = <1>;
};
-----------------------------------------------------------------------
Hisilicon HiP01 system controller
......
Marvell Berlin SoC Family Device Tree Bindings
---------------------------------------------------------------
Work in progress statement:
Device tree files and bindings applying to Marvell Berlin SoCs and boards are
considered "unstable". Any Marvell Berlin device tree binding may change at any
time. Be sure to use a device tree binary and a kernel image generated from the
same source tree.
Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
stable binding/ABI.
---------------------------------------------------------------
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
......@@ -49,10 +61,9 @@ chip control registers, so there should be a single DT node only providing the
different functions which are described below.
Required properties:
- compatible: shall be one of
"marvell,berlin2-chip-ctrl" for BG2
"marvell,berlin2cd-chip-ctrl" for BG2CD
"marvell,berlin2q-chip-ctrl" for BG2Q
- compatible:
* the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of following register sets for
BG2/BG2CD: chip control register set
BG2Q: chip control register set and cpu pll registers
......@@ -63,90 +74,23 @@ Marvell Berlin SoCs have a system control register set providing several
individual registers dealing with pinmux, padmux, and reset.
Required properties:
- compatible: should be one of
"marvell,berlin2-system-ctrl" for BG2
"marvell,berlin2cd-system-ctrl" for BG2CD
"marvell,berlin2q-system-ctrl" for BG2Q
- compatible:
* the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of the system control register set
* Clock provider binding
As clock related registers are spread among the chip control registers, the
chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
SoCs share the same IP for PLLs and clocks, with some minor differences in
features and register layout.
Required properties:
- #clock-cells: shall be set to 1
- clocks: clock specifiers referencing the core clock input clocks
- clock-names: array of strings describing the input clock specifiers above.
Allowed clock-names for the reference clocks are
"refclk" for the SoCs osciallator input on all SoCs,
and SoC-specific input clocks for
BG2/BG2CD: "video_ext0" for the external video clock input
Clocks provided by core clocks shall be referenced by a clock specifier
indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
for the corresponding index mapping.
* Pin controller binding
Pin control registers are part of both register sets, chip control and system
control. The pins controlled are organized in groups, so no actual pin
information is needed.
A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and the muxing
function used.
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
a 'function' in the pin-controller subsystem.
Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.
* Reset controller binding
A reset controller is part of the chip control registers set. The chip control
node also provides the reset. The register set is not at the same offset between
Berlin SoCs.
Required property:
- #reset-cells: must be set to 2
Example:
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;
#reset-cells = <2>;
compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
clocks = <&refclk>, <&externaldev 0>;
clock-names = "refclk", "video_ext0";
spi1_pmux: spi1-pmux {
groups = "G0";
function = "spi1";
};
/* sub-device nodes */
};
sysctrl: system-controller@d000 {
compatible = "marvell,berlin2-system-ctrl";
compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux {
groups = "GSM4";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM5";
function = "uart1";
};
uart2_pmux: uart2-pmux {
groups = "GSM3";
function = "uart2";
};
/* sub-device nodes */
};
* ARM Snoop Control Unit (SCU)
As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
with a Snoop Control Unit. The register range is usually 256 (0x100)
bytes.
References:
- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
Revision r2p0
- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
Revision r0p1
- compatible : Should be:
"arm,cortex-a9-scu"
"arm,cortex-a5-scu"
- reg : Specify the base address and the size of the SCU register window.
Example:
scu@a04100000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};
ST-Ericsson Ux500 boards
------------------------
Required properties (in root node) one of these:
compatible = "st-ericsson,mop500" (legacy)
compatible = "st-ericsson,u8500"
Required node (under root node):
soc: represents the system-on-chip and contains the chip
peripherals
Required property of soc node, one of these:
compatible = "stericsson,db8500"
Required subnodes under soc node:
backupram: (used for CPU spin tables and for storing data
during retention, system won't boot without this):
compatible = "ste,dbx500-backupram"
scu:
see binding for arm/scu.txt
interrupt-controller:
see binding for arm/gic.txt
timer:
see binding for arm/twd.txt
clocks:
see binding for clocks/ux500.txt
Example:
/dts-v1/;
/ {
model = "ST-Ericsson HREF (pre-v60) and ST UIB";
compatible = "st-ericsson,mop500", "st-ericsson,u8500";
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "stericsson,db8500";
interrupt-parent = <&intc>;
ranges;
backupram@80150000 {
compatible = "ste,dbx500-backupram";
reg = <0x80150000 0x2000>;
};
intc: interrupt-controller@a0411000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xa0411000 0x1000>,
<0xa0410100 0x100>;
};
scu@a04100000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};
timer@a0410600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xa0410600 0x20>;
interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
clocks = <&smp_twd_clk>;
};
clocks {
compatible = "stericsson,u8500-clks";
smp_twd_clk: smp-twd-clock {
#clock-cells = <0>;
};
};
};
};
* Hisilicon Hi6220 Clock Controller
Clock control registers reside in different Hi6220 system controllers,
please refer the following document to know more about the binding rules
for these system controllers:
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi6220-aoctrl"
- "hisilicon,hi6220-sysctrl"
- "hisilicon,hi6220-mediactrl"
- "hisilicon,hi6220-pmctrl"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
For example:
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi6220-clock.h>.
* Clock bindings for Freescale i.MX7 Dual
Required properties:
- compatible: Should be "fsl,imx7d-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
for the full list of i.MX7 Dual clock IDs.
Device Tree Clock bindings for Marvell Berlin
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
minor differences in features and register layout.
Required properties:
- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
- #clock-cells: must be 1
- clocks: must be the input parent clock phandle
- clock-names: name of the input parent clock
Allowed clock-names for the reference clocks are
"refclk" for the SoCs oscillator input on all SoCs,
and SoC-specific input clocks for
BG2/BG2CD: "video_ext0" for the external video clock input
Example:
chip_clk: clock {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
......@@ -58,5 +58,5 @@ Example:
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
}
};
};
* Pin-controller driver for the Marvell Berlin SoCs
Pin control registers are part of both chip controller and system
controller register sets. Pin controller nodes should be a sub-node of
either the chip controller or system controller node. The pins
controlled are organized in groups, so no actual pin information is
needed.
A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and
the muxing function used.
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what
is called a 'function' in the pin-controller subsystem.
Required properties:
- compatible: should be one of:
"marvell,berlin2-soc-pinctrl",
"marvell,berlin2-system-pinctrl",
"marvell,berlin2cd-soc-pinctrl",
"marvell,berlin2cd-system-pinctrl",
"marvell,berlin2q-soc-pinctrl",
"marvell,berlin2q-system-pinctrl"
Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.
Example:
sys_pinctrl: pin-controller {
compatible = "marvell,berlin2q-system-pinctrl";
uart0_pmux: uart0-pmux {
groups = "GSM12";
function = "uart0";
};
};
&uart0 {
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
};
* Freescale i.MX7 Dual IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx7d-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
Reference Manual for detailed CONFIG settings.
CONFIG bits definition:
PAD_CTL_PUS_100K_DOWN (0 << 5)
PAD_CTL_PUS_5K_UP (1 << 5)
PAD_CTL_PUS_47K_UP (2 << 5)
PAD_CTL_PUS_100K_UP (3 << 5)
PAD_CTL_PUE (1 << 4)
PAD_CTL_HYS (1 << 3)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_FAST (0 << 2)
PAD_CTL_DSE_X1 (0 << 0)
PAD_CTL_DSE_X2 (1 << 0)
PAD_CTL_DSE_X3 (2 << 0)
PAD_CTL_DSE_X4 (3 << 0)
Marvell Berlin reset controller
===============================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
The reset controller node must be a sub-node of the chip controller
node on Berlin SoCs.
Required properties:
- compatible: should be "marvell,berlin2-reset"
- #reset-cells: must be set to 2
Example:
chip_rst: reset {
compatible = "marvell,berlin2-reset";
#reset-cells = <2>;
};
&usb_phy0 {
resets = <&chip_rst 0x104 12>;
};
Broadcom BCM63138 Processor Monitor Bus binding
===============================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Require properties:
- compatible: must be "brcm,bcm63138-pmb"
- reg: base register address and size for this bus controller
- #reset-cells: must be 2 first cell is the address within the bus instance designated
by the phandle, and the second is the number of zones for this peripheral
Example:
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
#reset-cells = <2>;
};
......@@ -6,7 +6,8 @@ Required properties:
* "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc.
* "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc.
* "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
* "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc.
* "samsung,exynos3250-rtc" - (deprecated) for controllers compatible with
exynos3250 rtc (use "samsung,s3c6410-rtc").
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: Two interrupt numbers to the cpu should be specified. First
......
......@@ -60,7 +60,7 @@ Example:
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7791";
reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
......
......@@ -6,6 +6,9 @@ Required properties:
- interrupts : A list of 3 interrupts; one per timer channel.
- clocks: phandle to the source clock
Optional properties:
- timer-width: Bit width of the timer, necessary if not 16.
Example:
ttc0: ttc0@f8001000 {
......@@ -14,4 +17,5 @@ ttc0: ttc0@f8001000 {
compatible = "cdns,ttc";
reg = <0xF8001000 0x1000>;
clocks = <&cpu_clk 3>;
timer-width = <32>;
};
......@@ -5,6 +5,13 @@ OHCI
Required properties:
- compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
used in host mode.
- reg: Address and length of the register set for the device
- interrupts: Should contain ehci interrupt
- clocks: Should reference the peripheral, host and system clocks
- clock-names: Should contains two strings
"ohci_clk" for the peripheral clock
"hclk" for the host clock
"uhpck" for the system clock
- num-ports: Number of ports.
- atmel,vbus-gpio: If present, specifies a gpio that needs to be
activated for the bus to be powered.
......@@ -14,6 +21,8 @@ Required properties:
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
interrupts = <20 4>;
num-ports = <2>;
};
......@@ -23,11 +32,19 @@ EHCI
Required properties:
- compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
used in host mode.
- reg: Address and length of the register set for the device
- interrupts: Should contain ehci interrupt
- clocks: Should reference the peripheral and the UTMI clocks
- clock-names: Should contains two strings
"ehci_clk" for the peripheral clock
"usb_clk" for the UTMI clock
usb1: ehci@00800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 4>;
clocks = <&utmi>, <&uhphs_clk>;
clock-names = "usb_clk", "ehci_clk";
};
AT91 USB device controller
......@@ -53,6 +70,8 @@ usb1: gadget@fffa4000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 4>;
clocks = <&udc_clk>, <&udpck>;
clock-names = "pclk", "hclk";
atmel,vbus-gpio = <&pioC 5 0>;
};
......@@ -65,6 +84,10 @@ Required properties:
"sama5d3-udc"
- reg: Address and length of the register set for the device
- interrupts: Should contain usba interrupt
- clocks: Should reference the peripheral and host clocks
- clock-names: Should contains two strings
"pclk" for the peripheral clock
"hclk" for the host clock
- ep childnode: To specify the number of endpoints and their properties.
Optional properties:
......@@ -86,6 +109,8 @@ usb2: gadget@fff78000 {
reg = <0x00600000 0x80000
0xfff78000 0x400>;
interrupts = <27 4 0>;
clocks = <&utmi>, <&udphs_clk>;
clock-names = "hclk", "pclk";
atmel,vbus-gpio = <&pioB 19 0>;
ep0 {
......
......@@ -40,6 +40,7 @@ calxeda Calxeda
capella Capella Microsystems, Inc
cavium Cavium, Inc.
cdns Cadence Design Systems Inc.
ceva Ceva, Inc.
chipidea Chipidea, Inc
chipone ChipOne
chipspark ChipSPARK
......@@ -52,6 +53,7 @@ cnxt Conexant Systems, Inc.
cortina Cortina Systems, Inc.
cosmic Cosmic Circuits
crystalfontz Crystalfontz America, Inc.
cubietech Cubietech, Ltd.
dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc.
delta Delta Electronics, Inc.
......@@ -61,6 +63,7 @@ digilent Diglent, Inc.
dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
ea Embedded Artists AB
ebv EBV Elektronik
edt Emerging Display Technologies
elan Elan Microelectronic Corp.
......@@ -91,9 +94,11 @@ gumstix Gumstix, Inc.
gw Gateworks Corporation
hannstar HannStar Display Corporation
haoyu Haoyu Microelectronic Co. Ltd.
hardkernel Hardkernel Co., Ltd
himax Himax Technologies, Inc.
hisilicon Hisilicon Limited.
hit Hitachi Ltd.
hitex Hitex Development Tools
honeywell Honeywell
hp Hewlett Packard
i2se I2SE GmbH
......@@ -160,6 +165,7 @@ radxa Radxa
raidsonic RaidSonic Technology GmbH
ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
raspberrypi Raspberry Pi Foundation
realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation
richtek Richtek Technology Corporation
......@@ -192,6 +198,7 @@ ste ST-Ericsson
stericsson ST-Ericsson
synology Synology, Inc.
tbs TBS Technologies
tcl Toby Churchill Ltd.
thine THine Electronics, Inc.
ti Texas Instruments
tlm Trusted Logic Mobility
......@@ -205,6 +212,7 @@ variscite Variscite Ltd.
via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
voipac Voipac Technologies s.r.o.
wexler Wexler
winbond Winbond Electronics corp.
wlf Wolfson Microelectronics
wm Wondermedia Technologies, Inc.
......
......@@ -20,9 +20,9 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \
tny_a9263.dtb \
usb_a9263.dtb \
at91-foxg20.dtb \
at91-kizbox.dtb \
at91sam9g20ek.dtb \
at91sam9g20ek_2mmc.dtb \
kizbox.dtb \
tny_a9g20.dtb \
usb_a9g20.dtb \
usb_a9g20_lpw.dtb \
......@@ -31,13 +31,16 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \
at91sam9n12ek.dtb \
at91sam9rlek.dtb \
at91-ariag25.dtb \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
at91-kizboxmini.dtb \
at91sam9g15ek.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-sama5d3_xplained.dtb \
sama5d31ek.dtb \
sama5d33ek.dtb \
......@@ -56,13 +59,18 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2835-rpi-b.dtb \
bcm2835-rpi-b-plus.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4708-asus-rt-ac56u.dtb \
bcm4708-asus-rt-ac68u.dtb \
bcm4708-buffalo-wzr-1750dhp.dtb \
bcm4708-luxul-xwc-1000.dtb \
bcm4708-netgear-r6250.dtb \
bcm4708-netgear-r6300-v2.dtb \
bcm4708-smartrg-sr400ac.dtb \
bcm47081-asus-rt-n18u.dtb \
bcm47081-buffalo-wzr-600dhp2.dtb \
bcm47081-buffalo-wzr-900dhp.dtb \
bcm4709-asus-rt-ac87u.dtb \
bcm4709-buffalo-wxr-1900dhp.dtb \
bcm4709-netgear-r8000.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
......@@ -113,6 +121,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5420-peach-pit.dtb \
exynos5420-smdk5420.dtb \
exynos5422-odroidxu3.dtb \
exynos5422-odroidxu3-lite.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb \
exynos5800-peach-pi.dtb
......@@ -201,6 +210,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ts219-6282.dtb \
kirkwood-ts419-6281.dtb \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_LPC18XX) += \
lpc4350-hitex-eval.dtb \
lpc4357-ea4357-devkit.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
ea3250.dtb phy3250.dtb
dtb-$(CONFIG_MACH_MESON6) += \
......@@ -254,14 +266,18 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-tx53-x13x.dtb \
imx53-voipac-bsb.dtb
dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-apf6dev.dtb \
imx6dl-aristainetos_4.dtb \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
imx6dl-gw53xx.dtb \
imx6dl-gw54xx.dtb \
imx6dl-gw551x.dtb \
imx6dl-gw552x.dtb \
imx6dl-hummingboard.dtb \
imx6dl-nitrogen6x.dtb \
......@@ -277,6 +293,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-udoo.dtb \
imx6dl-wandboard.dtb \
imx6dl-wandboard-revb1.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
......@@ -288,6 +305,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw53xx.dtb \
imx6q-gw5400-a.dtb \
imx6q-gw54xx.dtb \
imx6q-gw551x.dtb \
imx6q-gw552x.dtb \
imx6q-hummingboard.dtb \
imx6q-nitrogen6x.dtb \
......@@ -313,12 +331,15 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-colibri-eval-v3.dtb \
vf610m4-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += \
......@@ -360,6 +381,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
am3517-craneboard.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
logicpd-torpedo-37xx-devkit.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
omap3-beagle-xm.dtb \
......@@ -406,9 +428,11 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
dtb-$(CONFIG_SOC_TI81XX) += \
dm8168-evm.dtb
dtb-$(CONFIG_SOC_AM33XX) += \
am335x-baltos-ir5221.dtb \
am335x-base0033.dtb \
am335x-bone.dtb \
am335x-boneblack.dtb \
am335x-sl50.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-nano.dtb \
......@@ -496,7 +520,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
......@@ -520,32 +544,39 @@ dtb-$(CONFIG_ARCH_STI) += \
stih416-b2020.dtb \
stih416-b2020e.dtb \
stih418-b2199.dtb
dtb-$(CONFIG_ARCH_STM32)+= stm32f429-disco.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
sun4i-a10-chuwi-v7-cw0825.dtb \
sun4i-a10-cubieboard.dtb \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-utoo-p66.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
sun6i-a31-hummingbird.dtb \
sun6i-a31-i7.dtb \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31s-cs908.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
......@@ -555,15 +586,25 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-micro.dtb \
sun7i-a20-pcduino3.dtb
sun7i-a20-orangepi.dtb \
sun7i-a20-orangepi-mini.dtb \
sun7i-a20-pcduino3.dtb \
sun7i-a20-pcduino3-nano.dtb \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-harmony.dtb \
tegra20-iris-512.dtb \
......@@ -600,6 +641,11 @@ dtb-$(CONFIG_ARCH_U8500) += \
ste-hrefv60plus-tvk.dtb \
ste-ccu8540.dtb \
ste-ccu9540.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-sld3-ref.dtb \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
uniphier-ph1-sld8-ref.dtb
dtb-$(CONFIG_ARCH_VERSATILE) += \
versatile-ab.dtb \
versatile-pb.dtb
......@@ -624,6 +670,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
armada-370-db.dtb \
armada-370-dlink-dns327l.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-netgear-rn104.dtb \
......@@ -633,6 +680,8 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db-ap.dtb \
armada-385-linksys-caiman.dtb \
armada-385-linksys-cobra.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-rd.dtb
......@@ -649,12 +698,12 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-openblocks-ax3-4.dtb \
armada-xp-synology-ds414.dtb
dtb-$(CONFIG_MACH_DOVE) += \
dove-cm-a510.dtb \
dove-cubox.dtb \
dove-cubox-es.dtb \
dove-d2plug.dtb \
dove-d3plug.dtb \
dove-dove-db.dtb
dove-dove-db.dtb \
dove-sbc-a510.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
......
This diff is collapsed.
......@@ -81,6 +81,13 @@ i2c0_pins: pinmux_i2c0_pins {
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
......@@ -218,8 +225,67 @@ tps: tps@24 {
reg = <0x24>;
};
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
#address-cells = <1>;
#size-cells = <1>;
baseboard_data: baseboard_data@0 {
reg = <0 0x100>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <100000>;
cape_eeprom0: cape_eeprom0@54 {
compatible = "at,24c256";
reg = <0x54>;
#address-cells = <1>;
#size-cells = <1>;
cape0_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom1: cape_eeprom1@55 {
compatible = "at,24c256";
reg = <0x55>;
#address-cells = <1>;
#size-cells = <1>;
cape1_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom2: cape_eeprom2@56 {
compatible = "at,24c256";
reg = <0x56>;
#address-cells = <1>;
#size-cells = <1>;
cape2_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom3: cape_eeprom3@57 {
compatible = "at,24c256";
reg = <0x57>;
#address-cells = <1>;
#size-cells = <1>;
cape3_data: cape_data@0 {
reg = <0 0x100>;
};
};
};
/include/ "tps65217.dtsi"
&tps {
......
......@@ -8,6 +8,7 @@
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x EVM";
......@@ -38,6 +39,20 @@ lis3_reg: fixedregulator@1 {
regulator-boot-on;
};
wlan_en_reg: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* WLAN_EN GPIO for this board - Bank1, pin16 */
gpio = <&gpio1 16 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
......@@ -176,6 +191,15 @@ uart0_pins: pinmux_uart0_pins {
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
......@@ -266,6 +290,25 @@ mmc1_pins: pinmux_mmc1_pins {
>;
};
mmc3_pins: pinmux_mmc3_pins {
pinctrl-single,pins = <
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
>;
};
wlan_pins: pinmux_wlan_pins {
pinctrl-single,pins = <
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
>;
};
lcd_pins_s0: lcd_pins_s0 {
pinctrl-single,pins = <
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
......@@ -323,6 +366,13 @@ &uart0 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
......@@ -665,6 +715,37 @@ &mmc1 {
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
&mmc3 {
/* these are on the crossbar and are outlined in the
xbar-event-map element */
dmas = <&edma 12
&edma 13>;
dma-names = "tx", "rx";
status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlan_pins>;
ti,non-removable;
ti,needs-special-hs-handling;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
};
};
&edma {
ti,edma-xbar-event-map = /bits/ 16 <1 12
2 13>;
};
&sham {
status = "okay";
};
......
This diff is collapsed.
......@@ -60,6 +60,17 @@ uart4: serial@4809e000 {
dma-names = "tx", "rx";
clock-frequency = <48000000>;
};
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};
......
......@@ -21,6 +21,7 @@ / {
aliases {
display0 = &lcd0;
serial3 = &uart3;
};
vmmcsd_fixed: fixedregulator-sd {
......@@ -42,6 +43,15 @@ vtt_fixed: fixedregulator-vtt {
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
};
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
......@@ -106,9 +116,21 @@ lcd_in: endpoint {
};
};
};
/* fixed 12MHz oscillator */
refclk: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12000000>;
};
};
&am43xx_pinmux {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wlan_pins_default>;
pinctrl-1 = <&wlan_pins_sleep>;
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
......@@ -340,6 +362,53 @@ vpfe1_pins_sleep: vpfe1_pins_sleep {
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
>;
};
mmc3_pins_default: pinmux_mmc3_pins_default {
pinctrl-single,pins = <
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
>;
};
mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
pinctrl-single,pins = <
0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
>;
};
wlan_pins_default: pinmux_wlan_pins_default {
pinctrl-single,pins = <
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
>;
};
wlan_pins_sleep: pinmux_wlan_pins_sleep {
pinctrl-single,pins = <
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
0x5c (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
0x40 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
>;
};
uart3_pins: uart3_pins {
pinctrl-single,pins = <
0x228 (PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
0x22c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
0x230 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
>;
};
};
&i2c0 {
......@@ -403,6 +472,21 @@ ldo1: regulator-ldo1 {
regulator-always-on;
};
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&refclk 0>;
clock-names = "xvclk";
port {
ov2659_0: endpoint {
remote-endpoint = <&vpfe1_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
};
&i2c1 {
......@@ -422,6 +506,21 @@ pixcir_ts@5c {
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&refclk 0>;
clock-names = "xvclk";
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe0_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
};
&epwmss0 {
......@@ -446,6 +545,10 @@ &gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
......@@ -468,6 +571,43 @@ &mmc1 {
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
&mmc3 {
status = "okay";
/* these are on the crossbar and are outlined in the
xbar-event-map element */
dmas = <&edma 30
&edma 31>;
dma-names = "tx", "rx";
vmmc-supply = <&vmmcwl_fixed>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc3_pins_default>;
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
ti,non-removable;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
};
};
&edma {
ti,edma-xbar-event-map = /bits/ 16 <1 30
2 31>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&usb2_phy1 {
status = "okay";
};
......@@ -625,7 +765,7 @@ &vpfe0 {
port {
vpfe0_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
......@@ -642,7 +782,7 @@ &vpfe1 {
port {
vpfe1_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_0>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
......
......@@ -162,7 +162,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
compatible = "mx25l25635e", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};
......
/*
* Device Tree file for D-Link DNS-327L
*
* Copyright (C) 2015, Andrew Andrianov <andrew@ncrmnt.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* Remaining unsolved:
* There's still some unknown device on i2c address 0x13
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"
/ {
model = "D-Link DNS-327L";
compatible = "dlink,dns327l",
"marvell,armada370",
"marvell,armada-370-xp";
chosen {
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MiB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
nand@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
/* 1.0 MiB */
reg = <0x0000000 0x100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
/* 128 KiB */
reg = <0x100000 0x20000>;
read-only;
};
partition@120000 {
label = "uImage";
/* 7 MiB */
reg = <0x120000 0x700000>;
};
partition@820000 {
label = "ubifs";
/* ~ 84 MiB */
reg = <0x820000 0x54e0000>;
};
/* Hardcoded into stock bootloader */
partition@5d00000 {
label = "failsafe-uImage";
/* 5 MiB */
reg = <0x5d00000 0x500000>;
};
partition@6200000 {
label = "failsafe-fs";
/* 29 MiB */
reg = <0x6200000 0x1d00000>;
};
partition@7f00000 {
label = "bbt";
/* 1 MiB for BBT */
reg = <0x7f00000 0x100000>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <
&backup_button_pin
&power_button_pin
&reset_button_pin>;
pinctrl-names = "default";
power-button {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
backup-button {
label = "Backup Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
};
reset-button {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <
&sata_l_amber_pin
&sata_r_amber_pin
&backup_led_pin
/* Ensure these are managed by hardware */
&sata_l_white_pin
&sata_r_white_pin>;
pinctrl-names = "default";
sata-r-amber-pin {
label = "dns327l:amber:sata-r";
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
sata-l-amber-pin {
label = "dns327l:amber:sata-l";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
backup-led-pin {
label = "dns327l:white:usb";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-0 = <&xhci_pwr_pin>;
pinctrl-names = "default";
regulator-name = "USB3.0 Port Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
sata_r_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-0 = <&sata_r_pwr_pin>;
pinctrl-names = "default";
regulator-name = "SATA-R Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
sata_l_power: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-0 = <&sata_l_pwr_pin>;
pinctrl-names = "default";
regulator-name = "SATA-L Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
};
};
};
&pinctrl {
sata_l_white_pin: sata-l-white-pin {
marvell,pins = "mpp57";
marvell,function = "sata0";
};
sata_r_white_pin: sata-r-white-pin {
marvell,pins = "mpp55";
marvell,function = "sata1";
};
sata_r_amber_pin: sata-r-amber-pin {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
sata_l_amber_pin: sata-l-amber-pin {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
backup_led_pin: backup-led-pin {
marvell,pins = "mpp61";
marvell,function = "gpo";
};
xhci_pwr_pin: xhci-pwr-pin {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
sata_r_pwr_pin: sata-r-pwr-pin {
marvell,pins = "mpp54";
marvell,function = "gpio";
};
sata_l_pwr_pin: sata-l-pwr-pin {
marvell,pins = "mpp56";
marvell,function = "gpio";
};
uart1_pins: uart1-pins {
marvell,pins = "mpp60", "mpp61";
marvell,function = "uart1";
};
power_button_pin: power-button-pin {
marvell,pins = "mpp65";
marvell,function = "gpio";
};
backup_button_pin: backup-button-pin {
marvell,pins = "mpp63";
marvell,function = "gpio";
};
reset_button_pin: reset-button-pin {
marvell,pins = "mpp64";
marvell,function = "gpio";
};
};
/* Serial console */
&uart0 {
status = "okay";
};
/* Connected to Weltrend MCU */
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
marvell,reg-init = <0x0 0x16 0x0 0x0002>,
<0x0 0x19 0x0 0x0077>,
<0x0 0x18 0x0 0x5747>;
};
};
&eth1 {
phy = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&i2c0 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
status = "okay";
};
......@@ -92,7 +92,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064";
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
......
......@@ -149,7 +149,6 @@ rtc@10300 {
};
spi0: spi@10600 {
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -160,7 +159,6 @@ spi0: spi@10600 {
};
spi1: spi@10680 {
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
......
......@@ -139,11 +139,15 @@ L2: l2-cache {
* board level if a different configuration is used.
*/
spi0: spi@10600 {
compatible = "marvell,armada-370-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi0_pins1>;
pinctrl-names = "default";
};
spi1: spi@10680 {
compatible = "marvell,armada-370-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
};
......
......@@ -81,7 +81,7 @@ spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
......
......@@ -238,7 +238,8 @@ rtc@10300 {
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -249,7 +250,8 @@ spi0: spi@10600 {
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......
......@@ -70,7 +70,7 @@ spi1: spi@10680 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <54000000>;
};
......
/*
* Device Tree include for the Linksys WRT1200AC (Caiman)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT1200AC";
compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs{
i2c@11000 {
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
wan_amber@0 {
label = "caiman:amber:wan";
reg = <0x0>;
};
wan_white@1 {
label = "caiman:white:wan";
reg = <0x1>;
};
wlan_2g@2 {
label = "caiman:white:wlan_2g";
reg = <0x2>;
};
wlan_5g@3 {
label = "caiman:white:wlan_5g";
reg = <0x3>;
};
usb2@5 {
label = "caiman:white:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "caiman:white:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "caiman:white:usb3_2";
reg = <0x7>;
};
wps_white@8 {
label = "caiman:white:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "caiman:amber:wps";
reg = <0x9>;
};
};
};
};
};
gpio-leds {
power {
label = "caiman:white:power";
};
sata {
label = "caiman:white:sata";
};
};
};
/*
* Device Tree file for the Linksys WRT1900ACv2 (Cobra)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT1900ACv2";
compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs{
i2c@11000 {
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
wan_amber@0 {
label = "cobra:amber:wan";
reg = <0x0>;
};
wan_white@1 {
label = "cobra:white:wan";
reg = <0x1>;
};
wlan_2g@2 {
label = "cobra:white:wlan_2g";
reg = <0x2>;
};
wlan_5g@3 {
label = "cobra:white:wlan_5g";
reg = <0x3>;
};
usb2@5 {
label = "cobra:white:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "cobra:white:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "cobra:white:usb3_2";
reg = <0x7>;
};
wps_white@8 {
label = "cobra:white:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "cobra:amber:wps";
reg = <0x9>;
};
};
};
};
};
gpio-leds {
power {
label = "cobra:white:power";
};
sata {
label = "cobra:white:sata";
};
};
};
/*
* Device Tree include file for Armada 385 based Linksys boards
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"
/ {
model = "Linksys boards based on Armada 385";
compatible = "linksys,armada385", "marvell,armada385",
"marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "disabled";
};
i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
tmp421@4c {
compatible = "ti,tmp421";
reg = <0x4c>;
};
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9635";
reg = <0x68>;
};
};
/* J10: VCC, NC, RX, NC, TX, GND */
serial@12000 {
status = "okay";
};
ethernet@70000 {
status = "okay";
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@34000 {
status = "okay";
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
mdio {
status = "okay";
};
sata@a8000 {
status = "okay";
};
/* USB part of the eSATA/USB 2.0 port */
usb@50000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
usb-phy = <&usb3_phy>;
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x200000>; /* 2MB */
read-only;
};
partition@100000 {
label = "u_env";
reg = <0x200000 0x40000>; /* 256KB */
};
partition@140000 {
label = "s_env";
reg = <0x240000 0x40000>; /* 256KB */
};
partition@900000 {
label = "devinfo";
reg = <0x900000 0x100000>; /* 1MB */
read-only;
};
/* kernel1 overlaps with rootfs1 by design */
partition@a00000 {
label = "kernel1";
reg = <0xa00000 0x2800000>; /* 40MB */
};
partition@1000000 {
label = "rootfs1";
reg = <0x1000000 0x2200000>; /* 34MB */
};
/* kernel2 overlaps with rootfs2 by design */
partition@3200000 {
label = "kernel2";
reg = <0x3200000 0x2800000>; /* 40MB */
};
partition@3800000 {
label = "rootfs2";
reg = <0x3800000 0x2200000>; /* 34MB */
};
/*
* 38MB, last MB is for the BBT, not writable
*/
partition@5a00000 {
label = "syscfg";
reg = <0x5a00000 0x2600000>;
};
/*
* Unused area between "s_env" and "devinfo".
* Moved here because otherwise the renumbered
* partitions would break the bootloader
* supplied bootargs
*/
partition@180000 {
label = "unused_area";
reg = <0x280000 0x680000>; /* 6.5MB */
};
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Marvell 88W8864, 5GHz-only */
status = "okay";
};
pcie@2,0 {
/* Marvell 88W8864, 2GHz-only */
status = "okay";
};
};
};
usb3_phy: usb3_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_xhci0_vbus>;
};
reg_xhci0_vbus: xhci0-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
button@1 {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
button@2 {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&power_led_pin &sata_led_pin>;
pinctrl-names = "default";
power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
sata {
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth2>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
};
};
};
};
&pinctrl {
keys_pin: keys-pin {
marvell,pins = "mpp24", "mpp47";
marvell,function = "gpio";
};
power_led_pin: power-led-pin {
marvell,pins = "mpp55";
marvell,function = "gpio";
};
sata_led_pin: sata-led-pin {
marvell,pins = "mpp54";
marvell,function = "gpio";
};
xhci0_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp50";
marvell,function = "gpio";
};
};
......@@ -73,7 +73,7 @@ spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32";
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
......
......@@ -69,7 +69,7 @@ spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
......
......@@ -74,7 +74,7 @@ spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
......
......@@ -167,7 +167,8 @@ gic: interrupt-controller@d000 {
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -178,7 +179,8 @@ spi0: spi@10600 {
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -495,7 +497,7 @@ eth0: ethernet@70000 {
status = "disabled";
};
mdio@72004 {
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
......
......@@ -73,7 +73,7 @@ spi@10680 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "n25q128a13";
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
......
......@@ -128,7 +128,8 @@ gic: interrupt-controller@d000 {
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-390-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -139,7 +140,8 @@ spi0: spi@10600 {
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-390-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
......
......@@ -140,7 +140,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
......
......@@ -222,7 +222,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
compatible = "m25p64", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
......
......@@ -227,7 +227,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
......
......@@ -114,7 +114,7 @@ spi0: spi@10600 {
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064";
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
......
......@@ -85,10 +85,18 @@ L2: l2-cache {
};
spi0: spi@10600 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
spi1: spi@10680 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
......
......@@ -8,6 +8,12 @@ nvic: nv-interrupt-controller {
reg = <0xe000e100 0xc00>;
};
systick: timer@e000e010 {
compatible = "arm,armv7m-systick";
reg = <0xe000e010 0x10>;
status = "disabled";
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......
/*
* Device Tree file for Arietta G25
* This device tree is minimal, to activate more peripherals, see:
* http://dts.acmesystems.it/arietta/
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
/ {
model = "Acme Systems Arietta G25";
compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9";
aliases {
serial0 = &dbgu;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x8000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
mmc0: mmc@f0008000 {
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
usb2: gadget@f803c000 {
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
rtc@fffffeb0 {
status = "okay";
};
};
usb0: ohci@00600000 {
status = "okay";
num-ports = <3>;
};
usb1: ehci@00700000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
arietta_led {
label = "arietta_led";
gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
linux,default-trigger = "heartbeat";
};
};
};
/*
* kizbox.dts - Device Tree file for Overkiz Kizbox board
* at91-kizbox.dts - Device Tree file for Overkiz Kizbox board
*
* Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
* Copyright (C) 2012-2014 Boris BREZILLON <b.brezillon@overkiz.com>
* 2014-2015 Gaël PORTAY <g.portay@overkiz.com>
*
* Licensed under GPLv2.
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "at91sam9g20.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz kizbox";
model = "Overkiz Kizbox";
compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
};
memory {
......@@ -38,22 +40,18 @@ main_xtal {
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@fffb0000 {
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
usart1: serial@fffb4000 {
usart3: serial@fffd0000 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
dbgu: serial@fffff200 {
status = "okay";
};
......@@ -65,86 +63,97 @@ watchdog@fffffd40 {
};
};
usb0: ohci@00500000 {
num-ports = <1>;
status = "okay";
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
status = "okay";
bootloaderkernel@0 {
label = "bootloader-kernel";
reg = <0x0 0xc0000>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@c0000 {
ubi@20000 {
label = "ubi";
reg = <0xc0000 0x7f40000>;
reg = <0x20000 0x7fe0000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
reset {
label = "PB_RST";
gpios = <&pioB 30 GPIO_ACTIVE_HIGH>;
linux,code = <0x100>;
gpio-key,wakeup;
};
usb0: ohci@00500000 {
num-ports = <1>;
status = "okay";
user {
label = "PB_USER";
gpios = <&pioB 31 GPIO_ACTIVE_HIGH>;
linux,code = <0x101>;
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
pcf8563@51 {
/* nxp pcf8563 rtc */
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
leds {
compatible = "gpio-leds";
pwm_leds {
compatible = "pwm-leds";
led1g {
label = "led1:green";
gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
network_green {
label = "pwm:green:network";
pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
led1r {
label = "led1:red";
gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
network_red {
label = "pwm:red:network";
pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
led2g {
label = "led2:green";
gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "on";
user_green {
label = "pwm:green:user";
pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
led2r {
label = "led2:red";
gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
user_red {
label = "pwm:red:user";
pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
reset {
label = "reset";
gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
gpio-key,wakeup;
};
mode {
label = "mode";
gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
linux,code = <0x101>;
gpio-key,wakeup;
};
tcb_pwm: pwm {
compatible = "atmel,tcb-pwm";
#pwm-cells = <3>;
tc-block = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tcb1_tioa0
&pinctrl_tcb1_tioa1
&pinctrl_tcb1_tioa2
&pinctrl_tcb1_tiob0>;
};
};
/*
* at91-kizbox2.dts - Device Tree file for Overkiz Kizbox 2 board
*
* Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "sama5d31.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz Kizbox 2";
compatible = "overkiz,kizbox2", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
};
memory {
reg = <0x20000000 0x10000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
i2c1: i2c@f0018000 {
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
reg = <0x5b>;
status = "okay";
regulators {
vcc_1v8_reg: DCDC_REG1 {
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_1v2_reg: DCDC_REG2 {
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_3v3_reg: DCDC_REG3 {
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vddfuse_reg: LDO_REG1 {
regulator-name = "FUSE_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vddana_reg: LDO_REG2 {
regulator-name = "VDDANA";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vled_reg: LDO_REG3 {
regulator-name = "VLED";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
v3v8_rf_reg: LDO_REG4 {
regulator-name = "V3V8_RF";
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
regulator-always-on;
};
};
};
};
usart0: serial@f001c000 {
status = "okay";
};
usart1: serial@f0020000 {
status = "okay";
};
pwm0: pwm@f002c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwmh0_1
&pinctrl_pwm0_pwmh1_1
&pinctrl_pwm0_pwmh2_0>;
status = "okay";
};
adc0: adc@f8018000 {
atmel,adc-vref = <3333>;
status = "okay";
};
usart2: serial@f8020000 {
status = "okay";
};
macb1: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
dbgu: serial@ffffee00 {
status = "okay";
};
watchdog@fffffe40 {
status = "okay";
};
};
usb1: ohci@00600000 {
status = "okay";
};
usb2: ehci@00700000 {
status = "okay";
};
nand0: nand@60000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
prog {
label = "PB_PROG";
gpios = <&pioE 27 GPIO_ACTIVE_LOW>;
linux,code = <0x102>;
gpio-key,wakeup;
};
reset {
label = "PB_RST";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
gpio-key,wakeup;
};
user {
label = "PB_USER";
gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
linux,code = <0x101>;
gpio-key,wakeup;
};
};
pwm_leds {
compatible = "pwm-leds";
blue {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
green {
label = "pwm:green:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
label = "pwm:red:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
};
};
/*
* at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
*
* Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz Kizbox mini";
compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
};
memory {
reg = <0x20000000 0x8000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
apb {
usart0: serial@f801c000 {
status = "okay";
};
macb0: ethernet@f802c000 {
phy-mode = "rmii";
status = "okay";
};
pwm0: pwm@f8034000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffe40 {
status = "okay";
};
};
usb0: ohci@00600000 {
num-ports = <1>;
status = "okay";
};
usb1: ehci@00700000 {
status = "okay";
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
prog {
label = "PB_PROG";
gpios = <&pioC 17 GPIO_ACTIVE_LOW>;
linux,code = <0x102>;
gpio-key,wakeup;
};
reset {
label = "PB_RST";
gpios = <&pioC 16 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
pwm_leds {
compatible = "pwm-leds";
green {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
};
};
......@@ -14,7 +14,7 @@ / {
compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = "serial0:115200n8";
};
memory {
......@@ -35,6 +35,8 @@ ahb {
apb {
mmc0: mmc@f0000000 {
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
vmmc-supply = <&vcc_mmc0_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "okay";
slot@0 {
reg = <0>;
......@@ -43,6 +45,17 @@ slot@0 {
};
};
mmc1: mmc@f8000000 {
vmmc-supply = <&vcc_3v3_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "disabled";
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 1 GPIO_ACTIVE_LOW>;
};
};
spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
......@@ -105,7 +118,13 @@ vddana_reg: LDO_REG2 {
macb0: ethernet@f0028000 {
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@7 {
reg = <0x7>;
};
};
pwm0: pwm@f002c000 {
......@@ -215,12 +234,6 @@ pinctrl_usba_vbus: usba_vbus {
};
};
};
pmc: pmc@fffffc00 {
main: mainck {
clock-frequency = <12000000>;
};
};
};
nand0: nand@60000000 {
......@@ -284,6 +297,14 @@ usb2: ehci@00700000 {
};
};
vcc_mmc0_reg: fixedregulator@0 {
compatible = "regulator-fixed";
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
regulator-name = "mmc0-card-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
gpio_keys {
compatible = "gpio-keys";
......
......@@ -50,7 +50,8 @@ / {
compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
bootargs = "ignore_loglevel earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
......@@ -106,6 +107,8 @@ phy0: ethernet-phy@1 {
mmc1: mmc@fc000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
vmmc-supply = <&vcc_mmc1_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "okay";
slot@0 {
reg = <0>;
......@@ -122,6 +125,11 @@ usart4: serial@fc010000 {
status = "okay";
};
spi1: spi@fc018000 {
cs-gpios = <&pioB 21 0>;
status = "okay";
};
adc0: adc@fc034000 {
atmel,adc-vref = <3300>;
status = "okay";
......@@ -238,4 +246,22 @@ d10 {
linux,default-trigger = "heartbeat";
};
};
vcc_3v3_reg: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "VCC 3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_mmc1_reg: fixedregulator@1 {
compatible = "regulator-fixed";
gpio = <&pioE 4 GPIO_ACTIVE_LOW>;
regulator-name = "VDD MCI1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_reg>;
};
};
......@@ -50,7 +50,8 @@ / {
compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
chosen {
bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
bootargs = "ignore_loglevel earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
......@@ -108,8 +109,8 @@ adc0: adc@fc034000 {
mmc0: mmc@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
slot@1 {
reg = <1>;
slot@0 {
reg = <0>;
bus-width = <4>;
cd-gpios = <&pioE 5 0>;
};
......
......@@ -940,8 +940,8 @@ usb0: ohci@00300000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00300000 0x100000>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
......
......@@ -12,6 +12,10 @@ / {
model = "Atmel AT91RM9200 evaluation kit";
compatible = "atmel,at91rm9200ek", "atmel,at91rm9200";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
......
......@@ -1008,8 +1008,8 @@ usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
......
......@@ -75,8 +75,8 @@ usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&ohci_clk>, <&hclk0>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&ohci_clk>, <&hclk0>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
......
......@@ -13,7 +13,8 @@ / {
compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw";
stdout-path = "serial0:115200n8";
};
memory {
......
......@@ -1010,8 +1010,8 @@ usb0: ohci@00a00000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
......
......@@ -13,7 +13,8 @@ / {
compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
stdout-path = "serial0:115200n8";
};
memory {
......
......@@ -10,7 +10,8 @@
/ {
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
stdout-path = "serial0:115200n8";
};
memory {
......
......@@ -1291,8 +1291,8 @@ usb0: ohci@00700000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
......@@ -1300,8 +1300,8 @@ usb1: ehci@00800000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00800000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&utmi>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
clocks = <&utmi>, <&uhphs_clk>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
};
......
......@@ -15,7 +15,8 @@ / {
compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
stdout-path = "serial0:115200n8";
};
memory {
......
......@@ -949,9 +949,8 @@ usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x00100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
<&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
};
......
......@@ -14,7 +14,8 @@ / {
compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2";
stdout-path = "serial0:115200n8";
};
memory {
......
......@@ -1065,13 +1065,6 @@ clk32k: slck {
};
};
rtc@fffffeb0 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
rtc@fffffd20 {
compatible = "atmel,at91sam9260-rtt";
reg = <0xfffffd20 0x10>;
......@@ -1085,6 +1078,14 @@ gpbr: syscon@fffffd60 {
reg = <0xfffffd60 0x10>;
status = "disabled";
};
rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
};
};
......
......@@ -13,7 +13,8 @@ / {
compatible = "atmel,at91sam9rlek", "atmel,at91sam9rl", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
stdout-path = "serial0:115200n8";
};
memory {
......@@ -181,13 +182,11 @@ pinctrl_board_mmc0: mmc0-board {
};
};
pmc: pmc@fffffc00 {
main: mainck {
clock-frequency = <12000000>;
};
watchdog@fffffd40 {
status = "okay";
};
watchdog@fffffd40 {
rtc@fffffe00 {
status = "okay";
};
};
......
......@@ -505,7 +505,7 @@ pinctrl_usart1_cts: usart1_cts-0 {
pinctrl_usart1_sck: usart1_sck-0 {
atmel,pins =
<AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
};
};
......@@ -694,6 +694,52 @@ pinctrl_i2c_gpio2: i2c_gpio2-0 {
};
};
pwm0 {
pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
atmel,pins =
<AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
atmel,pins =
<AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
atmel,pins =
<AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
atmel,pins =
<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
atmel,pins =
<AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
atmel,pins =
<AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
atmel,pins =
<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
atmel,pins =
<AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
atmel,pins =
<AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
tcb0 {
pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
......@@ -1176,8 +1222,8 @@ usb0: ohci@00600000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00600000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
clock-names = "ohci_clk", "hclk", "uhpck";
status = "disabled";
};
......@@ -1185,8 +1231,8 @@ usb1: ehci@00700000 {
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
reg = <0x00700000 0x100000>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
clock-names = "usb_clk", "ehci_clk", "uhpck";
clocks = <&utmi>, <&uhphs_clk>;
clock-names = "usb_clk", "ehci_clk";
status = "disabled";
};
};
......
......@@ -13,7 +13,8 @@ / {
compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
stdout-path = "serial0:115200n8";
};
ahb {
......
......@@ -18,11 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
......
......@@ -212,6 +212,18 @@ uart3: serial@18023000 {
status = "disabled";
};
nand: nand@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18046000 0x600>, <0xf8105408 0x600>, <0x18046f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
brcm,nand-has-wp;
};
gic: interrupt-controller@19021000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
......
/dts-v1/;
/include/ "bcm2835-rpi.dtsi"
#include "bcm2835-rpi.dtsi"
/ {
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
......@@ -25,6 +25,6 @@ &gpio {
/* I2S interface */
i2s_alt0: i2s_alt0 {
brcm,pins = <18 19 20 21>;
brcm,function = <4>; /* alt0 */
brcm,function = <BCM2835_FSEL_ALT0>;
};
};
/dts-v1/;
/include/ "bcm2835-rpi.dtsi"
#include "bcm2835-rpi.dtsi"
/ {
compatible = "raspberrypi,model-b", "brcm,bcm2835";
......@@ -18,6 +18,6 @@ &gpio {
/* I2S interface */
i2s_alt2: i2s_alt2 {
brcm,pins = <28 29 30 31>;
brcm,function = <6>; /* alt2 */
brcm,function = <BCM2835_FSEL_ALT2>;
};
};
/include/ "bcm2835.dtsi"
#include "bcm2835.dtsi"
/ {
memory {
......@@ -21,17 +21,17 @@ &gpio {
gpioout: gpioout {
brcm,pins = <6>;
brcm,function = <1>; /* GPIO out */
brcm,function = <BCM2835_FSEL_GPIO_OUT>;
};
alt0: alt0 {
brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
brcm,function = <4>; /* alt0 */
brcm,function = <BCM2835_FSEL_ALT0>;
};
alt3: alt3 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <7>; /* alt3 */
brcm,function = <BCM2835_FSEL_ALT3>;
};
};
......
/include/ "skeleton.dtsi"
#include <dt-bindings/pinctrl/bcm2835.h>
#include "skeleton.dtsi"
/ {
compatible = "brcm,bcm2835";
......@@ -14,6 +15,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x7e000000 0x20000000 0x02000000>;
dma-ranges = <0x40000000 0x00000000 0x20000000>;
timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
......@@ -60,6 +62,13 @@ rng@7e104000 {
reg = <0x7e104000 0x10>;
};
mailbox: mailbox@7e00b800 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
#mbox-cells = <0>;
};
gpio: gpio@7e200000 {
compatible = "brcm,bcm2835-gpio";
reg = <0x7e200000 0xb4>;
......@@ -112,7 +121,7 @@ spi: spi@7e204000 {
status = "disabled";
};
i2c0: i2c@20205000 {
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
......
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Asus RT-AC56U
*
* Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "asus,rt-ac56u", "brcm,bcm4708";
model = "Asus RT-AC56U (BCM4708)";
chosen {
bootargs = "console=ttyS0,115200";
};
memory {
reg = <0x00000000 0x08000000>;
};
leds {
compatible = "gpio-leds";
usb3 {
label = "bcm53xx:blue:usb3";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
wan {
label = "bcm53xx:blue:wan";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
lan {
label = "bcm53xx:blue:lan";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
power {
label = "bcm53xx:blue:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
all {
label = "bcm53xx:blue:all";
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
2ghz {
label = "bcm53xx:blue:2ghz";
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
usb2 {
label = "bcm53xx:blue:usb2";
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-off";
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
};
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
};
};
};
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......@@ -10,6 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
......@@ -47,6 +48,12 @@ hc595: gpio_spi@0 {
leds {
compatible = "gpio-leds";
usb {
label = "bcm53xx:blue:usb";
gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-off";
};
power0 {
label = "bcm53xx:red:power";
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
......
......@@ -10,6 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "luxul,xwc-1000", "brcm,bcm4708";
......@@ -23,12 +24,8 @@ memory {
reg = <0x00000000 0x08000000>;
};
axi@18000000 {
nand@28000 {
reg = <0x00028000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
nand: nand@18028000 {
nandcs@0 {
partition@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
......
......@@ -10,6 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "netgear,r6250v1", "brcm,bcm4708";
......
......@@ -10,6 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "netgear,r6300v2", "brcm,bcm4708";
......
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