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Commit 4295c8cc authored by Charles Keepax's avatar Charles Keepax Committed by Mark Brown
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ASoC: cs35l41: Fix a bunch of trivial code formating/style issues 

Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210914141349.30218-6-ckeepax@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 3e60abeb
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Showing with 467 additions and 496 deletions
sound/soc/codecs/cs35l41-i2c.c
View file @ 4295c8cc
...@@ -64,8 +64,7 @@ static int cs35l41_i2c_probe(struct i2c_client *client, ...@@ -64,8 +64,7 @@ static int cs35l41_i2c_probe(struct i2c_client *client,
cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config); cs35l41->regmap = devm_regmap_init_i2c(client, regmap_config);
if (IS_ERR(cs35l41->regmap)) { if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap); ret = PTR_ERR(cs35l41->regmap);
dev_err(cs35l41->dev, "Failed to allocate register map: %d\n", dev_err(cs35l41->dev, "Failed to allocate register map: %d\n", ret);
ret);
return ret; return ret;
} }
......
sound/soc/codecs/cs35l41-spi.c
View file @ 4295c8cc
...@@ -73,24 +73,19 @@ static void cs35l41_spi_otp_setup(struct cs35l41_private *cs35l41, ...@@ -73,24 +73,19 @@ static void cs35l41_spi_otp_setup(struct cs35l41_private *cs35l41,
static int cs35l41_spi_probe(struct spi_device *spi) static int cs35l41_spi_probe(struct spi_device *spi)
{ {
const struct regmap_config *regmap_config = &cs35l41_regmap_spi; const struct regmap_config *regmap_config = &cs35l41_regmap_spi;
struct cs35l41_platform_data *pdata = struct cs35l41_platform_data *pdata = dev_get_platdata(&spi->dev);
dev_get_platdata(&spi->dev);
struct cs35l41_private *cs35l41; struct cs35l41_private *cs35l41;
int ret; int ret;
cs35l41 = devm_kzalloc(&spi->dev, cs35l41 = devm_kzalloc(&spi->dev, sizeof(struct cs35l41_private), GFP_KERNEL);
sizeof(struct cs35l41_private),
GFP_KERNEL);
if (!cs35l41) if (!cs35l41)
return -ENOMEM; return -ENOMEM;
spi_set_drvdata(spi, cs35l41); spi_set_drvdata(spi, cs35l41);
cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config); cs35l41->regmap = devm_regmap_init_spi(spi, regmap_config);
if (IS_ERR(cs35l41->regmap)) { if (IS_ERR(cs35l41->regmap)) {
ret = PTR_ERR(cs35l41->regmap); ret = PTR_ERR(cs35l41->regmap);
dev_err(&spi->dev, "Failed to allocate register map: %d\n", dev_err(&spi->dev, "Failed to allocate register map: %d\n", ret);
ret);
return ret; return ret;
} }
......
sound/soc/codecs/cs35l41-tables.c
View file @ 4295c8cc
...@@ -9,42 +9,42 @@ ...@@ -9,42 +9,42 @@
#include "cs35l41.h" #include "cs35l41.h"
const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = { const struct reg_default cs35l41_reg[CS35L41_MAX_CACHE_REG] = {
{CS35L41_PWR_CTRL1, 0x00000000}, { CS35L41_PWR_CTRL1, 0x00000000 },
{CS35L41_PWR_CTRL3, 0x01000010}, { CS35L41_PWR_CTRL3, 0x01000010 },
{CS35L41_GPIO_PAD_CONTROL, 0x00000000}, { CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
{CS35L41_SP_ENABLES, 0x00000000}, { CS35L41_SP_ENABLES, 0x00000000 },
{CS35L41_SP_RATE_CTRL, 0x00000028}, { CS35L41_SP_RATE_CTRL, 0x00000028 },
{CS35L41_SP_FORMAT, 0x18180200}, { CS35L41_SP_FORMAT, 0x18180200 },
{CS35L41_SP_HIZ_CTRL, 0x00000002}, { CS35L41_SP_HIZ_CTRL, 0x00000002 },
{CS35L41_SP_FRAME_TX_SLOT, 0x03020100}, { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
{CS35L41_SP_FRAME_RX_SLOT, 0x00000100}, { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
{CS35L41_SP_TX_WL, 0x00000018}, { CS35L41_SP_TX_WL, 0x00000018 },
{CS35L41_SP_RX_WL, 0x00000018}, { CS35L41_SP_RX_WL, 0x00000018 },
{CS35L41_DAC_PCM1_SRC, 0x00000008}, { CS35L41_DAC_PCM1_SRC, 0x00000008 },
{CS35L41_ASP_TX1_SRC, 0x00000018}, { CS35L41_ASP_TX1_SRC, 0x00000018 },
{CS35L41_ASP_TX2_SRC, 0x00000019}, { CS35L41_ASP_TX2_SRC, 0x00000019 },
{CS35L41_ASP_TX3_SRC, 0x00000020}, { CS35L41_ASP_TX3_SRC, 0x00000020 },
{CS35L41_ASP_TX4_SRC, 0x00000021}, { CS35L41_ASP_TX4_SRC, 0x00000021 },
{CS35L41_DSP1_RX1_SRC, 0x00000008}, { CS35L41_DSP1_RX1_SRC, 0x00000008 },
{CS35L41_DSP1_RX2_SRC, 0x00000009}, { CS35L41_DSP1_RX2_SRC, 0x00000009 },
{CS35L41_DSP1_RX3_SRC, 0x00000018}, { CS35L41_DSP1_RX3_SRC, 0x00000018 },
{CS35L41_DSP1_RX4_SRC, 0x00000019}, { CS35L41_DSP1_RX4_SRC, 0x00000019 },
{CS35L41_DSP1_RX5_SRC, 0x00000020}, { CS35L41_DSP1_RX5_SRC, 0x00000020 },
{CS35L41_DSP1_RX6_SRC, 0x00000021}, { CS35L41_DSP1_RX6_SRC, 0x00000021 },
{CS35L41_DSP1_RX7_SRC, 0x0000003A}, { CS35L41_DSP1_RX7_SRC, 0x0000003A },
{CS35L41_DSP1_RX8_SRC, 0x00000001}, { CS35L41_DSP1_RX8_SRC, 0x00000001 },
{CS35L41_NGATE1_SRC, 0x00000008}, { CS35L41_NGATE1_SRC, 0x00000008 },
{CS35L41_NGATE2_SRC, 0x00000009}, { CS35L41_NGATE2_SRC, 0x00000009 },
{CS35L41_AMP_DIG_VOL_CTRL, 0x00008000}, { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
{CS35L41_CLASSH_CFG, 0x000B0405}, { CS35L41_CLASSH_CFG, 0x000B0405 },
{CS35L41_WKFET_CFG, 0x00000111}, { CS35L41_WKFET_CFG, 0x00000111 },
{CS35L41_NG_CFG, 0x00000033}, { CS35L41_NG_CFG, 0x00000033 },
{CS35L41_AMP_GAIN_CTRL, 0x00000273}, { CS35L41_AMP_GAIN_CTRL, 0x00000273 },
{CS35L41_GPIO1_CTRL1, 0xE1000001}, { CS35L41_GPIO1_CTRL1, 0xE1000001 },
{CS35L41_GPIO2_CTRL1, 0xE1000001}, { CS35L41_GPIO2_CTRL1, 0xE1000001 },
{CS35L41_MIXER_NGATE_CFG, 0x00000000}, { CS35L41_MIXER_NGATE_CFG, 0x00000000 },
{CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303}, { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
{CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303}, { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
}; };
bool cs35l41_readable_reg(struct device *dev, unsigned int reg) bool cs35l41_readable_reg(struct device *dev, unsigned int reg)
...@@ -349,216 +349,213 @@ bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) ...@@ -349,216 +349,213 @@ bool cs35l41_volatile_reg(struct device *dev, unsigned int reg)
} }
} }
static const struct cs35l41_otp_packed_element_t static const struct cs35l41_otp_packed_element_t otp_map_1[CS35L41_NUM_OTP_ELEM] = {
otp_map_1[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */ /* addr shift size */
{0x00002030, 0, 4}, /*TRIM_OSC_FREQ_TRIM*/ { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{0x00002030, 7, 1}, /*TRIM_OSC_TRIM_DONE*/ { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{0x0000208c, 24, 6}, /*TST_DIGREG_VREF_TRIM*/ { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{0x00002090, 14, 4}, /*TST_REF_TRIM*/ { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{0x00002090, 10, 4}, /*TST_REF_TEMPCO_TRIM*/ { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{0x0000300C, 11, 4}, /*PLL_LDOA_TST_VREF_TRIM*/ { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{0x0000394C, 23, 2}, /*BST_ATEST_CM_VOFF*/ { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{0x00003950, 0, 7}, /*BST_ATRIM_IADC_OFFSET*/ { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{0x00003950, 8, 7}, /*BST_ATRIM_IADC_GAIN1*/ { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{0x00003950, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET1*/ { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{0x00003950, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN1*/ { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{0x00003954, 0, 7}, /*BST_ATRIM_IADC_OFFSET2*/ { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{0x00003954, 8, 7}, /*BST_ATRIM_IADC_GAIN2*/ { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{0x00003954, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET2*/ { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{0x00003954, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN2*/ { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{0x00003958, 0, 7}, /*BST_ATRIM_IADC_OFFSET3*/ { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{0x00003958, 8, 7}, /*BST_ATRIM_IADC_GAIN3*/ { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{0x00003958, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET3*/ { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{0x00003958, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN3*/ { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{0x0000395C, 0, 7}, /*BST_ATRIM_IADC_OFFSET4*/ { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{0x0000395C, 8, 7}, /*BST_ATRIM_IADC_GAIN4*/ { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{0x0000395C, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET4*/ { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{0x0000395C, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN4*/ { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{0x0000416C, 0, 8}, /*VMON_GAIN_OTP_VAL*/ { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{0x00004160, 0, 7}, /*VMON_OFFSET_OTP_VAL*/ { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{0x0000416C, 8, 8}, /*IMON_GAIN_OTP_VAL*/ { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{0x00004160, 16, 10}, /*IMON_OFFSET_OTP_VAL*/ { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{0x0000416C, 16, 12}, /*VMON_CM_GAIN_OTP_VAL*/ { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{0x0000416C, 28, 1}, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{0x00004170, 0, 6}, /*IMON_CAL_TEMPCO_OTP_VAL*/ { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{0x00004170, 6, 1}, /*IMON_CAL_TEMPCO_SIGN_OTP*/ { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{0x00004170, 8, 6}, /*IMON_CAL_TEMPCO2_OTP_VAL*/ { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{0x00004170, 14, 1}, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{0x00004170, 16, 9}, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{0x00004360, 0, 5}, /*TEMP_GAIN_OTP_VAL*/ { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{0x00004360, 6, 9}, /*TEMP_OFFSET_OTP_VAL*/ { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{0x00004448, 0, 8}, /*VP_SARADC_OFFSET*/ { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{0x00004448, 8, 8}, /*VP_GAIN_INDEX*/ { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{0x00004448, 16, 8}, /*VBST_SARADC_OFFSET*/ { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{0x00004448, 24, 8}, /*VBST_GAIN_INDEX*/ { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{0x0000444C, 0, 3}, /*ANA_SELINVREF*/ { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{0x00006E30, 0, 5}, /*GAIN_ERR_COEFF_0*/ { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{0x00006E30, 8, 5}, /*GAIN_ERR_COEFF_1*/ { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{0x00006E30, 16, 5}, /*GAIN_ERR_COEFF_2*/ { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{0x00006E30, 24, 5}, /*GAIN_ERR_COEFF_3*/ { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{0x00006E34, 0, 5}, /*GAIN_ERR_COEFF_4*/ { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{0x00006E34, 8, 5}, /*GAIN_ERR_COEFF_5*/ { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{0x00006E34, 16, 5}, /*GAIN_ERR_COEFF_6*/ { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{0x00006E34, 24, 5}, /*GAIN_ERR_COEFF_7*/ { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{0x00006E38, 0, 5}, /*GAIN_ERR_COEFF_8*/ { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{0x00006E38, 8, 5}, /*GAIN_ERR_COEFF_9*/ { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{0x00006E38, 16, 5}, /*GAIN_ERR_COEFF_10*/ { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{0x00006E38, 24, 5}, /*GAIN_ERR_COEFF_11*/ { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{0x00006E3C, 0, 5}, /*GAIN_ERR_COEFF_12*/ { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{0x00006E3C, 8, 5}, /*GAIN_ERR_COEFF_13*/ { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{0x00006E3C, 16, 5}, /*GAIN_ERR_COEFF_14*/ { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{0x00006E3C, 24, 5}, /*GAIN_ERR_COEFF_15*/ { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{0x00006E40, 0, 5}, /*GAIN_ERR_COEFF_16*/ { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{0x00006E40, 8, 5}, /*GAIN_ERR_COEFF_17*/ { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{0x00006E40, 16, 5}, /*GAIN_ERR_COEFF_18*/ { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{0x00006E40, 24, 5}, /*GAIN_ERR_COEFF_19*/ { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{0x00006E44, 0, 5}, /*GAIN_ERR_COEFF_20*/ { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{0x00006E48, 0, 10}, /*VOFF_GAIN_0*/ { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{0x00006E48, 10, 10}, /*VOFF_GAIN_1*/ { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{0x00006E48, 20, 10}, /*VOFF_GAIN_2*/ { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{0x00006E4C, 0, 10}, /*VOFF_GAIN_3*/ { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{0x00006E4C, 10, 10}, /*VOFF_GAIN_4*/ { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{0x00006E4C, 20, 10}, /*VOFF_GAIN_5*/ { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{0x00006E50, 0, 10}, /*VOFF_GAIN_6*/ { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{0x00006E50, 10, 10}, /*VOFF_GAIN_7*/ { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{0x00006E50, 20, 10}, /*VOFF_GAIN_8*/ { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{0x00006E54, 0, 10}, /*VOFF_GAIN_9*/ { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{0x00006E54, 10, 10}, /*VOFF_GAIN_10*/ { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{0x00006E54, 20, 10}, /*VOFF_GAIN_11*/ { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{0x00006E58, 0, 10}, /*VOFF_GAIN_12*/ { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{0x00006E58, 10, 10}, /*VOFF_GAIN_13*/ { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{0x00006E58, 20, 10}, /*VOFF_GAIN_14*/ { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{0x00006E5C, 0, 10}, /*VOFF_GAIN_15*/ { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{0x00006E5C, 10, 10}, /*VOFF_GAIN_16*/ { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{0x00006E5C, 20, 10}, /*VOFF_GAIN_17*/ { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{0x00006E60, 0, 10}, /*VOFF_GAIN_18*/ { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{0x00006E60, 10, 10}, /*VOFF_GAIN_19*/ { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{0x00006E60, 20, 10}, /*VOFF_GAIN_20*/ { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{0x00006E64, 0, 10}, /*VOFF_INT1*/ { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{0x00007418, 7, 5}, /*DS_SPK_INT1_CAP_TRIM*/ { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{0x0000741C, 0, 5}, /*DS_SPK_INT2_CAP_TRIM*/ { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{0x0000741C, 11, 4}, /*DS_SPK_LPF_CAP_TRIM*/ { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{0x0000741C, 19, 4}, /*DS_SPK_QUAN_CAP_TRIM*/ { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{0x00007434, 17, 1}, /*FORCE_CAL*/ { 0x00007434, 17, 1 }, /*FORCE_CAL*/
{0x00007434, 18, 7}, /*CAL_OVERRIDE*/ { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{0x00007068, 0, 9}, /*MODIX*/ { 0x00007068, 0, 9 }, /*MODIX*/
{0x0000410C, 7, 1}, /*VIMON_DLY_NOT_COMB*/ { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{0x0000400C, 0, 7}, /*VIMON_DLY*/ { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{0x00000000, 0, 1}, /*extra bit*/ { 0x00000000, 0, 1 }, /*extra bit*/
{0x00017040, 0, 8}, /*X_COORDINATE*/ { 0x00017040, 0, 8 }, /*X_COORDINATE*/
{0x00017040, 8, 8}, /*Y_COORDINATE*/ { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{0x00017040, 16, 8}, /*WAFER_ID*/ { 0x00017040, 16, 8 }, /*WAFER_ID*/
{0x00017040, 24, 8}, /*DVS*/ { 0x00017040, 24, 8 }, /*DVS*/
{0x00017044, 0, 24}, /*LOT_NUMBER*/ { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
}; };
static const struct cs35l41_otp_packed_element_t static const struct cs35l41_otp_packed_element_t otp_map_2[CS35L41_NUM_OTP_ELEM] = {
otp_map_2[CS35L41_NUM_OTP_ELEM] = {
/* addr shift size */ /* addr shift size */
{0x00002030, 0, 4}, /*TRIM_OSC_FREQ_TRIM*/ { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
{0x00002030, 7, 1}, /*TRIM_OSC_TRIM_DONE*/ { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
{0x0000208c, 24, 6}, /*TST_DIGREG_VREF_TRIM*/ { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
{0x00002090, 14, 4}, /*TST_REF_TRIM*/ { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
{0x00002090, 10, 4}, /*TST_REF_TEMPCO_TRIM*/ { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
{0x0000300C, 11, 4}, /*PLL_LDOA_TST_VREF_TRIM*/ { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
{0x0000394C, 23, 2}, /*BST_ATEST_CM_VOFF*/ { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
{0x00003950, 0, 7}, /*BST_ATRIM_IADC_OFFSET*/ { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
{0x00003950, 8, 7}, /*BST_ATRIM_IADC_GAIN1*/ { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
{0x00003950, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET1*/ { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
{0x00003950, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN1*/ { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
{0x00003954, 0, 7}, /*BST_ATRIM_IADC_OFFSET2*/ { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
{0x00003954, 8, 7}, /*BST_ATRIM_IADC_GAIN2*/ { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
{0x00003954, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET2*/ { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
{0x00003954, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN2*/ { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
{0x00003958, 0, 7}, /*BST_ATRIM_IADC_OFFSET3*/ { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
{0x00003958, 8, 7}, /*BST_ATRIM_IADC_GAIN3*/ { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
{0x00003958, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET3*/ { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
{0x00003958, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN3*/ { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
{0x0000395C, 0, 7}, /*BST_ATRIM_IADC_OFFSET4*/ { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
{0x0000395C, 8, 7}, /*BST_ATRIM_IADC_GAIN4*/ { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
{0x0000395C, 16, 8}, /*BST_ATRIM_IPKCOMP_OFFSET4*/ { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
{0x0000395C, 24, 8}, /*BST_ATRIM_IPKCOMP_GAIN4*/ { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
{0x0000416C, 0, 8}, /*VMON_GAIN_OTP_VAL*/ { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
{0x00004160, 0, 7}, /*VMON_OFFSET_OTP_VAL*/ { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
{0x0000416C, 8, 8}, /*IMON_GAIN_OTP_VAL*/ { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
{0x00004160, 16, 10}, /*IMON_OFFSET_OTP_VAL*/ { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
{0x0000416C, 16, 12}, /*VMON_CM_GAIN_OTP_VAL*/ { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
{0x0000416C, 28, 1}, /*VMON_CM_GAIN_SIGN_OTP_VAL*/ { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
{0x00004170, 0, 6}, /*IMON_CAL_TEMPCO_OTP_VAL*/ { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
{0x00004170, 6, 1}, /*IMON_CAL_TEMPCO_SIGN_OTP*/ { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
{0x00004170, 8, 6}, /*IMON_CAL_TEMPCO2_OTP_VAL*/ { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
{0x00004170, 14, 1}, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/ { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
{0x00004170, 16, 9}, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/ { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
{0x00004360, 0, 5}, /*TEMP_GAIN_OTP_VAL*/ { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
{0x00004360, 6, 9}, /*TEMP_OFFSET_OTP_VAL*/ { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
{0x00004448, 0, 8}, /*VP_SARADC_OFFSET*/ { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
{0x00004448, 8, 8}, /*VP_GAIN_INDEX*/ { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
{0x00004448, 16, 8}, /*VBST_SARADC_OFFSET*/ { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
{0x00004448, 24, 8}, /*VBST_GAIN_INDEX*/ { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
{0x0000444C, 0, 3}, /*ANA_SELINVREF*/ { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
{0x00006E30, 0, 5}, /*GAIN_ERR_COEFF_0*/ { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
{0x00006E30, 8, 5}, /*GAIN_ERR_COEFF_1*/ { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
{0x00006E30, 16, 5}, /*GAIN_ERR_COEFF_2*/ { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
{0x00006E30, 24, 5}, /*GAIN_ERR_COEFF_3*/ { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
{0x00006E34, 0, 5}, /*GAIN_ERR_COEFF_4*/ { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
{0x00006E34, 8, 5}, /*GAIN_ERR_COEFF_5*/ { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
{0x00006E34, 16, 5}, /*GAIN_ERR_COEFF_6*/ { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
{0x00006E34, 24, 5}, /*GAIN_ERR_COEFF_7*/ { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
{0x00006E38, 0, 5}, /*GAIN_ERR_COEFF_8*/ { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
{0x00006E38, 8, 5}, /*GAIN_ERR_COEFF_9*/ { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
{0x00006E38, 16, 5}, /*GAIN_ERR_COEFF_10*/ { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
{0x00006E38, 24, 5}, /*GAIN_ERR_COEFF_11*/ { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
{0x00006E3C, 0, 5}, /*GAIN_ERR_COEFF_12*/ { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
{0x00006E3C, 8, 5}, /*GAIN_ERR_COEFF_13*/ { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
{0x00006E3C, 16, 5}, /*GAIN_ERR_COEFF_14*/ { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
{0x00006E3C, 24, 5}, /*GAIN_ERR_COEFF_15*/ { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
{0x00006E40, 0, 5}, /*GAIN_ERR_COEFF_16*/ { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
{0x00006E40, 8, 5}, /*GAIN_ERR_COEFF_17*/ { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
{0x00006E40, 16, 5}, /*GAIN_ERR_COEFF_18*/ { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
{0x00006E40, 24, 5}, /*GAIN_ERR_COEFF_19*/ { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
{0x00006E44, 0, 5}, /*GAIN_ERR_COEFF_20*/ { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
{0x00006E48, 0, 10}, /*VOFF_GAIN_0*/ { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
{0x00006E48, 10, 10}, /*VOFF_GAIN_1*/ { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
{0x00006E48, 20, 10}, /*VOFF_GAIN_2*/ { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
{0x00006E4C, 0, 10}, /*VOFF_GAIN_3*/ { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
{0x00006E4C, 10, 10}, /*VOFF_GAIN_4*/ { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
{0x00006E4C, 20, 10}, /*VOFF_GAIN_5*/ { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
{0x00006E50, 0, 10}, /*VOFF_GAIN_6*/ { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
{0x00006E50, 10, 10}, /*VOFF_GAIN_7*/ { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
{0x00006E50, 20, 10}, /*VOFF_GAIN_8*/ { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
{0x00006E54, 0, 10}, /*VOFF_GAIN_9*/ { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
{0x00006E54, 10, 10}, /*VOFF_GAIN_10*/ { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
{0x00006E54, 20, 10}, /*VOFF_GAIN_11*/ { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
{0x00006E58, 0, 10}, /*VOFF_GAIN_12*/ { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
{0x00006E58, 10, 10}, /*VOFF_GAIN_13*/ { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
{0x00006E58, 20, 10}, /*VOFF_GAIN_14*/ { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
{0x00006E5C, 0, 10}, /*VOFF_GAIN_15*/ { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
{0x00006E5C, 10, 10}, /*VOFF_GAIN_16*/ { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
{0x00006E5C, 20, 10}, /*VOFF_GAIN_17*/ { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
{0x00006E60, 0, 10}, /*VOFF_GAIN_18*/ { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
{0x00006E60, 10, 10}, /*VOFF_GAIN_19*/ { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
{0x00006E60, 20, 10}, /*VOFF_GAIN_20*/ { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
{0x00006E64, 0, 10}, /*VOFF_INT1*/ { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
{0x00007418, 7, 5}, /*DS_SPK_INT1_CAP_TRIM*/ { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
{0x0000741C, 0, 5}, /*DS_SPK_INT2_CAP_TRIM*/ { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
{0x0000741C, 11, 4}, /*DS_SPK_LPF_CAP_TRIM*/ { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
{0x0000741C, 19, 4}, /*DS_SPK_QUAN_CAP_TRIM*/ { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
{0x00007434, 17, 1}, /*FORCE_CAL*/ { 0x00007434, 17, 1 }, /*FORCE_CAL*/
{0x00007434, 18, 7}, /*CAL_OVERRIDE*/ { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
{0x00007068, 0, 9}, /*MODIX*/ { 0x00007068, 0, 9 }, /*MODIX*/
{0x0000410C, 7, 1}, /*VIMON_DLY_NOT_COMB*/ { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
{0x0000400C, 0, 7}, /*VIMON_DLY*/ { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
{0x00004000, 11, 1}, /*VMON_POL*/ { 0x00004000, 11, 1 }, /*VMON_POL*/
{0x00017040, 0, 8}, /*X_COORDINATE*/ { 0x00017040, 0, 8 }, /*X_COORDINATE*/
{0x00017040, 8, 8}, /*Y_COORDINATE*/ { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
{0x00017040, 16, 8}, /*WAFER_ID*/ { 0x00017040, 16, 8 }, /*WAFER_ID*/
{0x00017040, 24, 8}, /*DVS*/ { 0x00017040, 24, 8 }, /*DVS*/
{0x00017044, 0, 24}, /*LOT_NUMBER*/ { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
}; };
const struct cs35l41_otp_map_element_t const struct cs35l41_otp_map_element_t cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = {
cs35l41_otp_map_map[CS35L41_NUM_OTP_MAPS] = {
{ {
.id = 0x01, .id = 0x01,
.map = otp_map_1, .map = otp_map_1,
......
sound/soc/codecs/cs35l41.c
View file @ 4295c8cc
...@@ -166,7 +166,8 @@ static const unsigned char cs35l41_bst_k2_table[4][5] = { ...@@ -166,7 +166,8 @@ static const unsigned char cs35l41_bst_k2_table[4][5] = {
}; };
static const unsigned char cs35l41_bst_slope_table[4] = { static const unsigned char cs35l41_bst_slope_table[4] = {
0x75, 0x6B, 0x3B, 0x28}; 0x75, 0x6B, 0x3B, 0x28
};
static int cs35l41_get_fs_mon_config_index(int freq) static int cs35l41_get_fs_mon_config_index(int freq)
{ {
...@@ -189,7 +190,8 @@ static const struct snd_kcontrol_new dre_ctrl = ...@@ -189,7 +190,8 @@ static const struct snd_kcontrol_new dre_ctrl =
SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
static const char * const cs35l41_pcm_sftramp_text[] = { static const char * const cs35l41_pcm_sftramp_text[] = {
"Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"}; "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
};
static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
CS35L41_AMP_DIG_VOL_CTRL, 0, CS35L41_AMP_DIG_VOL_CTRL, 0,
...@@ -206,20 +208,16 @@ static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, ...@@ -206,20 +208,16 @@ static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
static const struct snd_kcontrol_new pcm_source_mux = static const struct snd_kcontrol_new pcm_source_mux =
SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
static const char * const cs35l41_tx_input_texts[] = {"Zero", "ASPRX1", static const char * const cs35l41_tx_input_texts[] = {
"ASPRX2", "VMON", "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
"IMON", "VPMON", "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
"VBSTMON", };
"DSPTX1", "DSPTX2"};
static const unsigned int cs35l41_tx_input_values[] = {0x00, static const unsigned int cs35l41_tx_input_values[] = {
CS35L41_INPUT_SRC_ASPRX1, 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
CS35L41_INPUT_SRC_ASPRX2, CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
CS35L41_INPUT_SRC_IMON, };
CS35L41_INPUT_SRC_VPMON,
CS35L41_INPUT_SRC_VBSTMON,
CS35L41_INPUT_DSP_TX1,
CS35L41_INPUT_DSP_TX2};
static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
CS35L41_ASP_TX1_SRC, CS35L41_ASP_TX1_SRC,
...@@ -309,8 +307,7 @@ static int cs35l41_otp_unpack(void *data) ...@@ -309,8 +307,7 @@ static int cs35l41_otp_unpack(void *data)
u32 otp_val, otp_id_reg; u32 otp_val, otp_id_reg;
u32 *otp_mem; u32 *otp_mem;
otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL);
GFP_KERNEL);
if (!otp_mem) if (!otp_mem)
return -ENOMEM; return -ENOMEM;
...@@ -372,7 +369,6 @@ static int cs35l41_otp_unpack(void *data) ...@@ -372,7 +369,6 @@ static int cs35l41_otp_unpack(void *data)
(32 - bit_offset); (32 - bit_offset);
bit_offset += otp_map[i].size - 32; bit_offset += otp_map[i].size - 32;
} else { } else {
otp_val = (otp_mem[word_offset] & otp_val = (otp_mem[word_offset] &
GENMASK(bit_offset + otp_map[i].size - 1, GENMASK(bit_offset + otp_map[i].size - 1,
bit_offset)) >> bit_offset; bit_offset)) >> bit_offset;
...@@ -393,7 +389,8 @@ static int cs35l41_otp_unpack(void *data) ...@@ -393,7 +389,8 @@ static int cs35l41_otp_unpack(void *data)
otp_map[i].shift), otp_map[i].shift),
otp_val << otp_map[i].shift); otp_val << otp_map[i].shift);
if (ret < 0) { if (ret < 0) {
dev_err(cs35l41->dev, "Write OTP val failed: %d\n", ret); dev_err(cs35l41->dev, "Write OTP val failed: %d\n",
ret);
goto err_otp_unpack; goto err_otp_unpack;
} }
} }
...@@ -501,8 +498,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data) ...@@ -501,8 +498,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data)
CS35L41_BST_OVP_ERR_RLS, 0); CS35L41_BST_OVP_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT);
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED; ret = IRQ_HANDLED;
} }
...@@ -520,8 +516,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data) ...@@ -520,8 +516,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data)
CS35L41_BST_UVP_ERR_RLS, 0); CS35L41_BST_UVP_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT);
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED; ret = IRQ_HANDLED;
} }
...@@ -539,8 +534,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data) ...@@ -539,8 +534,7 @@ static irqreturn_t cs35l41_irq(int irq, void *data)
CS35L41_BST_SHORT_ERR_RLS, 0); CS35L41_BST_SHORT_ERR_RLS, 0);
regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2,
CS35L41_BST_EN_MASK, CS35L41_BST_EN_MASK,
CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT);
CS35L41_BST_EN_SHIFT);
ret = IRQ_HANDLED; ret = IRQ_HANDLED;
} }
...@@ -566,10 +560,8 @@ static const struct reg_sequence cs35l41_pdn_patch[] = { ...@@ -566,10 +560,8 @@ static const struct reg_sequence cs35l41_pdn_patch[] = {
static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event) struct snd_kcontrol *kcontrol, int event)
{ {
struct snd_soc_component *component = struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
snd_soc_dapm_to_component(w->dapm); struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
struct cs35l41_private *cs35l41 =
snd_soc_component_get_drvdata(component);
unsigned int val; unsigned int val;
int ret = 0; int ret = 0;
bool pdn; bool pdn;
...@@ -608,6 +600,7 @@ static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, ...@@ -608,6 +600,7 @@ static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
ret = -EINVAL; ret = -EINVAL;
} }
return ret; return ret;
} }
...@@ -647,7 +640,6 @@ static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { ...@@ -647,7 +640,6 @@ static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
}; };
static const struct snd_soc_dapm_route cs35l41_audio_map[] = { static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
{"ASP TX1 Source", "VMON", "VMON ADC"}, {"ASP TX1 Source", "VMON", "VMON ADC"},
{"ASP TX1 Source", "IMON", "IMON ADC"}, {"ASP TX1 Source", "IMON", "IMON ADC"},
{"ASP TX1 Source", "VPMON", "VPMON ADC"}, {"ASP TX1 Source", "VPMON", "VPMON ADC"},
...@@ -696,15 +688,13 @@ static const struct snd_soc_dapm_route cs35l41_audio_map[] = { ...@@ -696,15 +688,13 @@ static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
{"PCM Source", "ASP", "ASPRX1"}, {"PCM Source", "ASP", "ASPRX1"},
{"CLASS H", NULL, "PCM Source"}, {"CLASS H", NULL, "PCM Source"},
}; };
static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num,
unsigned int *tx_slot, unsigned int rx_num, unsigned int *tx_slot, unsigned int rx_num,
unsigned int *rx_slot) unsigned int *rx_slot)
{ {
struct cs35l41_private *cs35l41 = struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
snd_soc_component_get_drvdata(dai->component);
unsigned int val, mask; unsigned int val, mask;
int i; int i;
...@@ -732,10 +722,9 @@ static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, ...@@ -732,10 +722,9 @@ static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num,
return 0; return 0;
} }
static int cs35l41_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{ {
struct cs35l41_private *cs35l41 = struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
snd_soc_component_get_drvdata(codec_dai->component);
unsigned int daifmt = 0; unsigned int daifmt = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
...@@ -808,8 +797,7 @@ static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, ...@@ -808,8 +797,7 @@ static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai) struct snd_soc_dai *dai)
{ {
struct cs35l41_private *cs35l41 = struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
snd_soc_component_get_drvdata(dai->component);
unsigned int rate = params_rate(params); unsigned int rate = params_rate(params);
u8 asp_wl; u8 asp_wl;
int i; int i;
...@@ -877,16 +865,16 @@ static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, ...@@ -877,16 +865,16 @@ static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
{ {
if (substream->runtime) if (substream->runtime)
return snd_pcm_hw_constraint_list(substream->runtime, 0, return snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &cs35l41_constraints); SNDRV_PCM_HW_PARAM_RATE,
&cs35l41_constraints);
return 0; return 0;
} }
static int cs35l41_component_set_sysclk(struct snd_soc_component *component, static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
int clk_id, int source, unsigned int freq, int clk_id, int source,
int dir) unsigned int freq, int dir)
{ {
struct cs35l41_private *cs35l41 = struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
snd_soc_component_get_drvdata(component);
int extclk_cfg, clksrc; int extclk_cfg, clksrc;
switch (clk_id) { switch (clk_id) {
...@@ -936,24 +924,24 @@ static int cs35l41_component_set_sysclk(struct snd_soc_component *component, ...@@ -936,24 +924,24 @@ static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir) int clk_id, unsigned int freq, int dir)
{ {
struct cs35l41_private *cs35l41 = struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
snd_soc_component_get_drvdata(dai->component);
unsigned int fs1_val; unsigned int fs1_val;
unsigned int fs2_val; unsigned int fs2_val;
unsigned int val; unsigned int val;
int fsIndex; int fsindex;
fsIndex = cs35l41_get_fs_mon_config_index(freq); fsindex = cs35l41_get_fs_mon_config_index(freq);
if (fsIndex < 0) { if (fsindex < 0) {
dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
return -EINVAL; return -EINVAL;
} }
dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
if (freq <= 6144000) { if (freq <= 6144000) {
/* Use the lookup table */ /* Use the lookup table */
fs1_val = cs35l41_fs_mon[fsIndex].fs1; fs1_val = cs35l41_fs_mon[fsindex].fs1;
fs2_val = cs35l41_fs_mon[fsIndex].fs2; fs2_val = cs35l41_fs_mon[fsindex].fs2;
} else { } else {
/* Use hard-coded values */ /* Use hard-coded values */
fs1_val = 0x10; fs1_val = 0x10;
...@@ -989,8 +977,7 @@ static int cs35l41_boost_config(struct cs35l41_private *cs35l41, ...@@ -989,8 +977,7 @@ static int cs35l41_boost_config(struct cs35l41_private *cs35l41,
bst_lbst_val = 3; bst_lbst_val = 3;
break; break;
default: default:
dev_err(dev, "Invalid boost inductor value: %d nH\n", dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind);
boost_ind);
return -EINVAL; return -EINVAL;
} }
...@@ -1032,7 +1019,7 @@ static int cs35l41_boost_config(struct cs35l41_private *cs35l41, ...@@ -1032,7 +1019,7 @@ static int cs35l41_boost_config(struct cs35l41_private *cs35l41,
return ret; return ret;
} }
if ((boost_ipk < 1600) || (boost_ipk > 4500)) { if (boost_ipk < 1600 || boost_ipk > 4500) {
dev_err(dev, "Invalid boost inductor peak current: %d mA\n", dev_err(dev, "Invalid boost inductor peak current: %d mA\n",
boost_ipk); boost_ipk);
return -EINVAL; return -EINVAL;
...@@ -1191,10 +1178,8 @@ static int cs35l41_handle_pdata(struct device *dev, ...@@ -1191,10 +1178,8 @@ static int cs35l41_handle_pdata(struct device *dev,
"cirrus,gpio1-output-enable"); "cirrus,gpio1-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", ret = device_property_read_u32(dev, "cirrus,gpio1-src-select",
&val); &val);
if (ret >= 0) { if (ret >= 0)
val |= CS35L41_VALID_PDATA; irq_gpio1_config->irq_src_sel = val | CS35L41_VALID_PDATA;
irq_gpio1_config->irq_src_sel = val;
}
/* GPIO2 Pin Config */ /* GPIO2 Pin Config */
irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev, irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev,
...@@ -1203,10 +1188,8 @@ static int cs35l41_handle_pdata(struct device *dev, ...@@ -1203,10 +1188,8 @@ static int cs35l41_handle_pdata(struct device *dev,
"cirrus,gpio2-output-enable"); "cirrus,gpio2-output-enable");
ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", ret = device_property_read_u32(dev, "cirrus,gpio2-src-select",
&val); &val);
if (ret >= 0) { if (ret >= 0)
val |= CS35L41_VALID_PDATA; irq_gpio2_config->irq_src_sel = val | CS35L41_VALID_PDATA;
irq_gpio2_config->irq_src_sel = val;
}
return 0; return 0;
} }
...@@ -1266,8 +1249,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, ...@@ -1266,8 +1249,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
if (pdata) { if (pdata) {
cs35l41->pdata = *pdata; cs35l41->pdata = *pdata;
} else { } else {
ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata, ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata, cs35l41);
cs35l41);
if (ret != 0) if (ret != 0)
return ret; return ret;
} }
...@@ -1278,16 +1260,13 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, ...@@ -1278,16 +1260,13 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
cs35l41->supplies); cs35l41->supplies);
if (ret != 0) { if (ret != 0) {
dev_err(cs35l41->dev, dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
"Failed to request core supplies: %d\n",
ret);
return ret; return ret;
} }
ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
if (ret != 0) { if (ret != 0) {
dev_err(cs35l41->dev, dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
"Failed to enable core supplies: %d\n", ret);
return ret; return ret;
} }
...@@ -1394,8 +1373,8 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, ...@@ -1394,8 +1373,8 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
CS35L41_INT1_MASK_DEFAULT); CS35L41_INT1_MASK_DEFAULT);
ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
cs35l41_irq, IRQF_ONESHOT | IRQF_SHARED | irq_pol, IRQF_ONESHOT | IRQF_SHARED | irq_pol,
"cs35l41", cs35l41); "cs35l41", cs35l41);
/* CS35L41 needs INT for PDN_DONE */ /* CS35L41 needs INT for PDN_DONE */
...@@ -1452,6 +1431,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, ...@@ -1452,6 +1431,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41,
err: err:
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
return ret; return ret;
} }
...@@ -1460,6 +1440,7 @@ int cs35l41_remove(struct cs35l41_private *cs35l41) ...@@ -1460,6 +1440,7 @@ int cs35l41_remove(struct cs35l41_private *cs35l41)
regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
return 0; return 0;
} }
......
sound/soc/codecs/cs35l41.h
View file @ 4295c8cc
...@@ -691,7 +691,6 @@ ...@@ -691,7 +691,6 @@
#define CS35L41_TEMP_WARN_ERR_RLS 0x20 #define CS35L41_TEMP_WARN_ERR_RLS 0x20
#define CS35L41_TEMP_ERR_RLS 0x40 #define CS35L41_TEMP_ERR_RLS 0x40
#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F #define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F
#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF #define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF
#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF #define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF
...@@ -709,7 +708,7 @@ ...@@ -709,7 +708,7 @@
#define CS35L41_GPIO_POL_SHIFT 12 #define CS35L41_GPIO_POL_SHIFT 12
#define CS35L41_AMP_INV_PCM_SHIFT 14 #define CS35L41_AMP_INV_PCM_SHIFT 14
#define CS35L41_AMP_INV_PCM_MASK (1 << CS35L41_AMP_INV_PCM_SHIFT) #define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT)
#define CS35L41_AMP_PCM_VOL_SHIFT 3 #define CS35L41_AMP_PCM_VOL_SHIFT 3
#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3) #define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3)
#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF #define CS35L41_AMP_PCM_VOL_MUTE 0x4CF
......
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