Commit 4393a8f9 authored by Ben Dooks's avatar Ben Dooks Committed by Russell King

[ARM PATCH] 2092/1: S3C2410 - gpio bugfix and additions

Patch from Ben Dooks

Fix inverted mask in s3c2410_gpio_setpin() function,
add s3c2410_modify_misccr() for shared register, and
add s3c2410_gpio_getpin()

Signed-off-by: Ben Dooks 
parent ffafcaaf
...@@ -19,6 +19,10 @@ ...@@ -19,6 +19,10 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* *
* Changelog
* 13-Sep-2004 BJD Implemented change of MISCCR
* 14-Sep-2004 BJD Added getpin call
* 14-Sep-2004 BJD Fixed bug in setpin() call
*/ */
...@@ -90,9 +94,32 @@ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) ...@@ -90,9 +94,32 @@ void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
local_irq_save(flags); local_irq_save(flags);
dat = __raw_readl(base + 0x04); dat = __raw_readl(base + 0x04);
dat &= 1 << offs; dat &= ~(1 << offs);
dat |= to << offs; dat |= to << offs;
__raw_writel(dat, base + 0x04); __raw_writel(dat, base + 0x04);
local_irq_restore(flags); local_irq_restore(flags);
} }
unsigned int s3c2410_gpio_getpin(unsigned int pin)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
return __raw_readl(base + 0x04) & (1<< offs);
}
unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
{
unsigned long flags;
unsigned long misccr;
local_irq_save(flags);
misccr = __raw_readl(S3C2410_MISCCR);
misccr &= ~clear;
misccr ^= change;
__raw_writel(misccr, S3C2410_MISCCR);
local_irq_restore(flags);
return misccr;
}
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
* 06-Jun-2003 BJD Added CPU frequency settings * 06-Jun-2003 BJD Added CPU frequency settings
* 03-Sep-2003 BJD Linux v2.6 support * 03-Sep-2003 BJD Linux v2.6 support
* 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars * 12-Mar-2004 BJD Fixed include protection, fixed type of clock vars
* 14-Sep-2004 BJD Added misccr and getpin to gpio
*/ */
#ifndef __ASM_ARCH_HARDWARE_H #ifndef __ASM_ARCH_HARDWARE_H
...@@ -61,6 +62,10 @@ extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); ...@@ -61,6 +62,10 @@ extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#include <asm/sizes.h> #include <asm/sizes.h>
......
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