Merge nuts.ninka.net:/home/davem/src/BK/sparcwork-2.5

into nuts.ninka.net:/home/davem/src/BK/sparc-2.5

arch/sparc/kernel/head.S

@@ -25,6 +25,7 @@
 #include <asm/winmacro.h>
 #include <asm/thread_info.h>	/* TI_UWINMASK */
 #include <asm/errno.h>
+#include <asm/pgtsrmmu.h>	/* SRMMU_PGDIR_SHIFT */
 
 	.data
 /* 
@@ -623,12 +624,8 @@ srmmu_remap:
 		/* Ok, pull in the PTD. */
 		lda	[%o1] ASI_M_BYPASS, %o2		! This is the 0x0 16MB pgd
 
-		/* Calculate to KERNBASE entry.
-		 *
-		 * XXX Should not use empirical constant, but Gas gets an  XXX
-		 * XXX upset stomach with the bitshift I would have to use XXX
-		 */
-		add	%o1, 0x3c0, %o3		
+		/* Calculate to KERNBASE entry. */
+		add	%o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3		
 
 		/* Poke the entry into the calculated address. */
 		sta	%o2, [%o3] ASI_M_BYPASS
@@ -672,7 +669,7 @@ srmmu_nviking:
 		sll	%g1, 0x8, %g1			! make phys addr for l1 tbl
 
 		lda	[%g1] ASI_M_BYPASS, %g2		! get level1 entry for 0x0
-		add	%g1, 0x3c0, %g3			! XXX AWAY WITH EMPIRICALS
+		add	%g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
 		sta	%g2, [%g3] ASI_M_BYPASS		! place at KERNBASE entry
 		b	go_to_highmem
 		 nop					! wheee....

arch/sparc64/defconfig

@@ -619,6 +619,12 @@ CONFIG_YELLOWFIN=m
 CONFIG_R8169=m
 CONFIG_SK98LIN=m
 CONFIG_TIGON3=m
+
+#
+# Ethernet (10000 Mbit)
+#
+CONFIG_IXGB=m
+CONFIG_IXGB_NAPI=y
 CONFIG_FDDI=y
 # CONFIG_DEFXX is not set
 CONFIG_SKFP=m
@@ -756,7 +762,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT3_FS=m
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_JBD=y
+CONFIG_JBD=m
 # CONFIG_JBD_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
@@ -1047,12 +1053,28 @@ CONFIG_USB_HPUSBSCSI=m
 # USB Network adaptors
 #
 CONFIG_USB_CATC=m
-CONFIG_USB_CDCETHER=m
 CONFIG_USB_KAWETH=m
 CONFIG_USB_PEGASUS=m
 CONFIG_USB_RTL8150=m
 CONFIG_USB_USBNET=m
 
+#
+# USB Host-to-Host Cables
+#
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_GENESYS=y
+CONFIG_USB_NET1080=y
+CONFIG_USB_PL2301=y
+
+#
+# Intelligent USB Devices/Gadgets
+#
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_ZAURUS=y
+CONFIG_USB_CDCETHER=y
+
 #
 # USB port drivers
 #
@@ -1123,6 +1145,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y
 # Bluetooth device drivers
 #
 CONFIG_BT_HCIUSB=m
+CONFIG_BT_USB_SCO=y
 CONFIG_BT_USB_ZERO_PACKET=y
 CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_H4=y

arch/sparc64/kernel/ioctl32.c

@@ -115,7 +115,6 @@
 #define EXT2_IOC32_GETVERSION             _IOR('v', 1, int)
 #define EXT2_IOC32_SETVERSION             _IOW('v', 2, int)
 
-extern asmlinkage int sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
 
 static int w_long(unsigned int fd, unsigned int cmd, unsigned long arg)
 {

drivers/video/aty/Makefile

@@ -4,5 +4,4 @@ obj-$(CONFIG_FB_ATY128) += aty128fb.o
 atyfb-y				:= atyfb_base.o mach64_accel.o
 atyfb-$(CONFIG_FB_ATY_GX)	+= mach64_gx.o
 atyfb-$(CONFIG_FB_ATY_CT)	+= mach64_ct.o mach64_cursor.o
-atyfb-$(CONFIG_FB_ATY_XL_INIT)	+= xlinit.o
 atyfb-objs			:= $(atyfb-y)

drivers/video/aty/atyfb.h

@@ -36,17 +36,13 @@ struct pll_ct {
 	u8 pll_ref_div;
 	u8 pll_gen_cntl;
 	u8 mclk_fb_div;
-	u8 mclk_fb_mult;	/* 2 ro 4 */
-	u8 sclk_fb_div;
 	u8 pll_vclk_cntl;
 	u8 vclk_post_div;
 	u8 vclk_fb_div;
 	u8 pll_ext_cntl;
-	u8 spll_cntl2;
 	u32 dsp_config;		/* Mach64 GTB DSP */
 	u32 dsp_on_off;		/* Mach64 GTB DSP */
 	u8 mclk_post_div_real;
-	u8 xclk_post_div_real;
 	u8 vclk_post_div_real;
 };
 
@@ -79,7 +75,6 @@ struct atyfb_par {
 	u32 ref_clk_per;
 	u32 pll_per;
 	u32 mclk_per;
-	u32 xclk_per;
 	u8 bus_type;
 	u8 ram_type;
 	u8 mem_refresh_rate;
@@ -123,7 +118,7 @@ struct atyfb_par {
 #define M64F_EXTRA_BRIGHT	0x00020000
 #define M64F_LT_SLEEP		0x00040000
 #define M64F_XL_DLL		0x00080000
-#define M64F_MFB_TIMES_4	0x00100000
+
 
     /*
      *  Register access
@@ -156,33 +151,6 @@ static inline void aty_st_le32(int regindex, u32 val,
 #endif
 }
 
-static inline u16 aty_ld_le16(int regindex, const struct atyfb_par *par)
-{
-	/* Hack for bloc 1, should be cleanly optimized by compiler */
-	if (regindex >= 0x400)
-		regindex -= 0x800;
-
-#if defined(__mc68000__)
-	return le16_to_cpu(*((volatile u16 *)(par->ati_regbase + regindex)));
-#else
-	return readw(par->ati_regbase + regindex);
-#endif
-}
-
-static inline void aty_st_le16(int regindex, u16 val,
-				const struct atyfb_par *par)
-{
-	/* Hack for bloc 1, should be cleanly optimized by compiler */
-	if (regindex >= 0x400)
-		regindex -= 0x800;
-
-#if defined(__mc68000__)
-	*((volatile u16 *)(par->ati_regbase + regindex)) = cpu_to_le16(val);
-#else
-	writew(val, par->ati_regbase + regindex);
-#endif
-}
-
 static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
 {
 	/* Hack for bloc 1, should be cleanly optimized by compiler */
@@ -221,19 +189,6 @@ static inline u8 aty_ld_pll(int offset, const struct atyfb_par *par)
 }
 
 
-/* 
- * CT Family only.
- */
-static inline void aty_st_pll(int offset, u8 val,
-				const struct atyfb_par *par)
-{
-	/* write addr byte */
-	aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, par);
-	/* write the register value */
-	aty_st_8(CLOCK_CNTL + 2, val, par);
-	aty_st_8(CLOCK_CNTL + 1, (offset << 2) & ~PLL_WR_EN, par); 
-}
-
     /*
      *  DAC operations
      */

drivers/video/aty/mach64_cursor.c

@@ -135,10 +135,6 @@ static void aty_set_cursor(struct fb_info *info)
 			yoff = 0;
 		}
 
-		/* In doublescan mode, the cursor location also needs to be
-		   doubled. */
-                if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
-			y<<=1;
 		wait_for_fifo(4, par);
 		aty_st_le32(CUR_OFFSET, (info->fix.smem_len >> 3) + (yoff << 1),
 			    par);
@@ -168,7 +164,7 @@ int atyfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 
 #ifdef __sparc__
 	if (par->mmaped)
-		return;
+		return 0;
 #endif
 
 	aty_set_cursor(info);
@@ -192,7 +188,7 @@ struct aty_cursor *__init aty_init_cursor(struct fb_info *info)
 	info->fix.smem_len -= PAGE_SIZE;
 
 #ifdef __sparc__
-	addr = info->screen_base - 0x800000 + info->fix.smem_len;
+	addr = (unsigned long) info->screen_base - 0x800000 + info->fix.smem_len;
 	cursor->ram = (u8 *) addr;
 #else
 #ifdef __BIG_ENDIAN

drivers/video/aty/mach64_gx.c

+
 /*
  *  ATI Mach64 GX Support
  */
 
 #include <linux/delay.h>
 #include <linux/fb.h>
+#include <linux/sched.h>
 
 #include <asm/io.h>
 
@@ -337,8 +339,8 @@ const struct aty_dac_ops aty_dac_att21c498 = {
      *  ATI 18818 / ICS 2595 Clock Chip
      */
 
-static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per,
-				u8 bpp, union aty_pll *pll)
+static int aty_var_to_pll_18818(const struct fb_info *info,
+				u32 vclk_per, u8 bpp, union aty_pll *pll)
 {
 	u32 MHz100;		/* in 0.01 MHz */
 	u32 program_bits;
@@ -493,7 +495,7 @@ const struct aty_pll_ops aty_pll_ati18818_1 = {
      *  STG 1703 Clock Chip
      */
 
-static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per,
+static int aty_var_to_pll_1703(const struct fb_info *info,
 			       u32 vclk_per, u8 bpp, union aty_pll *pll)
 {
 	u32 mhz100;		/* in 0.01 MHz */
@@ -609,7 +611,7 @@ const struct aty_pll_ops aty_pll_stg1703 = {
      *  Chrontel 8398 Clock Chip
      */
 
-static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per,
+static int aty_var_to_pll_8398(const struct fb_info *info,
 			       u32 vclk_per, u8 bpp, union aty_pll *pll)
 {
 	u32 tempA, tempB, fOut, longMHz100, diff, preDiff;

drivers/video/cfbimgblt.c

@@ -73,8 +73,11 @@ static u32 cfb_tab32[] = {
 	0x00000000, 0xffffffff
 };
 
+#define FB_WRITEL fb_writel
+#define FB_READL  fb_readl
+
 #if defined (__BIG_ENDIAN)
-#define LEFT_POS(bpp)          (BITS_PER_LONG - bpp)
+#define LEFT_POS(bpp)          (32 - bpp)
 #define SHIFT_HIGH(val, bits)  ((val) >> (bits))
 #define SHIFT_LOW(val, bits)   ((val) << (bits))
 #else
@@ -83,47 +86,27 @@ static u32 cfb_tab32[] = {
 #define SHIFT_LOW(val, bits)   ((val) >> (bits))
 #endif
 
-#if BITS_PER_LONG == 32
-#define FB_WRITEL	fb_writel
-#define FB_READL	fb_readl
-#define INIT_FASTPATH	{}
-#define FASTPATH	fb_writel((end_mask & eorx)^bgx, dst++)
-#else
-#define FB_WRITEL	fb_writeq
-#define FB_READL	fb_readq
-#define INIT_FASTPATH	unsigned long val = 0, bpl = 0
-#define FASTPATH {					\
-	val |= SHIFT_HIGH((end_mask & eorx)^bgx, bpl);	\
-	bpl += 32;					\
-	bpl &= BITS_PER_LONG - 1;			\
-	if (!bpl) {					\
-		FB_WRITEL(val, dst++);			\
-		val = 0;				\
-	}						\
-}
-#endif
-
 static inline void color_imageblit(const struct fb_image *image, 
 				   struct fb_info *p, u8 *dst1, 
-				   unsigned long start_index,
-				   unsigned long pitch_index)
+				   u32 start_index,
+				   u32 pitch_index)
 {
 	/* Draw the penguin */
-	unsigned long *dst, *dst2, color = 0, val, shift;
+	u32 *dst, *dst2, color = 0, val, shift;
 	int i, n, bpp = p->var.bits_per_pixel;
-	unsigned long null_bits = BITS_PER_LONG - bpp;
+	u32 null_bits = 32 - bpp;
 	u32 *palette = (u32 *) p->pseudo_palette;
-	u8 *src = (u8 *) image->data;
+	const u8 *src = image->data;
 
-	dst2 = (unsigned long *) dst1;
+	dst2 = (u32 *) dst1;
 	for (i = image->height; i--; ) {
-		dst = (unsigned long *) dst1;
 		n = image->width;
-		shift = val = 0;
+		dst = (u32 *) dst1;
+		shift = 0;
+		val = 0;
 		
 		if (start_index) {
-			unsigned long start_mask = ~(SHIFT_HIGH(~0UL,
-								start_index));
+			u32 start_mask = ~(SHIFT_HIGH(~(u32)0, start_index));
 			val = FB_READL(dst) & start_mask;
 			shift = start_index;
 		}
@@ -139,14 +122,14 @@ static inline void color_imageblit(const struct fb_image *image,
 				FB_WRITEL(val, dst++);
 	
 				val = (shift == null_bits) ? 0 : 
-					SHIFT_LOW(color,BITS_PER_LONG - shift);
+					SHIFT_LOW(color, 32 - shift);
 			}
 			shift += bpp;
-			shift &= (BITS_PER_LONG - 1);
+			shift &= (32 - 1);
 			src++;
 		}
 		if (shift) {
-			unsigned long  end_mask = SHIFT_HIGH(~0UL, shift);
+			u32 end_mask = SHIFT_HIGH(~(u32)0, shift);
 
 			FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
 		}
@@ -154,41 +137,39 @@ static inline void color_imageblit(const struct fb_image *image,
 		if (pitch_index) {
 			dst2 += p->fix.line_length;
 			dst1 = (char *) dst2;
-			(unsigned long) dst1 &= ~(sizeof(unsigned long) - 1);
+			(unsigned long) dst1 &= ~(sizeof(u32) - 1);
 
 			start_index += pitch_index;
-			start_index &= BITS_PER_LONG - 1;
+			start_index &= 32 - 1;
 		}
 	}
 }
 
-static inline void slow_imageblit(const struct fb_image *image, 
-				  struct fb_info *p, u8 *dst1, 
-				  unsigned long fgcolor,
-				  unsigned long bgcolor, 
-				  unsigned long start_index,
-				  unsigned long pitch_index)
+static inline void slow_imageblit(const struct fb_image *image, struct fb_info *p, 
+				  u8 *dst1, u32 fgcolor,
+				  u32 bgcolor, 
+				  u32 start_index,
+				  u32 pitch_index)
 {
-	unsigned long shift, color = 0, bpp = p->var.bits_per_pixel;
-	unsigned long *dst, *dst2, val, pitch = p->fix.line_length;
-	unsigned long null_bits = BITS_PER_LONG - bpp;
-	unsigned long spitch = (image->width+7)/8;
-	const char *src = image->data, *s;
-	unsigned long i, j, l;
+	u32 shift, color = 0, bpp = p->var.bits_per_pixel;
+	u32 *dst, *dst2, val, pitch = p->fix.line_length;
+	u32 null_bits = 32 - bpp;
+	u32 spitch = (image->width+7)/8;
+	const u8 *src = image->data, *s;
+	u32 i, j, l;
 	
-	dst2 = (unsigned long *) dst1;
+	dst2 = (u32 *) dst1;
 
 	for (i = image->height; i--; ) {
-		dst = (unsigned long *) dst1;
-		j = image->width;
 		shift = val = 0;
-		s = src;
 		l = 8;
+		j = image->width;
+		dst = (u32 *) dst1;
+		s = src;
 
 		/* write leading bits */
 		if (start_index) {
-			unsigned long start_mask = ~(SHIFT_HIGH(~0UL,
-								start_index));
+			u32 start_mask = ~(SHIFT_HIGH(~(u32)0, start_index));
 			val = FB_READL(dst) & start_mask;
 			shift = start_index;
 		}
@@ -203,16 +184,16 @@ static inline void slow_imageblit(const struct fb_image *image,
 			if (shift >= null_bits) {
 				FB_WRITEL(val, dst++);
 				val = (shift == null_bits) ? 0 :
-					 SHIFT_LOW(color,BITS_PER_LONG - shift);
+					 SHIFT_LOW(color,32 - shift);
 			}
 			shift += bpp;
-			shift &= (BITS_PER_LONG - 1);
+			shift &= (32 - 1);
 			if (!l) { l = 8; s++; };
 		}
 
 		/* write trailing bits */
  		if (shift) {
-			unsigned long end_mask = SHIFT_HIGH(~0UL, shift);
+			u32 end_mask = SHIFT_HIGH(~(u32)0, shift);
 
 			FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
 		}
@@ -222,10 +203,10 @@ static inline void slow_imageblit(const struct fb_image *image,
 		if (pitch_index) {
 			dst2 += pitch;
 			dst1 = (char *) dst2;
-			(unsigned long) dst1 &= ~(sizeof(unsigned long) - 1);
+			(unsigned long) dst1 &= ~(sizeof(u32) - 1);
 
 			start_index += pitch_index;
-			start_index &= BITS_PER_LONG - 1;
+			start_index &= 32 - 1;
 		}
 		
 	}
@@ -239,15 +220,15 @@ static inline void slow_imageblit(const struct fb_image *image,
  *           fix->line_legth is divisible by 4;
  *           beginning and end of a scanline is dword aligned
  */
-static inline void fast_imageblit(const struct fb_image *image, 
-				  struct fb_info *p, u8 *dst1, 
-				  u32 fgcolor, u32 bgcolor) 
+static inline void fast_imageblit(const struct fb_image *image, struct fb_info *p, 
+				  u8 *dst1, u32 fgcolor, 
+				  u32 bgcolor) 
 {
 	u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel;
-	u32 ppw = BITS_PER_LONG/bpp, spitch = (image->width + 7)/8;
+	u32 ppw = 32/bpp, spitch = (image->width + 7)/8;
 	u32 bit_mask, end_mask, eorx, shift;
 	const char *s = image->data, *src;
-	unsigned long *dst;
+	u32 *dst;
 	u32 *tab = NULL;
 	int i, j, k;
 		
@@ -275,14 +256,12 @@ static inline void fast_imageblit(const struct fb_image *image,
 	k = image->width/ppw;
 
 	for (i = image->height; i--; ) {
-		INIT_FASTPATH;
-
-		dst = (unsigned long *) dst1, shift = 8; src = s;
+		dst = (u32 *) dst1, shift = 8; src = s;
 		
 		for (j = k; j--; ) {
 			shift -= ppw;
 			end_mask = tab[(*src >> shift) & bit_mask];
-			FASTPATH;
+			FB_WRITEL((end_mask & eorx)^bgx, dst++);
 			if (!shift) { shift = 8; src++; }		
 		}
 		dst1 += p->fix.line_length;
@@ -292,8 +271,8 @@ static inline void fast_imageblit(const struct fb_image *image,
 	
 void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
 {
-	unsigned long fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
-	unsigned long bpl = sizeof(unsigned long), bpp = p->var.bits_per_pixel;
+	u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
+	u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel;
 	u32 width = image->width, height = image->height; 
 	u32 dx = image->dx, dy = image->dy;
 	int x2, y2, vxres, vyres;
@@ -319,7 +298,7 @@ void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
 	height = y2 - dy;
 
 	bitstart = (dy * p->fix.line_length * 8) + (dx * bpp);
-	start_index = bitstart & (BITS_PER_LONG - 1);
+	start_index = bitstart & (32 - 1);
 	pitch_index = (p->fix.line_length & (bpl - 1)) * 8;
 
 	bitstart /= 8;
@@ -339,14 +318,14 @@ void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
 			bgcolor = image->bg_color;
 		}	
 		
-		if (BITS_PER_LONG % bpp == 0 && !start_index && !pitch_index && 
-		    ((width & (BITS_PER_LONG/bpp-1)) == 0) &&
+		if (32 % bpp == 0 && !start_index && !pitch_index && 
+		    ((width & (32/bpp-1)) == 0) &&
 		    bpp >= 8 && bpp <= 32) 			
 			fast_imageblit(image, p, dst1, fgcolor, bgcolor);
 		else 
 			slow_imageblit(image, p, dst1, fgcolor, bgcolor,
 					start_index, pitch_index);
-	} else if (image->depth <= bpp) 
+	} else if (image->depth == bpp) 
 		color_imageblit(image, p, dst1, start_index, pitch_index);
 }
 

include/asm-sparc/page.h

@@ -24,7 +24,6 @@
 
 #ifdef __KERNEL__
 
-/* #include <asm/head.h> XXX */      /* for KERNBASE */
 #include <asm/btfixup.h>
 
 #ifndef __ASSEMBLY__

include/video/mach64.h

@@ -558,7 +558,7 @@
 #define CRTC_CSYNC_EN		0x00000010
 #define CRTC_PIX_BY_2_EN	0x00000020	/* unused on RAGE */
 #define CRTC_DISPLAY_DIS	0x00000040
-#define CRTC_VGA_XOVERSCAN	0x00000080
+#define CRTC_VGA_XOVERSCAN	0x00000040
 
 #define CRTC_PIX_WIDTH_MASK	0x00000700
 #define CRTC_PIX_WIDTH_4BPP	0x00000100
@@ -849,19 +849,7 @@
 #define LI_CHIP_ID	0x4c49	/* RAGE LT PRO */
 #define LP_CHIP_ID	0x4c50	/* RAGE LT PRO */
 #define LT_CHIP_ID	0x4c54	/* RAGE LT */
-
-/* mach64CT family / (Rage XL) class */
-#define GR_CHIP_ID	0x4752	/* RAGE XL, BGA, PCI33 */
-#define GS_CHIP_ID	0x4753	/* RAGE XL, PQFP, PCI33 */
-#define GM_CHIP_ID	0x474d	/* RAGE XL, BGA, AGP 1x,2x */
-#define GN_CHIP_ID	0x474e	/* RAGE XL, PQFP,AGP 1x,2x */
-#define GO_CHIP_ID	0x474f	/* RAGE XL, BGA, PCI66 */
-#define GL_CHIP_ID	0x474c	/* RAGE XL, PQFP, PCI66 */
-
-#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
-		   (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
-		   (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)	
-
+#define XL_CHIP_ID	0x4752	/* RAGE (XL) */
 #define GT_CHIP_ID	0x4754	/* RAGE (GT) */
 #define GU_CHIP_ID	0x4755	/* RAGE II/II+ (GTB) */
 #define GV_CHIP_ID	0x4756	/* RAGE IIC, PCI */
@@ -1160,65 +1148,6 @@
 #define APC_LUT_MN		0x39
 #define APC_LUT_OP		0x3A
 
-/* Values in LCD_GEN_CTRL */
-#define CRT_ON                          0x00000001ul
-#define LCD_ON                          0x00000002ul
-#define HORZ_DIVBY2_EN                  0x00000004ul
-#define DONT_DS_ICON                    0x00000008ul
-#define LOCK_8DOT                       0x00000010ul
-#define ICON_ENABLE                     0x00000020ul
-#define DONT_SHADOW_VPAR                0x00000040ul
-#define V2CLK_PM_EN                     0x00000080ul
-#define RST_FM                          0x00000100ul
-#define DISABLE_PCLK_RESET              0x00000200ul    /* XC/XL */
-#define DIS_HOR_CRT_DIVBY2              0x00000400ul
-#define SCLK_SEL                        0x00000800ul
-#define SCLK_DELAY                      0x0000f000ul
-#define TVCLK_PM_EN                     0x00010000ul
-#define VCLK_DAC_PM_EN                  0x00020000ul
-#define VCLK_LCD_OFF                    0x00040000ul
-#define SELECT_WAIT_4MS                 0x00080000ul
-#define XTALIN_PM_EN                    0x00080000ul    /* XC/XL */
-#define V2CLK_DAC_PM_EN                 0x00100000ul
-#define LVDS_EN                         0x00200000ul
-#define LVDS_PLL_EN                     0x00400000ul
-#define LVDS_PLL_RESET                  0x00800000ul
-#define LVDS_RESERVED_BITS              0x07000000ul
-#define CRTC_RW_SELECT                  0x08000000ul    /* LTPro */
-#define USE_SHADOWED_VEND               0x10000000ul
-#define USE_SHADOWED_ROWCUR             0x20000000ul
-#define SHADOW_EN                       0x40000000ul
-#define SHADOW_RW_EN                    0x80000000ul
-
-/* Values in HORZ_STRETCHING */
-#define HORZ_STRETCH_BLEND              0x00000ffful
-#define HORZ_STRETCH_RATIO              0x0000fffful
-#define HORZ_STRETCH_LOOP               0x00070000ul
-#define HORZ_STRETCH_LOOP09                     0x00000000ul
-#define HORZ_STRETCH_LOOP11                     0x00010000ul
-#define HORZ_STRETCH_LOOP12                     0x00020000ul
-#define HORZ_STRETCH_LOOP14                     0x00030000ul
-#define HORZ_STRETCH_LOOP15                     0x00040000ul
-/*      ?                                       0x00050000ul */
-/*      ?                                       0x00060000ul */
-/*      ?                                       0x00070000ul */
-/*      ?                               0x00080000ul */
-#define HORZ_PANEL_SIZE                 0x0ff00000ul    /* XC/XL */
-/*      ?                               0x10000000ul */
-#define AUTO_HORZ_RATIO                 0x20000000ul    /* XC/XL */
-#define HORZ_STRETCH_MODE               0x40000000ul
-#define HORZ_STRETCH_EN                 0x80000000ul
-
-/* Values in VERT_STRETCHING */
-#define VERT_STRETCH_RATIO0             0x000003fful
-#define VERT_STRETCH_RATIO1             0x000ffc00ul
-#define VERT_STRETCH_RATIO2             0x3ff00000ul
-#define VERT_STRETCH_USE0               0x40000000ul
-#define VERT_STRETCH_EN                 0x80000000ul
-
-/* Values in EXT_VERT_STRETCH */
-#define AUTO_VERT_RATIO                 0x00400000ul
-#define VERT_STRETCH_MODE		0x00000400ul
 
 /* Values in LCD_MISC_CNTL */
 #define BIAS_MOD_LEVEL_MASK	0x0000ff00